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[picodrive.git] / Pico / cd / LC89510.c
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bf098bc5 1/***********************************************************\r
2 * *\r
3 * This source is taken from the Gens project *\r
4 * Written by Stéphane Dallongeville *\r
5 * Copyright (c) 2002 by Stéphane Dallongeville *\r
6 * Modified/adapted for Picodrive by notaz, 2007 *\r
7 * *\r
8 ***********************************************************/\r
cc68a136 9\r
10#include "../PicoInt.h"\r
11\r
c459aefd 12#define cdprintf dprintf\r
cc68a136 13//#define cdprintf(x...)\r
14\r
15\r
16#define CDC_DMA_SPEED 256\r
17\r
c459aefd 18int CDC_Decode_Reg_Read; // 2 context?\r
cc68a136 19\r
20\r
21static void CDD_Reset(void)\r
22{\r
23 // Reseting CDD\r
24\r
25 memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
26 Pico_mcd->cdd.Status = 0;\r
27 Pico_mcd->cdd.Minute = 0;\r
28 Pico_mcd->cdd.Seconde = 0;\r
29 Pico_mcd->cdd.Frame = 0;\r
30 Pico_mcd->cdd.Ext = 0;\r
31\r
32 // clear receive status and transfer command\r
33 memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
34 Pico_mcd->s68k_regs[0x38+9] = 0xF; // Default checksum\r
35}\r
36\r
37\r
38static void CDC_Reset(void)\r
39{\r
40 // Reseting CDC\r
41\r
42 memset(Pico_mcd->cdc.Buffer, 0, (16 * 1024 * 2) + 2352);\r
43\r
44 CDC_Update_Header();\r
45\r
46 Pico_mcd->cdc.COMIN = 0;\r
47 Pico_mcd->cdc.IFSTAT = 0xFF;\r
48 Pico_mcd->cdc.DAC.N = 0;\r
49 Pico_mcd->cdc.DBC.N = 0;\r
50 Pico_mcd->cdc.HEAD.N = 0x01000000;\r
51 Pico_mcd->cdc.PT.N = 0;\r
52 Pico_mcd->cdc.WA.N = 2352 * 2;\r
53 Pico_mcd->cdc.STAT.N = 0x00000080;\r
54 Pico_mcd->cdc.SBOUT = 0;\r
55 Pico_mcd->cdc.IFCTRL = 0;\r
56 Pico_mcd->cdc.CTRL.N = 0;\r
57\r
58 CDC_Decode_Reg_Read = 0;\r
c459aefd 59 Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136 60}\r
61\r
62\r
63void LC89510_Reset(void)\r
64{\r
65 CDD_Reset();\r
66 CDC_Reset();\r
67\r
68 Pico_mcd->cdc.Host_Data = 0;\r
69 Pico_mcd->cdc.DMA_Adr = 0;\r
70 Pico_mcd->cdc.Stop_Watch = 0;\r
71}\r
72\r
cc68a136 73\r
bf098bc5 74void Update_CDC_TRansfer(int which)\r
75{\r
76 unsigned int dep, length, len;\r
77 unsigned short *dest;\r
78 unsigned char *src;\r
cc68a136 79\r
80 if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
81 {\r
bf098bc5 82 length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
c459aefd 83 Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
bf098bc5 84 Pico_mcd->s68k_regs[4] |= 0x80; // End data transfer\r
85 Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
86 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
cc68a136 87\r
bf098bc5 88 if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Trasnfer End Interrupt Enable ?\r
cc68a136 89 {\r
90 Pico_mcd->cdc.IFSTAT &= ~0x40;\r
91\r
bf098bc5 92 if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
93 {\r
94 dprintf("cdc DTE irq 5");\r
95 SekInterruptS68k(5);\r
96 }\r
cc68a136 97 }\r
98 }\r
bf098bc5 99 else length = CDC_DMA_SPEED;\r
100\r
cc68a136 101\r
bf098bc5 102 // TODO: dst bounds checking? DAC.N alignment?\r
103 src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
cc68a136 104\r
105\r
bf098bc5 106 if (which == 7) // WORD RAM\r
cc68a136 107 {\r
bf098bc5 108 if (Pico_mcd->s68k_regs[3] & 4)\r
cc68a136 109 {\r
bf098bc5 110 dep = ((Pico_mcd->cdc.DMA_Adr & 0x3FFF) << 3);\r
111 cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
112 Pico_mcd->cdc.DAC.N, dep, length);\r
113\r
114 dep = ((Pico_mcd->cdc.DMA_Adr & 0x3FFF) << 4);\r
115 if (!(Pico_mcd->s68k_regs[3]&1)) dep += 2;\r
116 dest = (unsigned short *) (Pico_mcd->word_ram + dep);\r
117\r
118 for (len = length; len > 0; len--, src+=2, dest+=2)\r
119 *dest = (src[0]<<8) | src[1];\r
cc68a136 120 }\r
bf098bc5 121 else\r
122 {\r
123 dep = ((Pico_mcd->cdc.DMA_Adr & 0x7FFF) << 3);\r
124 cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
125 Pico_mcd->cdc.DAC.N, dep, length);\r
126 dest = (unsigned short *) (Pico_mcd->word_ram + dep);\r
cc68a136 127\r
bf098bc5 128 for (len = length; len > 0; len--, src+=2, dest++)\r
129 *dest = (src[0]<<8) | src[1];\r
130 }\r
cc68a136 131 }\r
bf098bc5 132 else if (which == 4) // PCM RAM\r
cc68a136 133 {\r
bf098bc5 134#if 0\r
135 dest = (unsigned char *) Ram_PCM;\r
136 dep = ((Pico_mcd->cdc.DMA_Adr & 0x03FF) << 2) + PCM_Chip.Bank;\r
137#else\r
138 cdprintf("TODO: PCM Dma");\r
139#endif\r
140 }\r
141 else if (which == 5) // PRG RAM\r
142 {\r
143 dep = (Pico_mcd->cdc.DMA_Adr & 0xFFFF) << 3;\r
144 dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
145 cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
146 Pico_mcd->cdc.DAC.N, dep, length);\r
cc68a136 147\r
bf098bc5 148 for (len = length; len > 0; len--, src+=2, dest++)\r
149 *dest = (src[0]<<8) | src[1];\r
cc68a136 150 }\r
151\r
bf098bc5 152 length <<= 1;\r
153 Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
c459aefd 154 if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
cc68a136 155 else Pico_mcd->cdc.DBC.N = 0;\r
156}\r
cc68a136 157\r
158\r
159unsigned short Read_CDC_Host(int is_sub)\r
160{\r
161 int addr;\r
162\r
c459aefd 163 if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
cc68a136 164 {\r
165 // Transfer data disabled\r
c459aefd 166 cdprintf("Read_CDC_Host: Transfer data disabled");\r
cc68a136 167 return 0;\r
168 }\r
169\r
170 if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) ||\r
171 (!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
172 {\r
173 // Wrong setting\r
c459aefd 174 cdprintf("Read_CDC_Host: Wrong setting");\r
cc68a136 175 return 0;\r
176 }\r
177\r
178 Pico_mcd->cdc.DBC.N -= 2;\r
179\r
180 if (Pico_mcd->cdc.DBC.N <= 0)\r
181 {\r
182 Pico_mcd->cdc.DBC.N = 0;\r
c459aefd 183 Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
cc68a136 184 Pico_mcd->s68k_regs[4] |= 0x80; // End data transfer\r
185 Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
186 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
187\r
188 if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Transfer End Interrupt Enable ?\r
189 {\r
190 Pico_mcd->cdc.IFSTAT &= ~0x40;\r
191\r
192 if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
193 dprintf("m68k: s68k irq 5");\r
194 SekInterruptS68k(5);\r
195 }\r
196\r
c459aefd 197 cdprintf("CDC - DTE interrupt");\r
cc68a136 198 }\r
199 }\r
200\r
201 addr = Pico_mcd->cdc.DAC.N;\r
202 Pico_mcd->cdc.DAC.N += 2;\r
c459aefd 203\r
204 cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
205 (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
206\r
cc68a136 207 return (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1];\r
208\r
209#if 0\r
210 __asm\r
211 {\r
212 mov esi, Pico_mcd->cdc.DAC.N\r
213 lea ebx, Pico_mcd->cdc.Buffer\r
214// and esi, 0x3FFF\r
215 mov ax, [ebx + esi]\r
216 add esi, 2\r
217 rol ax, 8\r
218 mov Pico_mcd->cdc.DAC.N, esi\r
219 mov val, ax\r
220 }\r
221#endif\r
222}\r
223\r
224\r
225void CDC_Update_Header(void)\r
226{\r
227 if (Pico_mcd->cdc.CTRL.B.B1 & 0x01) // Sub-Header wanted ?\r
228 {\r
229 Pico_mcd->cdc.HEAD.B.B0 = 0;\r
230 Pico_mcd->cdc.HEAD.B.B1 = 0;\r
231 Pico_mcd->cdc.HEAD.B.B2 = 0;\r
232 Pico_mcd->cdc.HEAD.B.B3 = 0;\r
233 }\r
234 else\r
235 {\r
236 _msf MSF;\r
237\r
238 LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
239\r
240 Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
241 Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
242 Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
243 Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
244 }\r
245}\r
246\r
247\r
248unsigned char CDC_Read_Reg(void)\r
249{\r
250 unsigned char ret;\r
251\r
cc68a136 252 switch(Pico_mcd->s68k_regs[5] & 0xF)\r
253 {\r
254 case 0x0: // COMIN\r
c459aefd 255 cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
cc68a136 256\r
257 Pico_mcd->s68k_regs[5] = 0x1;\r
258 return Pico_mcd->cdc.COMIN;\r
259\r
260 case 0x1: // IFSTAT\r
c459aefd 261 cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
cc68a136 262\r
263 CDC_Decode_Reg_Read |= (1 << 1); // Reg 1 (decoding)\r
264 Pico_mcd->s68k_regs[5] = 0x2;\r
265 return Pico_mcd->cdc.IFSTAT;\r
266\r
267 case 0x2: // DBCL\r
c459aefd 268 cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
cc68a136 269\r
270 Pico_mcd->s68k_regs[5] = 0x3;\r
271 return Pico_mcd->cdc.DBC.B.L;\r
272\r
273 case 0x3: // DBCH\r
c459aefd 274 cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
cc68a136 275\r
276 Pico_mcd->s68k_regs[5] = 0x4;\r
277 return Pico_mcd->cdc.DBC.B.H;\r
278\r
279 case 0x4: // HEAD0\r
c459aefd 280 cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
cc68a136 281\r
282 CDC_Decode_Reg_Read |= (1 << 4); // Reg 4 (decoding)\r
283 Pico_mcd->s68k_regs[5] = 0x5;\r
284 return Pico_mcd->cdc.HEAD.B.B0;\r
285\r
286 case 0x5: // HEAD1\r
c459aefd 287 cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
cc68a136 288\r
289 CDC_Decode_Reg_Read |= (1 << 5); // Reg 5 (decoding)\r
290 Pico_mcd->s68k_regs[5] = 0x6;\r
291 return Pico_mcd->cdc.HEAD.B.B1;\r
292\r
293 case 0x6: // HEAD2\r
c459aefd 294 cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
cc68a136 295\r
296 CDC_Decode_Reg_Read |= (1 << 6); // Reg 6 (decoding)\r
297 Pico_mcd->s68k_regs[5] = 0x7;\r
298 return Pico_mcd->cdc.HEAD.B.B2;\r
299\r
300 case 0x7: // HEAD3\r
c459aefd 301 cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
cc68a136 302\r
303 CDC_Decode_Reg_Read |= (1 << 7); // Reg 7 (decoding)\r
304 Pico_mcd->s68k_regs[5] = 0x8;\r
305 return Pico_mcd->cdc.HEAD.B.B3;\r
306\r
307 case 0x8: // PTL\r
c459aefd 308 cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
cc68a136 309\r
310 CDC_Decode_Reg_Read |= (1 << 8); // Reg 8 (decoding)\r
311 Pico_mcd->s68k_regs[5] = 0x9;\r
312 return Pico_mcd->cdc.PT.B.L;\r
313\r
314 case 0x9: // PTH\r
c459aefd 315 cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
cc68a136 316\r
317 CDC_Decode_Reg_Read |= (1 << 9); // Reg 9 (decoding)\r
318 Pico_mcd->s68k_regs[5] = 0xA;\r
319 return Pico_mcd->cdc.PT.B.H;\r
320\r
321 case 0xA: // WAL\r
c459aefd 322 cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
cc68a136 323\r
324 Pico_mcd->s68k_regs[5] = 0xB;\r
325 return Pico_mcd->cdc.WA.B.L;\r
326\r
327 case 0xB: // WAH\r
c459aefd 328 cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
cc68a136 329\r
330 Pico_mcd->s68k_regs[5] = 0xC;\r
331 return Pico_mcd->cdc.WA.B.H;\r
332\r
333 case 0xC: // STAT0\r
c459aefd 334 cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
cc68a136 335\r
336 CDC_Decode_Reg_Read |= (1 << 12); // Reg 12 (decoding)\r
337 Pico_mcd->s68k_regs[5] = 0xD;\r
338 return Pico_mcd->cdc.STAT.B.B0;\r
339\r
340 case 0xD: // STAT1\r
c459aefd 341 cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
cc68a136 342\r
343 CDC_Decode_Reg_Read |= (1 << 13); // Reg 13 (decoding)\r
344 Pico_mcd->s68k_regs[5] = 0xE;\r
345 return Pico_mcd->cdc.STAT.B.B1;\r
346\r
347 case 0xE: // STAT2\r
c459aefd 348 cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
cc68a136 349\r
350 CDC_Decode_Reg_Read |= (1 << 14); // Reg 14 (decoding)\r
351 Pico_mcd->s68k_regs[5] = 0xF;\r
352 return Pico_mcd->cdc.STAT.B.B2;\r
353\r
354 case 0xF: // STAT3\r
c459aefd 355 cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
cc68a136 356\r
357 ret = Pico_mcd->cdc.STAT.B.B3;\r
358 Pico_mcd->cdc.IFSTAT |= 0x20; // decoding interrupt flag cleared\r
359 if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
360 {\r
361 if ((CDC_Decode_Reg_Read & 0x73F2) == 0x73F2)\r
362 Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
363 }\r
364 return ret;\r
365 }\r
366\r
367 return 0;\r
368}\r
369\r
370\r
371void CDC_Write_Reg(unsigned char Data)\r
372{\r
c459aefd 373 cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
cc68a136 374\r
375 switch (Pico_mcd->s68k_regs[5] & 0xF)\r
376 {\r
377 case 0x0: // SBOUT\r
378 Pico_mcd->s68k_regs[5] = 0x1;\r
379 Pico_mcd->cdc.SBOUT = Data;\r
380\r
381 break;\r
382\r
383 case 0x1: // IFCTRL\r
384 Pico_mcd->s68k_regs[5] = 0x2;\r
385 Pico_mcd->cdc.IFCTRL = Data;\r
386\r
387 if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0) // Stop data transfer\r
388 {\r
389 Pico_mcd->cdc.DBC.N = 0;\r
c459aefd 390 Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136 391 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
392 }\r
393 break;\r
394\r
395 case 0x2: // DBCL\r
396 Pico_mcd->s68k_regs[5] = 0x3;\r
397 Pico_mcd->cdc.DBC.B.L = Data;\r
398\r
399 break;\r
400\r
401 case 0x3: // DBCH\r
402 Pico_mcd->s68k_regs[5] = 0x4;\r
403 Pico_mcd->cdc.DBC.B.H = Data;\r
404\r
405 break;\r
406\r
407 case 0x4: // DACL\r
408 Pico_mcd->s68k_regs[5] = 0x5;\r
409 Pico_mcd->cdc.DAC.B.L = Data;\r
410\r
411 break;\r
412\r
413 case 0x5: // DACH\r
414 Pico_mcd->s68k_regs[5] = 0x6;\r
415 Pico_mcd->cdc.DAC.B.H = Data;\r
416\r
417 break;\r
418\r
419 case 0x6: // DTTRG\r
420 if (Pico_mcd->cdc.IFCTRL & 0x02) // Data transfer enable ?\r
421 {\r
422 Pico_mcd->cdc.IFSTAT &= ~0x08; // Data transfer in progress\r
c459aefd 423 Pico_mcd->scd.Status_CDC |= 0x08; // Data transfer in progress\r
cc68a136 424 Pico_mcd->s68k_regs[4] &= 0x7F; // A data transfer start\r
425\r
c459aefd 426 cdprintf("************** Starting Data Transfer ***********");\r
cc68a136 427 cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
428 Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, Pico_mcd->cdc.DMA_Adr);\r
429 }\r
430 break;\r
431\r
432 case 0x7: // DTACK\r
433 Pico_mcd->cdc.IFSTAT |= 0x40; // end data transfer interrupt flag cleared\r
434 break;\r
435\r
436 case 0x8: // WAL\r
437 Pico_mcd->s68k_regs[5] = 0x9;\r
438 Pico_mcd->cdc.WA.B.L = Data;\r
439\r
440 break;\r
441\r
442 case 0x9: // WAH\r
443 Pico_mcd->s68k_regs[5] = 0xA;\r
444 Pico_mcd->cdc.WA.B.H = Data;\r
445\r
446 break;\r
447\r
448 case 0xA: // CTRL0\r
449 Pico_mcd->s68k_regs[5] = 0xB;\r
450 Pico_mcd->cdc.CTRL.B.B0 = Data;\r
451\r
452 break;\r
453\r
454 case 0xB: // CTRL1\r
455 Pico_mcd->s68k_regs[5] = 0xC;\r
456 Pico_mcd->cdc.CTRL.B.B1 = Data;\r
457\r
458 break;\r
459\r
460 case 0xC: // PTL\r
461 Pico_mcd->s68k_regs[5] = 0xD;\r
462 Pico_mcd->cdc.PT.B.L = Data;\r
463\r
464 break;\r
465\r
466 case 0xD: // PTH\r
467 Pico_mcd->s68k_regs[5] = 0xE;\r
468 Pico_mcd->cdc.PT.B.H = Data;\r
469\r
470 break;\r
471\r
472 case 0xE: // CTRL2\r
473 Pico_mcd->cdc.CTRL.B.B2 = Data;\r
474 break;\r
475\r
476 case 0xF: // RESET\r
477 CDC_Reset();\r
478 break;\r
479 }\r
480}\r
481\r
482\r
483static int bswapwrite(int a, unsigned short d)\r
484{\r
485 *(unsigned short *)(Pico_mcd->s68k_regs + a) = (d>>8)|(d<<8);\r
486 return d + (d >> 8);\r
487}\r
488\r
489void CDD_Export_Status(void)\r
490{\r
491 unsigned int csum;\r
492\r
493 csum = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
494 csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
495 csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
496 csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
497 Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
498 csum += Pico_mcd->cdd.Ext;\r
499 Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
500\r
672ad671 501 Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
cc68a136 502\r
503 if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
504 {\r
505 dprintf("cdd export irq 4");\r
506 SekInterruptS68k(4);\r
507 }\r
508\r
c459aefd 509// cdprintf("CDD exported status\n");\r
510 cdprintf("out: Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136 511 (Pico_mcd->s68k_regs[0x38+0] << 8) | Pico_mcd->s68k_regs[0x38+1],\r
512 (Pico_mcd->s68k_regs[0x38+2] << 8) | Pico_mcd->s68k_regs[0x38+3],\r
513 (Pico_mcd->s68k_regs[0x38+4] << 8) | Pico_mcd->s68k_regs[0x38+5],\r
514 (Pico_mcd->s68k_regs[0x38+6] << 8) | Pico_mcd->s68k_regs[0x38+7],\r
515 (Pico_mcd->s68k_regs[0x38+8] << 8) | Pico_mcd->s68k_regs[0x38+9]);\r
516}\r
517\r
518\r
519void CDD_Import_Command(void)\r
520{\r
c459aefd 521// cdprintf("CDD importing command\n");\r
522 cdprintf("in: Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136 523 (Pico_mcd->s68k_regs[0x38+10+0] << 8) | Pico_mcd->s68k_regs[0x38+10+1],\r
524 (Pico_mcd->s68k_regs[0x38+10+2] << 8) | Pico_mcd->s68k_regs[0x38+10+3],\r
525 (Pico_mcd->s68k_regs[0x38+10+4] << 8) | Pico_mcd->s68k_regs[0x38+10+5],\r
526 (Pico_mcd->s68k_regs[0x38+10+6] << 8) | Pico_mcd->s68k_regs[0x38+10+7],\r
527 (Pico_mcd->s68k_regs[0x38+10+8] << 8) | Pico_mcd->s68k_regs[0x38+10+9]);\r
528\r
529 switch (Pico_mcd->s68k_regs[0x38+10+0])\r
530 {\r
531 case 0x0: // STATUS (?)\r
532 Get_Status_CDD_c0();\r
533 break;\r
534\r
535 case 0x1: // STOP ALL (?)\r
536 Stop_CDD_c1();\r
537 break;\r
538\r
539 case 0x2: // GET TOC INFORMATIONS\r
540 switch(Pico_mcd->s68k_regs[0x38+10+3])\r
541 {\r
542 case 0x0: // get current position (MSF format)\r
543 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
544 Get_Pos_CDD_c20();\r
545 break;\r
546\r
547 case 0x1: // get elapsed time of current track played/scanned (relative MSF format)\r
548 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 1;\r
549 Get_Track_Pos_CDD_c21();\r
550 break;\r
551\r
552 case 0x2: // get current track in RS2-RS3\r
553 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 2;\r
554 Get_Current_Track_CDD_c22();\r
555 break;\r
556\r
bf098bc5 557 case 0x3: // get total length (MSF format)\r
cc68a136 558 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 3;\r
559 Get_Total_Lenght_CDD_c23();\r
560 break;\r
561\r
562 case 0x4: // first & last track number\r
563 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 4;\r
564 Get_First_Last_Track_CDD_c24();\r
565 break;\r
566\r
567 case 0x5: // get track addresse (MSF format)\r
568 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 5;\r
569 Get_Track_Adr_CDD_c25();\r
570 break;\r
571\r
572 default : // invalid, then we return status\r
573 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 0xF;\r
574 Get_Status_CDD_c0();\r
575 break;\r
576 }\r
577 break;\r
578\r
579 case 0x3: // READ\r
580 Play_CDD_c3();\r
581 break;\r
582\r
583 case 0x4: // SEEK\r
584 Seek_CDD_c4();\r
585 break;\r
586\r
587 case 0x6: // PAUSE/STOP\r
588 Pause_CDD_c6();\r
589 break;\r
590\r
591 case 0x7: // RESUME\r
592 Resume_CDD_c7();\r
593 break;\r
594\r
595 case 0x8: // FAST FOWARD\r
596 Fast_Foward_CDD_c8();\r
597 break;\r
598\r
599 case 0x9: // FAST REWIND\r
600 Fast_Rewind_CDD_c9();\r
601 break;\r
602\r
603 case 0xA: // RECOVER INITIAL STATE (?)\r
604 CDD_cA();\r
605 break;\r
606\r
607 case 0xC: // CLOSE TRAY\r
608 Close_Tray_CDD_cC();\r
609 break;\r
610\r
611 case 0xD: // OPEN TRAY\r
612 Open_Tray_CDD_cD();\r
613 break;\r
614\r
615 default: // UNKNOWN\r
616 CDD_Def();\r
617 break;\r
618 }\r
619}\r
620\r
fast MegaDrive/MegaCD/32X emulator