notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Sonic CD shows it's title screen
[picodrive.git] / Pico / cd / Memory.c
CommitLineData
cc68a136 1// This is part of Pico Library\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4// (c) Copyright 2006 notaz, All rights reserved.\r
5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9// A68K no longer supported here\r
10\r
11//#define __debug_io\r
12\r
13#include "../PicoInt.h"\r
14\r
15#include "../sound/sound.h"\r
16#include "../sound/ym2612.h"\r
17#include "../sound/sn76496.h"\r
18\r
cb4a513a 19#include "gfx_cd.h"\r
20\r
cc68a136 21typedef unsigned char u8;\r
22typedef unsigned short u16;\r
23typedef unsigned int u32;\r
24\r
25//#define __debug_io\r
26//#define __debug_io2\r
ab0607f7 27#define rdprintf dprintf\r
28//#define rdprintf(...)\r
cc68a136 29\r
30// -----------------------------------------------------------------\r
31\r
8c1952f0 32// extern m68ki_cpu_core m68ki_cpu;\r
cc68a136 33\r
34extern int counter75hz;\r
35\r
36\r
cb4a513a 37static u32 m68k_reg_read16(u32 a)\r
cc68a136 38{\r
39 u32 d=0;\r
40 a &= 0x3e;\r
672ad671 41 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);\r
cc68a136 42\r
43 switch (a) {\r
672ad671 44 case 0:\r
c459aefd 45 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens\r
672ad671 46 goto end;\r
cc68a136 47 case 2:\r
672ad671 48 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
bf098bc5 49 dprintf("m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
cc68a136 50 goto end;\r
c459aefd 51 case 4:\r
52 d = Pico_mcd->s68k_regs[4]<<8;\r
53 goto end;\r
54 case 6:\r
55 d = Pico_mcd->m.hint_vector;\r
56 goto end;\r
cc68a136 57 case 8:\r
cc68a136 58 d = Read_CDC_Host(0);\r
59 goto end;\r
c459aefd 60 case 0xA:\r
61 dprintf("m68k reserved read");\r
62 goto end;\r
cc68a136 63 case 0xC:\r
64 dprintf("m68k stopwatch read");\r
65 break;\r
66 }\r
67\r
cc68a136 68 if (a < 0x30) {\r
69 // comm flag/cmd/status (0xE-0x2F)\r
70 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
71 goto end;\r
72 }\r
73\r
74 dprintf("m68k_regs invalid read @ %02x", a);\r
75\r
76end:\r
77\r
672ad671 78 // dprintf("ret = %04x", d);\r
cc68a136 79 return d;\r
80}\r
81\r
cb4a513a 82static void m68k_reg_write8(u32 a, u32 d)\r
cc68a136 83{\r
84 a &= 0x3f;\r
672ad671 85 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);\r
cc68a136 86\r
87 switch (a) {\r
88 case 0:\r
672ad671 89 d &= 1;\r
cc68a136 90 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }\r
c459aefd 91 return;\r
cc68a136 92 case 1:\r
672ad671 93 d &= 3;\r
cc68a136 94 if (!(d&1)) PicoMCD |= 2; // reset pending, needed to be sure we fetch the right vectors on reset\r
c459aefd 95 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));\r
96 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);\r
97 if ((PicoMCD&2) && (d&3)==1) {\r
cc68a136 98 SekResetS68k(); // S68k comes out of RESET or BRQ state\r
99 PicoMCD&=~2;\r
672ad671 100 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);\r
cc68a136 101 }\r
c459aefd 102 Pico_mcd->m.busreq = d;\r
103 return;\r
672ad671 104 case 2:\r
105 Pico_mcd->s68k_regs[2] = d; // really use s68k side register\r
106 return;\r
cc68a136 107 case 3:\r
bf098bc5 108 dprintf("m68k_regs w3: %02x @%06x", (u8)d, SekPc);\r
672ad671 109 d &= 0xc2;\r
110 if ((Pico_mcd->s68k_regs[3]>>6) != ((d>>6)&3))\r
111 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
112 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);\r
113 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :\r
114 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));\r
115 d |= Pico_mcd->s68k_regs[3]&0x1d;\r
d0d47c5b 116 if (!(d & 4) && (d & 2)) d &= ~1; // return word RAM to s68k in 2M mode\r
672ad671 117 Pico_mcd->s68k_regs[3] = d; // really use s68k side register\r
118 return;\r
c459aefd 119 case 6:\r
120 *((char *)&Pico_mcd->m.hint_vector+1) = d;\r
121 return;\r
122 case 7:\r
123 *(char *)&Pico_mcd->m.hint_vector = d;\r
124 return;\r
cc68a136 125 case 0xe:\r
672ad671 126 //dprintf("m68k: comm flag: %02x", d);\r
cc68a136 127\r
672ad671 128 //dprintf("s68k @ %06x", SekPcS68k);\r
cc68a136 129\r
130 Pico_mcd->s68k_regs[0xe] = d;\r
c459aefd 131 return;\r
672ad671 132 }\r
133\r
134 if ((a&0xf0) == 0x10) {\r
cc68a136 135 Pico_mcd->s68k_regs[a] = d;\r
672ad671 136 return;\r
cc68a136 137 }\r
138\r
c459aefd 139 dprintf("m68k: invalid write? [%02x] %02x", a, d);\r
cc68a136 140}\r
141\r
142\r
143\r
cb4a513a 144static u32 s68k_reg_read16(u32 a)\r
cc68a136 145{\r
146 u32 d=0;\r
cc68a136 147\r
672ad671 148 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);\r
cc68a136 149\r
150 switch (a) {\r
151 case 0:\r
cb4a513a 152 d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state\r
c459aefd 153 goto end;\r
672ad671 154 case 2:\r
155 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0x1f);\r
bf098bc5 156 dprintf("s68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
672ad671 157 goto end;\r
cc68a136 158 case 6:\r
159 d = CDC_Read_Reg();\r
160 goto end;\r
161 case 8:\r
cb4a513a 162 d = Read_CDC_Host(1); // Gens returns 0 here on byte reads\r
cc68a136 163 goto end;\r
164 case 0xC:\r
165 dprintf("s68k stopwatch read");\r
166 break;\r
167 case 0x34: // fader\r
168 d = 0; // no busy bit\r
169 goto end;\r
170 }\r
171\r
172 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
173\r
174end:\r
175\r
672ad671 176 // dprintf("ret = %04x", d);\r
cc68a136 177\r
178 return d;\r
179}\r
180\r
cb4a513a 181static void s68k_reg_write8(u32 a, u32 d)\r
cc68a136 182{\r
672ad671 183 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);\r
cc68a136 184\r
185 // TODO: review against Gens\r
186 switch (a) {\r
672ad671 187 case 2:\r
188 return; // only m68k can change WP\r
189 case 3:\r
bf098bc5 190 dprintf("s68k_regs w3: %02x @%06x", (u8)d, SekPc);\r
672ad671 191 d &= 0x1d;\r
d0d47c5b 192 if (d&4) {\r
193 d |= Pico_mcd->s68k_regs[3]&0xc2;\r
194 if ((d ^ Pico_mcd->s68k_regs[3]) & 5) d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit\r
195 } else {\r
196 d |= Pico_mcd->s68k_regs[3]&0xc3;\r
197 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode\r
198 }\r
672ad671 199 break;\r
cc68a136 200 case 4:\r
201 dprintf("s68k CDC dest: %x", d&7);\r
202 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode\r
203 return;\r
204 case 5:\r
c459aefd 205 //dprintf("s68k CDC reg addr: %x", d&0xf);\r
cc68a136 206 break;\r
207 case 7:\r
208 CDC_Write_Reg(d);\r
209 return;\r
210 case 0xa:\r
211 dprintf("s68k set CDC dma addr");\r
212 break;\r
213 case 0x33: // IRQ mask\r
214 dprintf("s68k irq mask: %02x", d);\r
215 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {\r
216 CDD_Export_Status();\r
217 // counter75hz = 0; // ???\r
218 }\r
219 break;\r
220 case 0x34: // fader\r
221 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;\r
222 return;\r
672ad671 223 case 0x36:\r
224 return; // d/m bit is unsetable\r
225 case 0x37: {\r
226 u32 d_old = Pico_mcd->s68k_regs[0x37];\r
227 Pico_mcd->s68k_regs[0x37] = d&7;\r
228 if ((d&4) && !(d_old&4)) {\r
cc68a136 229 CDD_Export_Status();\r
230 // counter75hz = 0; // ???\r
231 }\r
672ad671 232 return;\r
233 }\r
cc68a136 234 case 0x4b:\r
235 Pico_mcd->s68k_regs[a] = (u8) d;\r
236 CDD_Import_Command();\r
237 return;\r
238 }\r
239\r
240 if ((a&0x1f0) == 0x10 || a == 0x0e || (a >= 0x38 && a < 0x42))\r
241 {\r
242 dprintf("m68k: invalid write @ %02x?", a);\r
243 return;\r
244 }\r
245\r
246 Pico_mcd->s68k_regs[a] = (u8) d;\r
247}\r
248\r
249\r
250\r
251\r
252\r
253static int PadRead(int i)\r
254{\r
255 int pad=0,value=0,TH;\r
256 pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU\r
257 TH=Pico.ioports[i+1]&0x40;\r
258\r
259 if(PicoOpt & 0x20) { // 6 button gamepad enabled\r
260 int phase = Pico.m.padTHPhase[i];\r
261\r
262 if(phase == 2 && !TH) {\r
263 value=(pad&0xc0)>>2; // ?0SA 0000\r
264 goto end;\r
265 } else if(phase == 3 && TH) {\r
266 value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r
267 goto end;\r
268 } else if(phase == 3 && !TH) {\r
269 value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r
270 goto end;\r
271 }\r
272 }\r
273\r
274 if(TH) value=(pad&0x3f); // ?1CB RLDU\r
275 else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
276\r
277 end:\r
278\r
279 // orr the bits, which are set as output\r
280 value |= Pico.ioports[i+1]&Pico.ioports[i+4];\r
281\r
282 return value; // will mirror later\r
283}\r
284\r
285static u8 z80Read8(u32 a)\r
286{\r
287 if(Pico.m.z80Run&1) return 0;\r
288\r
289 a&=0x1fff;\r
290\r
291 if(!(PicoOpt&4)) {\r
292 // Z80 disabled, do some faking\r
293 static u8 zerosent = 0;\r
294 if(a == Pico.m.z80_lastaddr) { // probably polling something\r
295 u8 d = Pico.m.z80_fakeval;\r
296 if((d & 0xf) == 0xf && !zerosent) {\r
297 d = 0; zerosent = 1;\r
298 } else {\r
299 Pico.m.z80_fakeval++;\r
300 zerosent = 0;\r
301 }\r
302 return d;\r
303 } else {\r
304 Pico.m.z80_fakeval = 0;\r
305 }\r
306 }\r
307\r
308 Pico.m.z80_lastaddr = (u16) a;\r
309 return Pico.zram[a];\r
310}\r
311\r
312\r
313// for nonstandard reads\r
314static u32 UnusualRead16(u32 a, int realsize)\r
315{\r
316 u32 d=0;\r
317\r
318 dprintf("unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);\r
319\r
320\r
321 dprintf("ret = %04x", d);\r
322 return d;\r
323}\r
324\r
325static u32 OtherRead16(u32 a, int realsize)\r
326{\r
327 u32 d=0;\r
328\r
329 if ((a&0xff0000)==0xa00000) {\r
330 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)\r
331 if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; goto end; } // 0x4000-0x5fff, Fudge if disabled\r
332 d=0xffff; goto end;\r
333 }\r
334 if ((a&0xffffe0)==0xa10000) { // I/O ports\r
335 a=(a>>1)&0xf;\r
336 switch(a) {\r
337 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)\r
338 case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;\r
339 case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;\r
340 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM\r
341 }\r
342 d|=d<<8;\r
343 goto end;\r
344 }\r
345 // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers\r
346 if (a==0xa11100) { d=((Pico.m.z80Run&1)<<8)|0x8000|Pico.m.rotate++; goto end; }\r
347\r
348 if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }\r
349\r
672ad671 350 if ((a&0xffffc0)==0xa12000) {\r
cb4a513a 351 d=m68k_reg_read16(a);\r
672ad671 352 goto end;\r
353 }\r
cc68a136 354\r
355 d = UnusualRead16(a, realsize);\r
356\r
357end:\r
358 return d;\r
359}\r
360\r
361//extern UINT32 mz80GetRegisterValue(void *, UINT32);\r
362\r
363static void OtherWrite8(u32 a,u32 d,int realsize)\r
364{\r
365 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound\r
366 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram\r
367 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound\r
368 if ((a&0xffffe0)==0xa10000) { // I/O ports\r
369 a=(a>>1)&0xf;\r
370 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
371 if(PicoOpt&0x20) {\r
372 if(a==1) {\r
373 Pico.m.padDelay[0] = 0;\r
374 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;\r
375 }\r
376 else if(a==2) {\r
377 Pico.m.padDelay[1] = 0;\r
378 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;\r
379 }\r
380 }\r
381 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM\r
382 return;\r
383 }\r
384 if (a==0xa11100) {\r
385 extern int z80startCycle, z80stopCycle;\r
386 //int lineCycles=(488-SekCyclesLeft)&0x1ff;\r
387 d&=1; d^=1;\r
388 if(!d) {\r
389 // hack: detect a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)\r
390 if((PicoOpt&4) && Pico.m.z80Run==1) z80_run(20);\r
391 z80stopCycle = SekCyclesDone();\r
392 //z80ExtraCycles += (lineCycles>>1)-(lineCycles>>5); // only meaningful in PicoFrameHints()\r
393 } else {\r
394 z80startCycle = SekCyclesDone();\r
395 //if(Pico.m.scanline != -1)\r
396 //z80ExtraCycles -= (lineCycles>>1)-(lineCycles>>5)+16;\r
397 }\r
398 //dprintf("set_zrun: %i [%i|%i] zPC=%04x @%06x", d, Pico.m.scanline, SekCyclesDone(), mz80GetRegisterValue(NULL, 0), SekPc);\r
399 Pico.m.z80Run=(u8)d; return;\r
400 }\r
401 if (a==0xa11200) { if(!(d&1)) z80_reset(); return; }\r
402\r
403 if ((a&0xff7f00)==0xa06000) // Z80 BANK register\r
404 {\r
405 Pico.m.z80_bank68k>>=1;\r
406 Pico.m.z80_bank68k|=(d&1)<<8;\r
407 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one\r
408 return;\r
409 }\r
410\r
411 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored\r
412\r
cb4a513a 413 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }\r
cc68a136 414\r
415 dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
416}\r
417\r
418static void OtherWrite16(u32 a,u32 d)\r
419{\r
420 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }\r
421 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)\r
422\r
423 if ((a&0xffffe0)==0xa10000) { // I/O ports\r
424 a=(a>>1)&0xf;\r
425 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
426 if(PicoOpt&0x20) {\r
427 if(a==1) {\r
428 Pico.m.padDelay[0] = 0;\r
429 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;\r
430 }\r
431 else if(a==2) {\r
432 Pico.m.padDelay[1] = 0;\r
433 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;\r
434 }\r
435 }\r
436 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM\r
437 return;\r
438 }\r
439 if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }\r
440 if (a==0xa11200) { if(!(d&0x100)) z80_reset(); return; }\r
441\r
442 OtherWrite8(a, d>>8, 16);\r
443 OtherWrite8(a+1,d&0xff, 16);\r
444}\r
445\r
446// -----------------------------------------------------------------\r
447// Read Rom and read Ram\r
448\r
449u8 PicoReadM68k8(u32 a)\r
450{\r
451 u32 d=0;\r
452\r
453 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram\r
454\r
455 a&=0xffffff;\r
456\r
457 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios\r
458\r
459 // prg RAM\r
460 if ((a&0xfe0000)==0x020000) {\r
672ad671 461 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 462 d = *(prg_bank+((a^1)&0x1ffff));\r
463 goto end;\r
464 }\r
465\r
d0d47c5b 466 // word RAM\r
467 if ((a&0xfc0000)==0x200000) {\r
468 dprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);\r
469 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 470 if (a >= 0x220000) {\r
471 dprintf("cell");\r
472 } else {\r
473 a=((a&0x1fffe)<<1)|(a&1);\r
474 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
475 d = Pico_mcd->word_ram[a^1];\r
476 }\r
d0d47c5b 477 } else {\r
478 // allow access in any mode, like Gens does\r
479 d = Pico_mcd->word_ram[(a^1)&0x3ffff];\r
480 }\r
481 dprintf("ret = %02x", (u8)d);\r
482 goto end;\r
483 }\r
484\r
cc68a136 485 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r
486\r
c459aefd 487 if ((a&0xffffc0)==0xa12000)\r
488 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);\r
672ad671 489\r
cc68a136 490 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;\r
491\r
c459aefd 492 if ((a&0xffffc0)==0xa12000)\r
493 rdprintf("ret = %02x", (u8)d);\r
672ad671 494\r
cc68a136 495 end:\r
496\r
497#ifdef __debug_io\r
498 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
499#endif\r
500 return (u8)d;\r
501}\r
502\r
ab0607f7 503\r
cc68a136 504u16 PicoReadM68k16(u32 a)\r
505{\r
506 u16 d=0;\r
507\r
508 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram\r
509\r
510 a&=0xfffffe;\r
511\r
512 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios\r
513\r
514 // prg RAM\r
515 if ((a&0xfe0000)==0x020000) {\r
672ad671 516 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 517 d = *(u16 *)(prg_bank+(a&0x1fffe));\r
518 goto end;\r
519 }\r
520\r
d0d47c5b 521 // word RAM\r
522 if ((a&0xfc0000)==0x200000) {\r
523 dprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);\r
524 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 525 if (a >= 0x220000) {\r
526 dprintf("cell");\r
527 } else {\r
528 a=((a&0x1fffe)<<1);\r
529 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
530 d = *(u16 *)(Pico_mcd->word_ram+a);\r
531 }\r
d0d47c5b 532 } else {\r
533 // allow access in any mode, like Gens does\r
534 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r
535 }\r
536 dprintf("ret = %04x", d);\r
537 goto end;\r
538 }\r
539\r
c459aefd 540 if ((a&0xffffc0)==0xa12000)\r
541 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);\r
672ad671 542\r
cc68a136 543 d = (u16)OtherRead16(a, 16);\r
544\r
c459aefd 545 if ((a&0xffffc0)==0xa12000)\r
546 rdprintf("ret = %04x", d);\r
672ad671 547\r
cc68a136 548 end:\r
549\r
550#ifdef __debug_io\r
551 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
552#endif\r
553 return d;\r
554}\r
555\r
ab0607f7 556\r
cc68a136 557u32 PicoReadM68k32(u32 a)\r
558{\r
559 u32 d=0;\r
560\r
561 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram\r
562\r
563 a&=0xfffffe;\r
564\r
565 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios\r
566\r
567 // prg RAM\r
568 if ((a&0xfe0000)==0x020000) {\r
672ad671 569 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 570 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r
571 d = (pm[0]<<16)|pm[1];\r
572 goto end;\r
573 }\r
574\r
d0d47c5b 575 // word RAM\r
576 if ((a&0xfc0000)==0x200000) {\r
577 dprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);\r
578 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 579 if (a >= 0x220000) {\r
580 dprintf("cell");\r
581 } else {\r
bf098bc5 582 a=((a&0x1fffe)<<1);\r
583 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
ab0607f7 584 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;\r
585 d |= *(u16 *)(Pico_mcd->word_ram+a+4);\r
bf098bc5 586 }\r
d0d47c5b 587 } else {\r
588 // allow access in any mode, like Gens does\r
589 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r
590 }\r
591 dprintf("ret = %08x", d);\r
592 goto end;\r
593 }\r
594\r
c459aefd 595 if ((a&0xffffc0)==0xa12000)\r
596 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);\r
672ad671 597\r
cc68a136 598 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
599\r
c459aefd 600 if ((a&0xffffc0)==0xa12000)\r
601 rdprintf("ret = %08x", d);\r
672ad671 602\r
cc68a136 603 end:\r
604#ifdef __debug_io\r
605 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
606#endif\r
607 return d;\r
608}\r
609\r
ab0607f7 610\r
cc68a136 611// -----------------------------------------------------------------\r
612// Write Ram\r
613\r
614void PicoWriteM68k8(u32 a,u8 d)\r
615{\r
616#ifdef __debug_io\r
617 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
618#endif\r
619 //if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
620 // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
621\r
622\r
ab0607f7 623 if ((a&0xe00000)==0xe00000) { // Ram\r
624 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;\r
625 return;\r
626 }\r
cc68a136 627\r
628 a&=0xffffff;\r
629\r
630 // prg RAM\r
631 if ((a&0xfe0000)==0x020000) {\r
672ad671 632 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
bf098bc5 633 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;\r
cc68a136 634 return;\r
635 }\r
636\r
d0d47c5b 637 // word RAM\r
638 if ((a&0xfc0000)==0x200000) {\r
639 dprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);\r
640 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 641 if (a >= 0x220000) {\r
642 dprintf("cell");\r
643 } else {\r
644 a=((a&0x1fffe)<<1)|(a&1);\r
645 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
646 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;\r
647 }\r
d0d47c5b 648 } else {\r
649 // allow access in any mode, like Gens does\r
bf098bc5 650 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;\r
d0d47c5b 651 }\r
652 return;\r
653 }\r
654\r
c459aefd 655 if ((a&0xffffc0)==0xa12000)\r
656 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);\r
672ad671 657\r
cc68a136 658 OtherWrite8(a,d,8);\r
659}\r
660\r
ab0607f7 661\r
cc68a136 662void PicoWriteM68k16(u32 a,u16 d)\r
663{\r
664#ifdef __debug_io\r
665 dprintf("w16: %06x, %04x", a&0xffffff, d);\r
666#endif\r
cc68a136 667 // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
668\r
ab0607f7 669 if ((a&0xe00000)==0xe00000) { // Ram\r
670 *(u16 *)(Pico.ram+(a&0xfffe))=d;\r
671 return;\r
672 }\r
cc68a136 673\r
674 a&=0xfffffe;\r
675\r
676 // prg RAM\r
677 if ((a&0xfe0000)==0x020000) {\r
672ad671 678 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 679 *(u16 *)(prg_bank+(a&0x1fffe))=d;\r
680 return;\r
681 }\r
682\r
d0d47c5b 683 // word RAM\r
684 if ((a&0xfc0000)==0x200000) {\r
685 dprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);\r
686 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 687 if (a >= 0x220000) {\r
688 dprintf("cell");\r
689 } else {\r
690 a=((a&0x1fffe)<<1);\r
691 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
692 *(u16 *)(Pico_mcd->word_ram+a)=d;\r
693 }\r
d0d47c5b 694 } else {\r
695 // allow access in any mode, like Gens does\r
696 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;\r
697 }\r
698 return;\r
699 }\r
700\r
c459aefd 701 if ((a&0xffffc0)==0xa12000)\r
702 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);\r
cc68a136 703\r
704 OtherWrite16(a,d);\r
705}\r
706\r
ab0607f7 707\r
cc68a136 708void PicoWriteM68k32(u32 a,u32 d)\r
709{\r
710#ifdef __debug_io\r
711 dprintf("w32: %06x, %08x", a&0xffffff, d);\r
712#endif\r
713\r
714 if ((a&0xe00000)==0xe00000)\r
715 {\r
716 // Ram:\r
717 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r
718 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
719 return;\r
720 }\r
721\r
722 a&=0xfffffe;\r
723\r
724 // prg RAM\r
725 if ((a&0xfe0000)==0x020000) {\r
672ad671 726 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 727 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r
728 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
729 return;\r
730 }\r
731\r
672ad671 732 // word RAM\r
d0d47c5b 733 if ((a&0xfc0000)==0x200000) {\r
734 if (d != 0) // don't log clears\r
735 dprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);\r
736 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 737 if (a >= 0x220000) {\r
738 dprintf("cell");\r
739 } else {\r
bf098bc5 740 a=((a&0x1fffe)<<1);\r
741 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
ab0607f7 742 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;\r
743 *(u16 *)(Pico_mcd->word_ram+a+4) = d;\r
bf098bc5 744 }\r
d0d47c5b 745 } else {\r
746 // allow access in any mode, like Gens does\r
747 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r
748 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
749 }\r
672ad671 750 return;\r
d0d47c5b 751 }\r
672ad671 752\r
c459aefd 753 if ((a&0xffffc0)==0xa12000)\r
754 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);\r
cc68a136 755\r
ab0607f7 756#if 0\r
757 if ((a&0x3f) == 0x1c && SekPc == 0xffff05ba)\r
758 {\r
759 int i;\r
760 FILE *ff;\r
761 unsigned short *ram = (unsigned short *) Pico.ram;\r
762 // unswap and dump RAM\r
763 for (i = 0; i < 0x10000/2; i++)\r
764 ram[i] = (ram[i]>>8) | (ram[i]<<8);\r
765 ff = fopen("ram.bin", "wb");\r
766 fwrite(ram, 1, 0x10000, ff);\r
767 fclose(ff);\r
768 exit(0);\r
769 }\r
770#endif\r
771\r
cc68a136 772 OtherWrite16(a, (u16)(d>>16));\r
773 OtherWrite16(a+2,(u16)d);\r
774}\r
775\r
776\r
777// -----------------------------------------------------------------\r
778\r
779\r
780u8 PicoReadS68k8(u32 a)\r
781{\r
782 u32 d=0;\r
783\r
784 a&=0xffffff;\r
785\r
786 // prg RAM\r
787 if (a < 0x80000) {\r
788 d = *(Pico_mcd->prg_ram+(a^1));\r
789 goto end;\r
790 }\r
791\r
792 // regs\r
793 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 794 a &= 0x1ff;\r
795 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);\r
796 if (a >= 0x50 && a < 0x68)\r
797 d = gfx_cd_read(a&~1);\r
798 else d = s68k_reg_read16(a&~1);\r
799 if ((a&1)==0) d>>=8;\r
c459aefd 800 rdprintf("ret = %02x", (u8)d);\r
cc68a136 801 goto end;\r
802 }\r
803\r
d0d47c5b 804 // word RAM (2M area)\r
805 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
806 dprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPc);\r
807 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
808 // TODO (decode)\r
809 dprintf("(decode)");\r
810 } else {\r
811 // allow access in any mode, like Gens does\r
812 d = Pico_mcd->word_ram[(a^1)&0x3ffff];\r
813 }\r
814 dprintf("ret = %02x", (u8)d);\r
815 goto end;\r
816 }\r
817\r
818 // word RAM (1M area)\r
819 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
820 dprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPc);\r
bf098bc5 821 a=((a&0x1fffe)<<1)|(a&1);\r
822 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
823 d = Pico_mcd->word_ram[a^1];\r
824 dprintf("ret = %02x", (u8)d);\r
d0d47c5b 825 goto end;\r
826 }\r
827\r
ab0607f7 828 // bram\r
829 if ((a&0xff0000)==0xfe0000) {\r
830 d = Pico_mcd->bram[(a>>1)&0x1fff];\r
831 goto end;\r
832 }\r
833\r
cc68a136 834 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
835\r
836 end:\r
837\r
838#ifdef __debug_io2\r
839 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
840#endif\r
841 return (u8)d;\r
842}\r
843\r
ab0607f7 844\r
cc68a136 845u16 PicoReadS68k16(u32 a)\r
846{\r
847 u16 d=0;\r
848\r
849 a&=0xfffffe;\r
850\r
851 // prg RAM\r
852 if (a < 0x80000) {\r
853 d = *(u16 *)(Pico_mcd->prg_ram+a);\r
854 goto end;\r
855 }\r
856\r
857 // regs\r
858 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 859 a &= 0x1fe;\r
860 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);\r
861 if (a >= 0x50 && a < 0x68)\r
862 d = gfx_cd_read(a);\r
863 else d = s68k_reg_read16(a);\r
c459aefd 864 rdprintf("ret = %04x", d);\r
cc68a136 865 goto end;\r
866 }\r
867\r
d0d47c5b 868 // word RAM (2M area)\r
869 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
870 dprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPc);\r
871 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
872 // TODO (decode)\r
873 dprintf("(decode)");\r
874 } else {\r
875 // allow access in any mode, like Gens does\r
876 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r
877 }\r
ab0607f7 878 dprintf("ret = %04x", d);\r
d0d47c5b 879 goto end;\r
880 }\r
881\r
882 // word RAM (1M area)\r
883 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
884 dprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPc);\r
bf098bc5 885 a=((a&0x1fffe)<<1);\r
886 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
887 d = *(u16 *)(Pico_mcd->word_ram+a);\r
ab0607f7 888 dprintf("ret = %04x", d);\r
889 goto end;\r
890 }\r
891\r
892 // bram\r
893 if ((a&0xff0000)==0xfe0000) {\r
894 dprintf("s68k_bram r16: [%06x] @%06x", a, SekPc);\r
895 a = (a>>1)&0x1fff;\r
896 d = Pico_mcd->bram[a++]; // Gens does little endian here, an so do we..\r
897 d|= Pico_mcd->bram[a++] << 8;\r
898 dprintf("ret = %04x", d);\r
d0d47c5b 899 goto end;\r
900 }\r
901\r
cc68a136 902 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
903\r
904 end:\r
905\r
906#ifdef __debug_io2\r
907 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
908#endif\r
909 return d;\r
910}\r
911\r
ab0607f7 912\r
cc68a136 913u32 PicoReadS68k32(u32 a)\r
914{\r
915 u32 d=0;\r
916\r
917 a&=0xfffffe;\r
918\r
919 // prg RAM\r
920 if (a < 0x80000) {\r
921 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r
922 d = (pm[0]<<16)|pm[1];\r
923 goto end;\r
924 }\r
925\r
926 // regs\r
927 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 928 a &= 0x1fe;\r
929 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);\r
930 if (a >= 0x50 && a < 0x68)\r
931 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);\r
932 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);\r
c459aefd 933 rdprintf("ret = %08x", d);\r
cc68a136 934 goto end;\r
935 }\r
936\r
d0d47c5b 937 // word RAM (2M area)\r
938 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
939 dprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPc);\r
940 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
941 // TODO (decode)\r
942 dprintf("(decode)");\r
943 } else {\r
944 // allow access in any mode, like Gens does\r
945 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r
946 }\r
ab0607f7 947 dprintf("ret = %08x", d);\r
d0d47c5b 948 goto end;\r
949 }\r
950\r
951 // word RAM (1M area)\r
952 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
ab0607f7 953 dprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPc);\r
bf098bc5 954 a=((a&0x1fffe)<<1);\r
955 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
ab0607f7 956 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;\r
957 d |= *(u16 *)(Pico_mcd->word_ram+a+4);\r
958 dprintf("ret = %08x", d);\r
959 goto end;\r
960 }\r
961\r
962 // bram\r
963 if ((a&0xff0000)==0xfe0000) {\r
964 dprintf("s68k_bram r32: [%06x] @%06x", a, SekPc);\r
965 a = (a>>1)&0x1fff;\r
966 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..\r
967 d|= Pico_mcd->bram[a++] << 24;\r
968 d|= Pico_mcd->bram[a++];\r
969 d|= Pico_mcd->bram[a++] << 8;\r
970 dprintf("ret = %08x", d);\r
d0d47c5b 971 goto end;\r
972 }\r
973\r
cc68a136 974 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
975\r
976 end:\r
977\r
978#ifdef __debug_io2\r
979 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
980#endif\r
981 return d;\r
982}\r
983\r
ab0607f7 984\r
cc68a136 985// -----------------------------------------------------------------\r
986\r
987void PicoWriteS68k8(u32 a,u8 d)\r
988{\r
989#ifdef __debug_io2\r
990 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r
991#endif\r
992\r
993 a&=0xffffff;\r
994\r
995 // prg RAM\r
996 if (a < 0x80000) {\r
997 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));\r
998 *pm=d;\r
999 return;\r
1000 }\r
1001\r
672ad671 1002 if (a != 0xff0011 && (a&0xff8000) == 0xff0000) // PCM hack\r
1003 return;\r
1004\r
cc68a136 1005 // regs\r
1006 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1007 a &= 0x1ff;\r
1008 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);\r
1009 if (a >= 0x50 && a < 0x68)\r
1010 gfx_cd_write(a&~1, (d<<8)|d);\r
1011 else s68k_reg_write8(a,d);\r
cc68a136 1012 return;\r
1013 }\r
1014\r
d0d47c5b 1015 // word RAM (2M area)\r
1016 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1017 dprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPc);\r
1018 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
1019 // TODO (decode)\r
1020 dprintf("(decode)");\r
1021 } else {\r
1022 // allow access in any mode, like Gens does\r
bf098bc5 1023 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;\r
d0d47c5b 1024 }\r
1025 return;\r
1026 }\r
1027\r
1028 // word RAM (1M area)\r
1029 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1030 if (d)\r
1031 dprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPc);\r
bf098bc5 1032 a=((a&0x1fffe)<<1)|(a&1);\r
1033 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
1034 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;\r
d0d47c5b 1035 return;\r
1036 }\r
1037\r
ab0607f7 1038 // bram\r
1039 if ((a&0xff0000)==0xfe0000) {\r
1040 Pico_mcd->bram[(a>>1)&0x1fff] = d;\r
1041 SRam.changed = 1;\r
1042 return;\r
1043 }\r
1044\r
cc68a136 1045 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r
1046}\r
1047\r
ab0607f7 1048\r
cc68a136 1049void PicoWriteS68k16(u32 a,u16 d)\r
1050{\r
1051#ifdef __debug_io2\r
1052 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
1053#endif\r
1054\r
1055 a&=0xfffffe;\r
1056\r
1057 // prg RAM\r
1058 if (a < 0x80000) {\r
1059 *(u16 *)(Pico_mcd->prg_ram+a)=d;\r
1060 return;\r
1061 }\r
1062\r
1063 // regs\r
1064 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1065 a &= 0x1fe;\r
1066 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);\r
1067 if (a >= 0x50 && a < 0x68)\r
1068 gfx_cd_write(a, d);\r
1069 else {\r
1070 s68k_reg_write8(a, d>>8);\r
1071 s68k_reg_write8(a+1,d&0xff);\r
1072 }\r
cc68a136 1073 return;\r
1074 }\r
1075\r
d0d47c5b 1076 // word RAM (2M area)\r
1077 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1078 dprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPc);\r
1079 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
1080 // TODO (decode)\r
1081 dprintf("(decode)");\r
1082 } else {\r
1083 // allow access in any mode, like Gens does\r
1084 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;\r
1085 }\r
1086 return;\r
1087 }\r
1088\r
1089 // word RAM (1M area)\r
1090 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1091 if (d)\r
1092 dprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPc);\r
bf098bc5 1093 a=((a&0x1fffe)<<1);\r
1094 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
1095 *(u16 *)(Pico_mcd->word_ram+a)=d;\r
d0d47c5b 1096 return;\r
1097 }\r
1098\r
ab0607f7 1099 // bram\r
1100 if ((a&0xff0000)==0xfe0000) {\r
1101 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPc);\r
1102 a = (a>>1)&0x1fff;\r
1103 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..\r
1104 Pico_mcd->bram[a++] = d >> 8;\r
1105 SRam.changed = 1;\r
1106 return;\r
1107 }\r
1108\r
cc68a136 1109 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
1110}\r
1111\r
ab0607f7 1112\r
cc68a136 1113void PicoWriteS68k32(u32 a,u32 d)\r
1114{\r
1115#ifdef __debug_io2\r
1116 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
1117#endif\r
1118\r
1119 a&=0xfffffe;\r
1120\r
1121 // prg RAM\r
1122 if (a < 0x80000) {\r
1123 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r
1124 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1125 return;\r
1126 }\r
1127\r
1128 // regs\r
1129 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1130 a &= 0x1fe;\r
1131 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);\r
1132 if (a >= 0x50 && a < 0x68) {\r
1133 gfx_cd_write(a, d>>16);\r
1134 gfx_cd_write(a+2, d&0xffff);\r
1135 } else {\r
1136 s68k_reg_write8(a, d>>24);\r
1137 s68k_reg_write8(a+1,(d>>16)&0xff);\r
1138 s68k_reg_write8(a+2,(d>>8) &0xff);\r
1139 s68k_reg_write8(a+3, d &0xff);\r
1140 }\r
cc68a136 1141 return;\r
1142 }\r
1143\r
d0d47c5b 1144 // word RAM (2M area)\r
1145 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1146 dprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPc);\r
1147 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
1148 // TODO (decode)\r
1149 dprintf("(decode)");\r
1150 } else {\r
1151 // allow access in any mode, like Gens does\r
1152 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r
1153 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1154 }\r
1155 return;\r
1156 }\r
1157\r
1158 // word RAM (1M area)\r
1159 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1160 if (d)\r
1161 dprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPc);\r
bf098bc5 1162 a=((a&0x1fffe)<<1);\r
1163 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
ab0607f7 1164 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;\r
1165 *(u16 *)(Pico_mcd->word_ram+a+4) = d;\r
d0d47c5b 1166 return;\r
1167 }\r
ab0607f7 1168\r
1169 // bram\r
1170 if ((a&0xff0000)==0xfe0000) {\r
1171 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPc);\r
1172 a = (a>>1)&0x1fff;\r
1173 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?\r
1174 Pico_mcd->bram[a++] = d >> 24;\r
1175 Pico_mcd->bram[a++] = d;\r
1176 Pico_mcd->bram[a++] = d >> 8;\r
1177 SRam.changed = 1;\r
1178 return;\r
1179 }\r
1180\r
cc68a136 1181 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
1182}\r
1183\r
1184\r
1185\r
1186// -----------------------------------------------------------------\r
1187\r
1188#ifdef EMU_M68K\r
1189unsigned char PicoReadCD8w (unsigned int a) {\r
1190 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k8(a) : PicoReadM68k8(a);\r
1191}\r
1192unsigned short PicoReadCD16w(unsigned int a) {\r
1193 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k16(a) : PicoReadM68k16(a);\r
1194}\r
1195unsigned int PicoReadCD32w(unsigned int a) {\r
1196 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k32(a) : PicoReadM68k32(a);\r
1197}\r
1198void PicoWriteCD8w (unsigned int a, unsigned char d) {\r
1199 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);\r
1200}\r
1201void PicoWriteCD16w(unsigned int a, unsigned short d) {\r
1202 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);\r
1203}\r
1204void PicoWriteCD32w(unsigned int a, unsigned int d) {\r
1205 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);\r
1206}\r
1207\r
1208// these are allowed to access RAM\r
1209unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {\r
1210 a&=0xffffff;\r
1211 if(m68ki_cpu_p == &PicoS68kCPU) {\r
1212 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram\r
1213 else dprintf("s68k read_pcrel8 @ %06x", a);\r
1214 } else {\r
1215 if(a<Pico.romsize) return *(u8 *)(Pico.rom+(a^1)); // Rom\r
1216 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
1217 }\r
1218 return 0;//(u8) lastread_d;\r
1219}\r
1220unsigned int m68k_read_pcrelative_CD16(unsigned int a) {\r
1221 a&=0xffffff;\r
1222 if(m68ki_cpu_p == &PicoS68kCPU) {\r
1223 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram\r
1224 else dprintf("s68k read_pcrel16 @ %06x", a);\r
1225 } else {\r
1226 if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
1227 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
1228 }\r
1229 return 0;//(u16) lastread_d;\r
1230}\r
1231unsigned int m68k_read_pcrelative_CD32(unsigned int a) {\r
1232 a&=0xffffff;\r
1233 if(m68ki_cpu_p == &PicoS68kCPU) {\r
1234 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram\r
1235 else dprintf("s68k read_pcrel32 @ %06x", a);\r
1236 } else {\r
1237 if(a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
1238 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
1239 }\r
1240 return 0; //lastread_d;\r
1241}\r
1242#endif // EMU_M68K\r
1243\r
fast MegaDrive/MegaCD/32X emulator