line draw deferment implemented
[picodrive.git] / Pico / cd / Sek.c
CommitLineData
03e4f2a3 1// (c) Copyright 2007 notaz, All rights reserved.
cc68a136 2
3
4#include "../PicoInt.h"
5
6
7int SekCycleCntS68k=0; // cycles done in this frame
8int SekCycleAimS68k=0; // cycle aim
9
3aa1e148 10
11/* context */
12// Cyclone 68000
b837b69b 13#ifdef EMU_C68K
3aa1e148 14struct Cyclone PicoCpuCS68k;
b837b69b 15#endif
3aa1e148 16// MUSASHI 68000
cc68a136 17#ifdef EMU_M68K
3aa1e148 18m68ki_cpu_core PicoCpuMS68k;
19#endif
20// FAME 68000
21#ifdef EMU_F68K
22M68K_CONTEXT PicoCpuFS68k;
cc68a136 23#endif
24
3aa1e148 25
51a902ae 26static int new_irq_level(int level)
27{
28 int level_new = 0, irqs;
29 Pico_mcd->m.s68k_pend_ints &= ~(1 << level);
30 irqs = Pico_mcd->m.s68k_pend_ints;
31 irqs &= Pico_mcd->s68k_regs[0x33];
32 while ((irqs >>= 1)) level_new++;
b837b69b 33
51a902ae 34 return level_new;
35}
cc68a136 36
b837b69b 37#ifdef EMU_C68K
0af33fe0 38// interrupt acknowledgement
39static int SekIntAckS68k(int level)
b837b69b 40{
51a902ae 41 int level_new = new_irq_level(level);
b837b69b 42
ca61ee42 43 elprintf(EL_INTS, "s68kACK %i -> %i", level, level_new);
3aa1e148 44 PicoCpuCS68k.irq = level_new;
0af33fe0 45 return CYCLONE_INT_ACK_AUTOVECTOR;
b837b69b 46}
47
eff55556 48static void SekResetAckS68k(void)
b837b69b 49{
ca61ee42 50 elprintf(EL_ANOMALY, "s68k: Reset encountered @ %06x", SekPcS68k);
b837b69b 51}
52
eff55556 53static int SekUnrecognizedOpcodeS68k(void)
b837b69b 54{
55 unsigned int pc, op;
56 pc = SekPcS68k;
3aa1e148 57 op = PicoCpuCS68k.read16(pc);
ca61ee42 58 elprintf(EL_ANOMALY, "Unrecognized Opcode %04x @ %06x", op, pc);
b837b69b 59 //exit(1);
60 return 0;
61}
62#endif
63
3aa1e148 64#ifdef EMU_M68K
65static int SekIntAckMS68k(int level)
66{
b5e5172d 67#ifndef EMU_CORE_DEBUG
3aa1e148 68 int level_new = new_irq_level(level);
ca61ee42 69 elprintf(EL_INTS, "s68kACK %i -> %i", level, level_new);
3aa1e148 70 CPU_INT_LEVEL = level_new << 8;
b5e5172d 71#else
72 CPU_INT_LEVEL = 0;
73#endif
3aa1e148 74 return M68K_INT_ACK_AUTOVECTOR;
75}
76#endif
77
78#ifdef EMU_F68K
79static void SekIntAckFS68k(unsigned level)
80{
81 int level_new = new_irq_level(level);
ca61ee42 82 elprintf(EL_INTS, "s68kACK %i -> %i", level, level_new);
b5e5172d 83#ifndef EMU_CORE_DEBUG
3aa1e148 84 PicoCpuFS68k.interrupts[0] = level_new;
b5e5172d 85#else
86 {
87 extern int dbg_irq_level_sub;
88 dbg_irq_level_sub = level_new;
89 PicoCpuFS68k.interrupts[0] = 0;
90 }
91#endif
3aa1e148 92}
93#endif
b837b69b 94
cc68a136 95
eff55556 96PICO_INTERNAL int SekInitS68k()
cc68a136 97{
b837b69b 98#ifdef EMU_C68K
99// CycloneInit();
3aa1e148 100 memset(&PicoCpuCS68k,0,sizeof(PicoCpuCS68k));
101 PicoCpuCS68k.IrqCallback=SekIntAckS68k;
102 PicoCpuCS68k.ResetCallback=SekResetAckS68k;
103 PicoCpuCS68k.UnrecognizedCallback=SekUnrecognizedOpcodeS68k;
b837b69b 104#endif
cc68a136 105#ifdef EMU_M68K
106 {
107 // Musashi is not very context friendly..
108 void *oldcontext = m68ki_cpu_p;
3aa1e148 109 m68k_set_context(&PicoCpuMS68k);
cc68a136 110 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
111 m68k_init();
3aa1e148 112 m68k_set_int_ack_callback(SekIntAckMS68k);
cc68a136 113// m68k_pulse_reset(); // not yet, memmap is not set up
114 m68k_set_context(oldcontext);
115 }
116#endif
3aa1e148 117#ifdef EMU_F68K
118 {
119 void *oldcontext = g_m68kcontext;
120 g_m68kcontext = &PicoCpuFS68k;
121 memset(&PicoCpuFS68k, 0, sizeof(PicoCpuFS68k));
03e4f2a3 122 fm68k_init();
3aa1e148 123 PicoCpuFS68k.iack_handler = SekIntAckFS68k;
b5e5172d 124 PicoCpuFS68k.sr = 0x2704; // Z flag
3aa1e148 125 g_m68kcontext = oldcontext;
126 }
127#endif
cc68a136 128
129 return 0;
130}
131
132// Reset the 68000:
eff55556 133PICO_INTERNAL int SekResetS68k()
cc68a136 134{
135 if (Pico.rom==NULL) return 1;
136
b837b69b 137#ifdef EMU_C68K
3aa1e148 138 PicoCpuCS68k.state_flags=0;
139 PicoCpuCS68k.osp=0;
140 PicoCpuCS68k.srh =0x27; // Supervisor mode
141 PicoCpuCS68k.flags=4; // Z set
142 PicoCpuCS68k.irq=0;
143 PicoCpuCS68k.a[7]=PicoCpuCS68k.read32(0); // Stack Pointer
144 PicoCpuCS68k.membase=0;
145 PicoCpuCS68k.pc=PicoCpuCS68k.checkpc(PicoCpuCS68k.read32(4)); // Program Counter
b837b69b 146#endif
cc68a136 147#ifdef EMU_M68K
148 {
149 void *oldcontext = m68ki_cpu_p;
150
3aa1e148 151 m68k_set_context(&PicoCpuMS68k);
2d0b15bb 152 m68ki_cpu.sp[0]=0;
153 m68k_set_irq(0);
cc68a136 154 m68k_pulse_reset();
155 m68k_set_context(oldcontext);
156 }
157#endif
3aa1e148 158#ifdef EMU_F68K
159 {
160 void *oldcontext = g_m68kcontext;
161 g_m68kcontext = &PicoCpuFS68k;
03e4f2a3 162 fm68k_reset();
3aa1e148 163 g_m68kcontext = oldcontext;
164 }
165#endif
cc68a136 166
167 return 0;
168}
169
eff55556 170PICO_INTERNAL int SekInterruptS68k(int irq)
cc68a136 171{
51a902ae 172 int irqs, real_irq = 1;
173 Pico_mcd->m.s68k_pend_ints |= 1 << irq;
174 irqs = Pico_mcd->m.s68k_pend_ints >> 1;
3aa1e148 175 while ((irqs >>= 1)) real_irq++;
51a902ae 176
b5e5172d 177#ifdef EMU_CORE_DEBUG
178 {
179 extern int dbg_irq_level_sub;
180 dbg_irq_level_sub=real_irq;
b5e5172d 181 return 0;
182 }
183#endif
b837b69b 184#ifdef EMU_C68K
3aa1e148 185 PicoCpuCS68k.irq=real_irq;
b837b69b 186#endif
cc68a136 187#ifdef EMU_M68K
188 void *oldcontext = m68ki_cpu_p;
3aa1e148 189 m68k_set_context(&PicoCpuMS68k);
190 m68k_set_irq(real_irq);
cc68a136 191 m68k_set_context(oldcontext);
3aa1e148 192#endif
193#ifdef EMU_F68K
194 PicoCpuFS68k.interrupts[0]=real_irq;
cc68a136 195#endif
196 return 0;
197}
198