[picodrive.git] / cpu / drc / emit_x86.c

/*
 * Basic macros to emit x86 instructions and some utils
 * Copyright (C) 2008,2009,2010 notaz
 *
 * This work is licensed under the terms of MAME license.
 * See COPYING file in the top-level directory.
 *
 * note:
 *  temp registers must be eax-edx due to use of SETcc and r/w 8/16.
 * note about silly things like emith_eor_r_r_r:
 *  these are here because the compiler was designed
 *  for ARM as it's primary target.
 */
#include <stdarg.h>

enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };

#define CONTEXT_REG xBP

#define ICOND_JO  0x00
#define ICOND_JNO 0x01
#define ICOND_JB  0x02
#define ICOND_JAE 0x03
#define ICOND_JE  0x04
#define ICOND_JNE 0x05
#define ICOND_JBE 0x06
#define ICOND_JA  0x07
#define ICOND_JS  0x08
#define ICOND_JNS 0x09
#define ICOND_JL  0x0c
#define ICOND_JGE 0x0d
#define ICOND_JLE 0x0e
#define ICOND_JG  0x0f

#define IOP_JMP   0xeb

// unified conditions (we just use rel8 jump instructions for x86)
#define DCOND_EQ ICOND_JE
#define DCOND_NE ICOND_JNE
#define DCOND_MI ICOND_JS      // MInus
#define DCOND_PL ICOND_JNS     // PLus or zero
#define DCOND_HI ICOND_JA      // higher (unsigned)
#define DCOND_HS ICOND_JAE     // higher || same (unsigned)
#define DCOND_LO ICOND_JB      // lower (unsigned)
#define DCOND_LS ICOND_JBE     // lower || same (unsigned)
#define DCOND_GE ICOND_JGE     // greater || equal (signed)
#define DCOND_GT ICOND_JG      // greater (signed)
#define DCOND_LE ICOND_JLE     // less || equal (signed)
#define DCOND_LT ICOND_JL      // less (signed)
#define DCOND_VS ICOND_JO      // oVerflow Set
#define DCOND_VC ICOND_JNO     // oVerflow Clear

#define EMIT_PTR(ptr, val, type) \
	*(type *)(ptr) = val

#define EMIT(val, type) { \
	EMIT_PTR(tcache_ptr, val, type); \
	tcache_ptr += sizeof(type); \
}

#define EMIT_OP(op) { \
	COUNT_OP; \
	EMIT(op, u8); \
}

#define EMIT_MODRM(mod,r,rm) \
	EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)

#define EMIT_SIB(scale,index,base) \
	EMIT(((scale)<<6) | ((index)<<3) | (base), u8)

#define EMIT_OP_MODRM(op,mod,r,rm) do { \
	EMIT_OP(op); \
	EMIT_MODRM(mod, r, rm); \
} while (0)

#define JMP8_POS(ptr) \
	ptr = tcache_ptr; \
	tcache_ptr += 2

#define JMP8_EMIT(op, ptr) \
	EMIT_PTR(ptr, 0x70|(op), u8); \
	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)

#define JMP8_EMIT_NC(ptr) \
	EMIT_PTR(ptr, IOP_JMP, u8); \
	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)

// _r_r
#define emith_move_r_r(dst, src) \
	EMIT_OP_MODRM(0x8b, 3, dst, src)

#define emith_add_r_r(d, s) \
	EMIT_OP_MODRM(0x01, 3, s, d)

#define emith_sub_r_r(d, s) \
	EMIT_OP_MODRM(0x29, 3, s, d)

#define emith_adc_r_r(d, s) \
	EMIT_OP_MODRM(0x11, 3, s, d)

#define emith_sbc_r_r(d, s) \
	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */

#define emith_or_r_r(d, s) \
	EMIT_OP_MODRM(0x09, 3, s, d)

#define emith_and_r_r(d, s) \
	EMIT_OP_MODRM(0x21, 3, s, d)

#define emith_eor_r_r(d, s) \
	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */

#define emith_tst_r_r(d, s) \
	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */

#define emith_cmp_r_r(d, s) \
	EMIT_OP_MODRM(0x39, 3, s, d)

// fake teq - test equivalence - get_flags(d ^ s)
#define emith_teq_r_r(d, s) { \
	emith_push(d); \
	emith_eor_r_r(d, s); \
	emith_pop(d); \
}

#define emith_mvn_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
}

#define emith_negc_r_r(d, s) { \
	int tmp_ = rcache_get_tmp(); \
	emith_move_r_imm(tmp_, 0); \
	emith_sbc_r_r(tmp_, s); \
	emith_move_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_neg_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
}

// _r_r_r
#define emith_add_r_r_r(d, s1, s2) { \
	if (d == s1) { \
		emith_add_r_r(d, s2); \
	} else if (d == s2) { \
		emith_add_r_r(d, s1); \
	} else { \
		emith_move_r_r(d, s1); \
		emith_add_r_r(d, s2); \
	} \
}

#define emith_eor_r_r_r(d, s1, s2) { \
	if (d == s1) { \
		emith_eor_r_r(d, s2); \
	} else if (d == s2) { \
		emith_eor_r_r(d, s1); \
	} else { \
		emith_move_r_r(d, s1); \
		emith_eor_r_r(d, s2); \
	} \
}

// _r_r_shift
#define emith_or_r_r_lsl(d, s, lslimm) { \
	int tmp_ = rcache_get_tmp(); \
	emith_lsl(tmp_, s, lslimm); \
	emith_or_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

// d != s
#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	emith_push(s); \
	emith_lsr(s, s, lsrimm); \
	emith_eor_r_r(d, s); \
	emith_pop(s); \
}

// _r_imm
#define emith_move_r_imm(r, imm) { \
	EMIT_OP(0xb8 + (r)); \
	EMIT(imm, u32); \
}

#define emith_move_r_imm_s8(r, imm) \
	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))

#define emith_arith_r_imm(op, r, imm) do { \
	EMIT_OP_MODRM(0x81, 3, op, r); \
	EMIT(imm, u32); \
} while (0)

#define emith_add_r_imm(r, imm) \
	emith_arith_r_imm(0, r, imm)

#define emith_or_r_imm(r, imm) \
	emith_arith_r_imm(1, r, imm)

#define emith_adc_r_imm(r, imm) \
	emith_arith_r_imm(2, r, imm)

#define emith_sbc_r_imm(r, imm) \
	emith_arith_r_imm(3, r, imm) // sbb

#define emith_and_r_imm(r, imm) \
	emith_arith_r_imm(4, r, imm)

#define emith_sub_r_imm(r, imm) \
	emith_arith_r_imm(5, r, imm)

#define emith_eor_r_imm(r, imm) \
	emith_arith_r_imm(6, r, imm)

#define emith_cmp_r_imm(r, imm) \
	emith_arith_r_imm(7, r, imm)

#define emith_tst_r_imm(r, imm) do { \
	EMIT_OP_MODRM(0xf7, 3, 0, r); \
	EMIT(imm, u32); \
} while (0)

// fake
#define emith_bic_r_imm(r, imm) \
	emith_arith_r_imm(4, r, ~(imm))

// fake conditionals (using SJMP instead)
#define emith_move_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_move_r_imm(r, imm); \
}

#define emith_add_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_add_r_imm(r, imm); \
}

#define emith_sub_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_sub_r_imm(r, imm); \
}

#define emith_or_r_imm_c(cond, r, imm) \
	emith_or_r_imm(r, imm)
#define emith_eor_r_imm_c(cond, r, imm) \
	emith_eor_r_imm(r, imm)
#define emith_bic_r_imm_c(cond, r, imm) \
	emith_bic_r_imm(r, imm)
#define emith_ror_c(cond, d, s, cnt) \
	emith_ror(d, s, cnt)

#define emith_read_r_r_offs_c(cond, r, rs, offs) \
	emith_read_r_r_offs(r, rs, offs)
#define emith_write_r_r_offs_c(cond, r, rs, offs) \
	emith_write_r_r_offs(r, rs, offs)
#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
	emith_read8_r_r_offs(r, rs, offs)
#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
	emith_write8_r_r_offs(r, rs, offs)
#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
	emith_read16_r_r_offs(r, rs, offs)
#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
	emith_write16_r_r_offs(r, rs, offs)
#define emith_jump_reg_c(cond, r) \
	emith_jump_reg(r)
#define emith_jump_ctx_c(cond, offs) \
	emith_jump_ctx(offs)
#define emith_ret_c(cond) \
	emith_ret()

// _r_r_imm
#define emith_add_r_r_imm(d, s, imm) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_add_r_imm(d, imm); \
}

#define emith_and_r_r_imm(d, s, imm) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, imm); \
}

// shift
#define emith_shift(op, d, s, cnt) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xc1, 3, op, d); \
	EMIT(cnt, u8); \
}

#define emith_lsl(d, s, cnt) \
	emith_shift(4, d, s, cnt)

#define emith_lsr(d, s, cnt) \
	emith_shift(5, d, s, cnt)

#define emith_asr(d, s, cnt) \
	emith_shift(7, d, s, cnt)

#define emith_rol(d, s, cnt) \
	emith_shift(0, d, s, cnt)

#define emith_ror(d, s, cnt) \
	emith_shift(1, d, s, cnt)

#define emith_rolc(r) \
	EMIT_OP_MODRM(0xd1, 3, 2, r)

#define emith_rorc(r) \
	EMIT_OP_MODRM(0xd1, 3, 3, r)

// misc
#define emith_push(r) \
	EMIT_OP(0x50 + (r))

#define emith_push_imm(imm) { \
	EMIT_OP(0x68); \
	EMIT(imm, u32); \
}

#define emith_pop(r) \
	EMIT_OP(0x58 + (r))

#define emith_neg_r(r) \
	EMIT_OP_MODRM(0xf7, 3, 3, r)

#define emith_clear_msb(d, s, count) { \
	u32 t = (u32)-1; \
	t >>= count; \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, t); \
}

#define emith_clear_msb_c(cond, d, s, count) { \
	(void)(cond); \
	emith_clear_msb(d, s, count); \
}

#define emith_sext(d, s, bits) { \
	emith_lsl(d, s, 32 - (bits)); \
	emith_asr(d, d, 32 - (bits)); \
}

#define emith_setc(r) { \
	EMIT_OP(0x0f); \
	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
}

// XXX: stupid mess
#define emith_mul_(op, dlo, dhi, s1, s2) { \
	int rmr; \
	if (dlo != xAX && dhi != xAX) \
		emith_push(xAX); \
	if (dlo != xDX && dhi != xDX) \
		emith_push(xDX); \
	if ((s1) == xAX) \
		rmr = s2; \
	else if ((s2) == xAX) \
		rmr = s1; \
	else { \
		emith_move_r_r(xAX, s1); \
		rmr = s2; \
	} \
	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	if (dhi != xDX && dhi != -1) \
		emith_push(xDX); \
	if (dlo != xAX) \
		emith_move_r_r(dlo, xAX); \
	if (dhi != xDX && dhi != -1) \
		emith_pop(dhi); \
	if (dlo != xDX && dhi != xDX) \
		emith_pop(xDX); \
	if (dlo != xAX && dhi != xAX) \
		emith_pop(xAX); \
}

#define emith_mul_u64(dlo, dhi, s1, s2) \
	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */

#define emith_mul_s64(dlo, dhi, s1, s2) \
	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */

#define emith_mul(d, s1, s2) \
	emith_mul_(4, d, -1, s1, s2)

// (dlo,dhi) += signed(s1) * signed(s2)
#define emith_mula_s64(dlo, dhi, s1, s2) { \
	emith_push(dhi); \
	emith_push(dlo); \
	emith_mul_(5, dlo, dhi, s1, s2); \
	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	EMIT_SIB(0, 4, 4); \
	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	emith_add_r_imm(xSP, 4*2); \
}

// "flag" instructions are the same
#define emith_subf_r_imm emith_sub_r_imm
#define emith_addf_r_r   emith_add_r_r
#define emith_subf_r_r   emith_sub_r_r
#define emith_adcf_r_r   emith_adc_r_r
#define emith_sbcf_r_r   emith_sbc_r_r
#define emith_eorf_r_r   emith_eor_r_r
#define emith_negcf_r_r  emith_negc_r_r

#define emith_lslf  emith_lsl
#define emith_lsrf  emith_lsr
#define emith_asrf  emith_asr
#define emith_rolf  emith_rol
#define emith_rorf  emith_ror
#define emith_rolcf emith_rolc
#define emith_rorcf emith_rorc

#define emith_deref_op(op, r, rs, offs) do { \
	/* mov r <-> [ebp+#offs] */ \
	if ((offs) >= 0x80) { \
		EMIT_OP_MODRM(op, 2, r, rs); \
		EMIT(offs, u32); \
	} else { \
		EMIT_OP_MODRM(op, 1, r, rs); \
		EMIT(offs, u8); \
	} \
} while (0)

#define is_abcdx(r) (xAX <= (r) && (r) <= xDX)

#define emith_read_r_r_offs(r, rs, offs) \
	emith_deref_op(0x8b, r, rs, offs)

#define emith_write_r_r_offs(r, rs, offs) \
	emith_deref_op(0x89, r, rs, offs)

// note: don't use prefixes on this
#define emith_read8_r_r_offs(r, rs, offs) do { \
	int r_ = r; \
	if (!is_abcdx(r)) \
		r_ = rcache_get_tmp(); \
	emith_deref_op(0x8a, r_, rs, offs); \
	if ((r) != r_) { \
		emith_move_r_r(r, r_); \
		rcache_free_tmp(r_); \
	} \
} while (0)

#define emith_write8_r_r_offs(r, rs, offs) do {\
	int r_ = r; \
	if (!is_abcdx(r)) { \
		r_ = rcache_get_tmp(); \
		emith_move_r_r(r_, r); \
	} \
	emith_deref_op(0x88, r_, rs, offs); \
	if ((r) != r_) \
		rcache_free_tmp(r_); \
} while (0)

#define emith_read16_r_r_offs(r, rs, offs) { \
	EMIT(0x66, u8); /* operand override */ \
	emith_read_r_r_offs(r, rs, offs); \
}

#define emith_write16_r_r_offs(r, rs, offs) { \
	EMIT(0x66, u8); \
	emith_write_r_r_offs(r, rs, offs); \
}

#define emith_ctx_read(r, offs) \
	emith_read_r_r_offs(r, CONTEXT_REG, offs)

#define emith_ctx_write(r, offs) \
	emith_write_r_r_offs(r, CONTEXT_REG, offs)

#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
	int r_ = r, offs_ = offs, cnt_ = cnt;     \
	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
		emith_ctx_read(r_, offs_);        \
} while (0)

#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
	int r_ = r, offs_ = offs, cnt_ = cnt;     \
	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
		emith_ctx_write(r_, offs_);       \
} while (0)

// assumes EBX is free
#define emith_ret_to_ctx(offs) { \
	emith_pop(xBX); \
	emith_ctx_write(xBX, offs); \
}

#define emith_jump(ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe9); \
	EMIT(disp, u32); \
}

#define emith_jump_patchable(target) \
	emith_jump(target)

#define emith_jump_cond(cond, ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
	EMIT(0x0f, u8); \
	EMIT_OP(0x80 | (cond)); \
	EMIT(disp, u32); \
}

#define emith_jump_cond_patchable(cond, target) \
	emith_jump_cond(cond, target)

#define emith_jump_patch(ptr, target) do { \
	u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
	u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
	EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
} while (0)

#define emith_jump_at(ptr, target) { \
	u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
	EMIT_PTR(ptr, 0xe9, u8); \
	EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
}

#define emith_call(ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe8); \
	EMIT(disp, u32); \
}

#define emith_call_cond(cond, ptr) \
	emith_call(ptr)

#define emith_call_reg(r) \
	EMIT_OP_MODRM(0xff, 3, 2, r)

#define emith_call_ctx(offs) { \
	EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
	EMIT(offs, u32); \
}

#define emith_ret() \
	EMIT_OP(0xc3)

#define emith_jump_reg(r) \
	EMIT_OP_MODRM(0xff, 3, 4, r)

#define emith_jump_ctx(offs) { \
	EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
	EMIT(offs, u32); \
}

#define emith_push_ret()

#define emith_pop_and_ret() \
	emith_ret()

#define EMITH_JMP_START(cond) { \
	u8 *cond_ptr; \
	JMP8_POS(cond_ptr)

#define EMITH_JMP_END(cond) \
	JMP8_EMIT(cond, cond_ptr); \
}

#define EMITH_JMP3_START(cond) { \
	u8 *cond_ptr, *else_ptr; \
	JMP8_POS(cond_ptr)

#define EMITH_JMP3_MID(cond) \
	JMP8_POS(else_ptr); \
	JMP8_EMIT(cond, cond_ptr);

#define EMITH_JMP3_END() \
	JMP8_EMIT_NC(else_ptr); \
}

// "simple" jump (no more then a few insns)
// ARM will use conditional instructions here
#define EMITH_SJMP_START EMITH_JMP_START
#define EMITH_SJMP_END EMITH_JMP_END

#define EMITH_SJMP3_START EMITH_JMP3_START
#define EMITH_SJMP3_MID EMITH_JMP3_MID
#define EMITH_SJMP3_END EMITH_JMP3_END

#define emith_pass_arg_r(arg, reg) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_r(rd, reg); \
}

#define emith_pass_arg_imm(arg, imm) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_imm(rd, imm); \
}

#define host_instructions_updated(base, end)

#define host_arg2reg(rd, arg) \
	switch (arg) { \
	case 0: rd = xAX; break; \
	case 1: rd = xDX; break; \
	case 2: rd = xCX; break; \
	}

/* SH2 drc specific */
#define emith_sh2_drc_entry() { \
	emith_push(xBX);        \
	emith_push(xBP);        \
	emith_push(xSI);        \
	emith_push(xDI);        \
}

#define emith_sh2_drc_exit() {  \
	emith_pop(xDI);         \
	emith_pop(xSI);         \
	emith_pop(xBP);         \
	emith_pop(xBX);         \
	emith_ret();            \
}

// assumes EBX is free temporary
#define emith_sh2_wcall(a, tab) { \
	int arg2_; \
	host_arg2reg(arg2_, 2); \
	emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
	EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
	EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
	emith_move_r_r(arg2_, CONTEXT_REG); \
	emith_jump_reg(xBX); \
}

#define emith_sh2_dtbf_loop() { \
	u8 *jmp0; /* negative cycles check */            \
	u8 *jmp1; /* unsinged overflow check */          \
	int cr, rn;                                      \
	int tmp_ = rcache_get_tmp();                     \
	cr = rcache_get_reg(SHR_SR, RC_GR_RMW);          \
	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	emith_sub_r_imm(rn, 1);                          \
	emith_sub_r_imm(cr, (cycles+1) << 12);           \
	cycles = 0;                                      \
	emith_asr(tmp_, cr, 2+12);                       \
	JMP8_POS(jmp0); /* no negative cycles */         \
	emith_move_r_imm(tmp_, 0);                       \
	JMP8_EMIT(ICOND_JNS, jmp0);                      \
	emith_and_r_imm(cr, 0xffe);                      \
	emith_subf_r_r(rn, tmp_);                        \
	JMP8_POS(jmp1); /* no overflow */                \
	emith_neg_r(rn); /* count left */                \
	emith_lsl(rn, rn, 2+12);                         \
	emith_or_r_r(cr, rn);                            \
	emith_or_r_imm(cr, 1);                           \
	emith_move_r_imm(rn, 0);                         \
	JMP8_EMIT(ICOND_JA, jmp1);                       \
	rcache_free_tmp(tmp_);                           \
}

#define emith_write_sr(sr, srcr) { \
	int tmp_ = rcache_get_tmp(); \
	emith_clear_msb(tmp_, srcr, 22); \
	emith_bic_r_imm(sr, 0x3ff); \
	emith_or_r_r(sr, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_tpop_carry(sr, is_sub) \
	emith_lsr(sr, sr, 1)

#define emith_tpush_carry(sr, is_sub) \
	emith_adc_r_r(sr, sr)

/*
 * if Q
 *   t = carry(Rn += Rm)
 * else
 *   t = carry(Rn -= Rm)
 * T ^= t
 */
#define emith_sh2_div1_step(rn, rm, sr) {         \
	u8 *jmp0, *jmp1;                          \
	int tmp_ = rcache_get_tmp();              \
	emith_eor_r_r(tmp_, tmp_);                \
	emith_tst_r_imm(sr, Q);  /* if (Q ^ M) */ \
	JMP8_POS(jmp0);          /* je do_sub */  \
	emith_add_r_r(rn, rm);                    \
	JMP8_POS(jmp1);          /* jmp done */   \
	JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */  \
	emith_sub_r_r(rn, rm);                    \
	JMP8_EMIT_NC(jmp1);      /* done: */      \
	emith_setc(tmp_);                         \
	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
	rcache_free_tmp(tmp_);                    \
}
Commit	Line	Data
3863edbd	1	/*
cff531af	2	* Basic macros to emit x86 instructions and some utils
	3	* Copyright (C) 2008,2009,2010 notaz
	4	*
	5	* This work is licensed under the terms of MAME license.
	6	* See COPYING file in the top-level directory.
	7	*
8b4f38f4	8	* note:
a2b8c5a5	9	* temp registers must be eax-edx due to use of SETcc and r/w 8/16.
f0d7b1fa	10	* note about silly things like emith_eor_r_r_r:
8b4f38f4	11	* these are here because the compiler was designed
8b4f38f4	12	* for ARM as it's primary target.
3863edbd	13	*/
679af8a3	14	#include <stdarg.h>
679af8a3	15
f4bb5d6b	16	enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
f4bb5d6b	17
f4bb5d6b	18	#define CONTEXT_REG xBP
679af8a3	19
18b94127	20	#define ICOND_JO 0x00
	21	#define ICOND_JNO 0x01
	22	#define ICOND_JB 0x02
	23	#define ICOND_JAE 0x03
	24	#define ICOND_JE 0x04
	25	#define ICOND_JNE 0x05
	26	#define ICOND_JBE 0x06
	27	#define ICOND_JA 0x07
	28	#define ICOND_JS 0x08
	29	#define ICOND_JNS 0x09
	30	#define ICOND_JL 0x0c
	31	#define ICOND_JGE 0x0d
	32	#define ICOND_JLE 0x0e
	33	#define ICOND_JG 0x0f
	34
	35	#define IOP_JMP 0xeb
80599a42	36
80599a42	37	// unified conditions (we just use rel8 jump instructions for x86)
18b94127	38	#define DCOND_EQ ICOND_JE
	39	#define DCOND_NE ICOND_JNE
	40	#define DCOND_MI ICOND_JS // MInus
	41	#define DCOND_PL ICOND_JNS // PLus or zero
	42	#define DCOND_HI ICOND_JA // higher (unsigned)
	43	#define DCOND_HS ICOND_JAE // higher \|\| same (unsigned)
	44	#define DCOND_LO ICOND_JB // lower (unsigned)
	45	#define DCOND_LS ICOND_JBE // lower \|\| same (unsigned)
	46	#define DCOND_GE ICOND_JGE // greater \|\| equal (signed)
	47	#define DCOND_GT ICOND_JG // greater (signed)
	48	#define DCOND_LE ICOND_JLE // less \|\| equal (signed)
	49	#define DCOND_LT ICOND_JL // less (signed)
	50	#define DCOND_VS ICOND_JO // oVerflow Set
	51	#define DCOND_VC ICOND_JNO // oVerflow Clear
80599a42	52
679af8a3	53	#define EMIT_PTR(ptr, val, type) \
	54	(type )(ptr) = val
	55
	56	#define EMIT(val, type) { \
	57	EMIT_PTR(tcache_ptr, val, type); \
f4bb5d6b	58	tcache_ptr += sizeof(type); \
679af8a3	59	}
679af8a3	60
e898de13	61	#define EMIT_OP(op) { \
	62	COUNT_OP; \
	63	EMIT(op, u8); \
	64	}
	65
679af8a3	66	#define EMIT_MODRM(mod,r,rm) \
	67	EMIT(((mod)<<6) \| ((r)<<3) \| (rm), u8)
	68
f0d7b1fa	69	#define EMIT_SIB(scale,index,base) \
	70	EMIT(((scale)<<6) \| ((index)<<3) \| (base), u8)
	71
04092e32	72	#define EMIT_OP_MODRM(op,mod,r,rm) do { \
e898de13	73	EMIT_OP(op); \
679af8a3	74	EMIT_MODRM(mod, r, rm); \
04092e32	75	} while (0)
679af8a3	76
80599a42	77	#define JMP8_POS(ptr) \
	78	ptr = tcache_ptr; \
	79	tcache_ptr += 2
	80
	81	#define JMP8_EMIT(op, ptr) \
18b94127	82	EMIT_PTR(ptr, 0x70\|(op), u8); \
	83	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
	84
	85	#define JMP8_EMIT_NC(ptr) \
	86	EMIT_PTR(ptr, IOP_JMP, u8); \
80599a42	87	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
80599a42	88
3863edbd	89	// _r_r
679af8a3	90	#define emith_move_r_r(dst, src) \
	91	EMIT_OP_MODRM(0x8b, 3, dst, src)
	92
80599a42	93	#define emith_add_r_r(d, s) \
	94	EMIT_OP_MODRM(0x01, 3, s, d)
	95
	96	#define emith_sub_r_r(d, s) \
	97	EMIT_OP_MODRM(0x29, 3, s, d)
	98
3863edbd	99	#define emith_adc_r_r(d, s) \
	100	EMIT_OP_MODRM(0x11, 3, s, d)
	101
	102	#define emith_sbc_r_r(d, s) \
	103	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
	104
80599a42	105	#define emith_or_r_r(d, s) \
	106	EMIT_OP_MODRM(0x09, 3, s, d)
	107
3863edbd	108	#define emith_and_r_r(d, s) \
	109	EMIT_OP_MODRM(0x21, 3, s, d)
	110
80599a42	111	#define emith_eor_r_r(d, s) \
3863edbd	112	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
	113
	114	#define emith_tst_r_r(d, s) \
	115	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
	116
	117	#define emith_cmp_r_r(d, s) \
	118	EMIT_OP_MODRM(0x39, 3, s, d)
80599a42	119
	120	// fake teq - test equivalence - get_flags(d ^ s)
	121	#define emith_teq_r_r(d, s) { \
	122	emith_push(d); \
	123	emith_eor_r_r(d, s); \
	124	emith_pop(d); \
	125	}
	126
52d759c3	127	#define emith_mvn_r_r(d, s) { \
	128	if (d != s) \
	129	emith_move_r_r(d, s); \
	130	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
	131	}
	132
	133	#define emith_negc_r_r(d, s) { \
	134	int tmp_ = rcache_get_tmp(); \
	135	emith_move_r_imm(tmp_, 0); \
	136	emith_sbc_r_r(tmp_, s); \
	137	emith_move_r_r(d, tmp_); \
	138	rcache_free_tmp(tmp_); \
	139	}
	140
	141	#define emith_neg_r_r(d, s) { \
	142	if (d != s) \
	143	emith_move_r_r(d, s); \
	144	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
	145	}
	146
3863edbd	147	// _r_r_r
bf092a36	148	#define emith_add_r_r_r(d, s1, s2) { \
	149	if (d == s1) { \
	150	emith_add_r_r(d, s2); \
	151	} else if (d == s2) { \
	152	emith_add_r_r(d, s1); \
	153	} else { \
	154	emith_move_r_r(d, s1); \
	155	emith_add_r_r(d, s2); \
	156	} \
	157	}
	158
3863edbd	159	#define emith_eor_r_r_r(d, s1, s2) { \
52d759c3	160	if (d == s1) { \
	161	emith_eor_r_r(d, s2); \
	162	} else if (d == s2) { \
	163	emith_eor_r_r(d, s1); \
	164	} else { \
3863edbd	165	emith_move_r_r(d, s1); \
52d759c3	166	emith_eor_r_r(d, s2); \
52d759c3	167	} \
3863edbd	168	}
3863edbd	169
f0d7b1fa	170	// _r_r_shift
f0d7b1fa	171	#define emith_or_r_r_lsl(d, s, lslimm) { \
52d759c3	172	int tmp_ = rcache_get_tmp(); \
f0d7b1fa	173	emith_lsl(tmp_, s, lslimm); \
f0d7b1fa	174	emith_or_r_r(d, tmp_); \
52d759c3	175	rcache_free_tmp(tmp_); \
3863edbd	176	}
3863edbd	177
f0d7b1fa	178	// d != s
	179	#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	180	emith_push(s); \
	181	emith_lsr(s, s, lsrimm); \
	182	emith_eor_r_r(d, s); \
	183	emith_pop(s); \
	184	}
	185
80599a42	186	// _r_imm
679af8a3	187	#define emith_move_r_imm(r, imm) { \
e898de13	188	EMIT_OP(0xb8 + (r)); \
679af8a3	189	EMIT(imm, u32); \
	190	}
	191
52d759c3	192	#define emith_move_r_imm_s8(r, imm) \
	193	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
	194
18b94127	195	#define emith_arith_r_imm(op, r, imm) do { \
80599a42	196	EMIT_OP_MODRM(0x81, 3, op, r); \
679af8a3	197	EMIT(imm, u32); \
18b94127	198	} while (0)
679af8a3	199
80599a42	200	#define emith_add_r_imm(r, imm) \
	201	emith_arith_r_imm(0, r, imm)
	202
	203	#define emith_or_r_imm(r, imm) \
	204	emith_arith_r_imm(1, r, imm)
	205
5686d931	206	#define emith_adc_r_imm(r, imm) \
	207	emith_arith_r_imm(2, r, imm)
	208
	209	#define emith_sbc_r_imm(r, imm) \
	210	emith_arith_r_imm(3, r, imm) // sbb
	211
80599a42	212	#define emith_and_r_imm(r, imm) \
	213	emith_arith_r_imm(4, r, imm)
	214
	215	#define emith_sub_r_imm(r, imm) \
	216	emith_arith_r_imm(5, r, imm)
	217
52d759c3	218	#define emith_eor_r_imm(r, imm) \
	219	emith_arith_r_imm(6, r, imm)
	220
ed8cf79b	221	#define emith_cmp_r_imm(r, imm) \
	222	emith_arith_r_imm(7, r, imm)
	223
18b94127	224	#define emith_tst_r_imm(r, imm) do { \
80599a42	225	EMIT_OP_MODRM(0xf7, 3, 0, r); \
679af8a3	226	EMIT(imm, u32); \
18b94127	227	} while (0)
679af8a3	228
80599a42	229	// fake
	230	#define emith_bic_r_imm(r, imm) \
	231	emith_arith_r_imm(4, r, ~(imm))
	232
	233	// fake conditionals (using SJMP instead)
8796b7ee	234	#define emith_move_r_imm_c(cond, r, imm) { \
	235	(void)(cond); \
	236	emith_move_r_imm(r, imm); \
	237	}
	238
80599a42	239	#define emith_add_r_imm_c(cond, r, imm) { \
80599a42	240	(void)(cond); \
3863edbd	241	emith_add_r_imm(r, imm); \
80599a42	242	}
80599a42	243
80599a42	244	#define emith_sub_r_imm_c(cond, r, imm) { \
80599a42	245	(void)(cond); \
3863edbd	246	emith_sub_r_imm(r, imm); \
	247	}
	248
b081408f	249	#define emith_or_r_imm_c(cond, r, imm) \
	250	emith_or_r_imm(r, imm)
	251	#define emith_eor_r_imm_c(cond, r, imm) \
	252	emith_eor_r_imm(r, imm)
	253	#define emith_bic_r_imm_c(cond, r, imm) \
	254	emith_bic_r_imm(r, imm)
	255	#define emith_ror_c(cond, d, s, cnt) \
	256	emith_ror(d, s, cnt)
	257
	258	#define emith_read_r_r_offs_c(cond, r, rs, offs) \
	259	emith_read_r_r_offs(r, rs, offs)
	260	#define emith_write_r_r_offs_c(cond, r, rs, offs) \
	261	emith_write_r_r_offs(r, rs, offs)
	262	#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
	263	emith_read8_r_r_offs(r, rs, offs)
	264	#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
	265	emith_write8_r_r_offs(r, rs, offs)
	266	#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
	267	emith_read16_r_r_offs(r, rs, offs)
	268	#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
	269	emith_write16_r_r_offs(r, rs, offs)
	270	#define emith_jump_reg_c(cond, r) \
	271	emith_jump_reg(r)
	272	#define emith_jump_ctx_c(cond, offs) \
	273	emith_jump_ctx(offs)
	274	#define emith_ret_c(cond) \
	275	emith_ret()
e05b81fc	276
52d759c3	277	// _r_r_imm
e05b81fc	278	#define emith_add_r_r_imm(d, s, imm) { \
	279	if (d != s) \
	280	emith_move_r_r(d, s); \
	281	emith_add_r_imm(d, imm); \
	282	}
	283
52d759c3	284	#define emith_and_r_r_imm(d, s, imm) { \
	285	if (d != s) \
	286	emith_move_r_r(d, s); \
18b94127	287	emith_and_r_imm(d, imm); \
52d759c3	288	}
52d759c3	289
80599a42	290	// shift
	291	#define emith_shift(op, d, s, cnt) { \
	292	if (d != s) \
	293	emith_move_r_r(d, s); \
	294	EMIT_OP_MODRM(0xc1, 3, op, d); \
	295	EMIT(cnt, u8); \
	296	}
	297
80599a42	298	#define emith_lsl(d, s, cnt) \
	299	emith_shift(4, d, s, cnt)
	300
3863edbd	301	#define emith_lsr(d, s, cnt) \
	302	emith_shift(5, d, s, cnt)
	303
	304	#define emith_asr(d, s, cnt) \
	305	emith_shift(7, d, s, cnt)
	306
ed8cf79b	307	#define emith_rol(d, s, cnt) \
	308	emith_shift(0, d, s, cnt)
	309
	310	#define emith_ror(d, s, cnt) \
	311	emith_shift(1, d, s, cnt)
	312
	313	#define emith_rolc(r) \
	314	EMIT_OP_MODRM(0xd1, 3, 2, r)
	315
	316	#define emith_rorc(r) \
	317	EMIT_OP_MODRM(0xd1, 3, 3, r)
	318
80599a42	319	// misc
	320	#define emith_push(r) \
	321	EMIT_OP(0x50 + (r))
	322
e05b81fc	323	#define emith_push_imm(imm) { \
	324	EMIT_OP(0x68); \
	325	EMIT(imm, u32); \
	326	}
	327
80599a42	328	#define emith_pop(r) \
	329	EMIT_OP(0x58 + (r))
	330
	331	#define emith_neg_r(r) \
	332	EMIT_OP_MODRM(0xf7, 3, 3, r)
	333
	334	#define emith_clear_msb(d, s, count) { \
	335	u32 t = (u32)-1; \
	336	t >>= count; \
	337	if (d != s) \
	338	emith_move_r_r(d, s); \
	339	emith_and_r_imm(d, t); \
	340	}
	341
f0d7b1fa	342	#define emith_clear_msb_c(cond, d, s, count) { \
	343	(void)(cond); \
	344	emith_clear_msb(d, s, count); \
	345	}
	346
80599a42	347	#define emith_sext(d, s, bits) { \
	348	emith_lsl(d, s, 32 - (bits)); \
	349	emith_asr(d, d, 32 - (bits)); \
	350	}
	351
f0d7b1fa	352	#define emith_setc(r) { \
f0d7b1fa	353	EMIT_OP(0x0f); \
8b4f38f4	354	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
f0d7b1fa	355	}
f0d7b1fa	356
80599a42	357	// XXX: stupid mess
3863edbd	358	#define emith_mul_(op, dlo, dhi, s1, s2) { \
80599a42	359	int rmr; \
3863edbd	360	if (dlo != xAX && dhi != xAX) \
80599a42	361	emith_push(xAX); \
3863edbd	362	if (dlo != xDX && dhi != xDX) \
3863edbd	363	emith_push(xDX); \
80599a42	364	if ((s1) == xAX) \
	365	rmr = s2; \
	366	else if ((s2) == xAX) \
	367	rmr = s1; \
	368	else { \
	369	emith_move_r_r(xAX, s1); \
	370	rmr = s2; \
	371	} \
3863edbd	372	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	373	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	374	if (dhi != xDX && dhi != -1) \
	375	emith_push(xDX); \
	376	if (dlo != xAX) \
	377	emith_move_r_r(dlo, xAX); \
	378	if (dhi != xDX && dhi != -1) \
	379	emith_pop(dhi); \
	380	if (dlo != xDX && dhi != xDX) \
	381	emith_pop(xDX); \
	382	if (dlo != xAX && dhi != xAX) \
80599a42	383	emith_pop(xAX); \
80599a42	384	}
80599a42	385
3863edbd	386	#define emith_mul_u64(dlo, dhi, s1, s2) \
	387	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
	388
	389	#define emith_mul_s64(dlo, dhi, s1, s2) \
	390	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
	391
	392	#define emith_mul(d, s1, s2) \
	393	emith_mul_(4, d, -1, s1, s2)
	394
f0d7b1fa	395	// (dlo,dhi) += signed(s1) * signed(s2)
	396	#define emith_mula_s64(dlo, dhi, s1, s2) { \
	397	emith_push(dhi); \
	398	emith_push(dlo); \
	399	emith_mul_(5, dlo, dhi, s1, s2); \
	400	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	401	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	402	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	403	EMIT_SIB(0, 4, 4); \
	404	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	405	emith_add_r_imm(xSP, 4*2); \
	406	}
	407
80599a42	408	// "flag" instructions are the same
80599a42	409	#define emith_subf_r_imm emith_sub_r_imm
3863edbd	410	#define emith_addf_r_r emith_add_r_r
80599a42	411	#define emith_subf_r_r emith_sub_r_r
3863edbd	412	#define emith_adcf_r_r emith_adc_r_r
3863edbd	413	#define emith_sbcf_r_r emith_sbc_r_r
8796b7ee	414	#define emith_eorf_r_r emith_eor_r_r
52d759c3	415	#define emith_negcf_r_r emith_negc_r_r
3863edbd	416
ed8cf79b	417	#define emith_lslf emith_lsl
	418	#define emith_lsrf emith_lsr
	419	#define emith_asrf emith_asr
	420	#define emith_rolf emith_rol
	421	#define emith_rorf emith_ror
	422	#define emith_rolcf emith_rolc
	423	#define emith_rorcf emith_rorc
80599a42	424
b081408f	425	#define emith_deref_op(op, r, rs, offs) do { \
e05b81fc	426	/* mov r <-> [ebp+#offs] */ \
e05b81fc	427	if ((offs) >= 0x80) { \
b081408f	428	EMIT_OP_MODRM(op, 2, r, rs); \
e05b81fc	429	EMIT(offs, u32); \
e05b81fc	430	} else { \
b081408f	431	EMIT_OP_MODRM(op, 1, r, rs); \
e05b81fc	432	EMIT(offs, u8); \
e05b81fc	433	} \
8796b7ee	434	} while (0)
679af8a3	435
a2b8c5a5	436	#define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
a2b8c5a5	437
04092e32	438	#define emith_read_r_r_offs(r, rs, offs) \
	439	emith_deref_op(0x8b, r, rs, offs)
	440
	441	#define emith_write_r_r_offs(r, rs, offs) \
	442	emith_deref_op(0x89, r, rs, offs)
	443
	444	// note: don't use prefixes on this
	445	#define emith_read8_r_r_offs(r, rs, offs) do { \
a2b8c5a5	446	int r_ = r; \
	447	if (!is_abcdx(r)) \
	448	r_ = rcache_get_tmp(); \
04092e32	449	emith_deref_op(0x8a, r_, rs, offs); \
a2b8c5a5	450	if ((r) != r_) { \
	451	emith_move_r_r(r, r_); \
	452	rcache_free_tmp(r_); \
	453	} \
	454	} while (0)
	455
04092e32	456	#define emith_write8_r_r_offs(r, rs, offs) do {\
a2b8c5a5	457	int r_ = r; \
	458	if (!is_abcdx(r)) { \
	459	r_ = rcache_get_tmp(); \
	460	emith_move_r_r(r_, r); \
	461	} \
04092e32	462	emith_deref_op(0x88, r_, rs, offs); \
a2b8c5a5	463	if ((r) != r_) \
	464	rcache_free_tmp(r_); \
	465	} while (0)
	466
b081408f	467	#define emith_read16_r_r_offs(r, rs, offs) { \
b081408f	468	EMIT(0x66, u8); /* operand override */ \
04092e32	469	emith_read_r_r_offs(r, rs, offs); \
b081408f	470	}
	471
	472	#define emith_write16_r_r_offs(r, rs, offs) { \
	473	EMIT(0x66, u8); \
04092e32	474	emith_write_r_r_offs(r, rs, offs); \
b081408f	475	}
b081408f	476
e05b81fc	477	#define emith_ctx_read(r, offs) \
b081408f	478	emith_read_r_r_offs(r, CONTEXT_REG, offs)
e05b81fc	479
e05b81fc	480	#define emith_ctx_write(r, offs) \
b081408f	481	emith_write_r_r_offs(r, CONTEXT_REG, offs)
e05b81fc	482
8796b7ee	483	#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
8796b7ee	484	int r_ = r, offs_ = offs, cnt_ = cnt; \
8b4f38f4	485	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
8796b7ee	486	emith_ctx_read(r_, offs_); \
	487	} while (0)
	488
8796b7ee	489	#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
8796b7ee	490	int r_ = r, offs_ = offs, cnt_ = cnt; \
8b4f38f4	491	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
8796b7ee	492	emith_ctx_write(r_, offs_); \
8796b7ee	493	} while (0)
679af8a3	494
e05b81fc	495	// assumes EBX is free
	496	#define emith_ret_to_ctx(offs) { \
	497	emith_pop(xBX); \
	498	emith_ctx_write(xBX, offs); \
	499	}
	500
679af8a3	501	#define emith_jump(ptr) { \
18b94127	502	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
e898de13	503	EMIT_OP(0xe9); \
679af8a3	504	EMIT(disp, u32); \
	505	}
	506
44e6452e	507	#define emith_jump_patchable(target) \
	508	emith_jump(target)
	509
18b94127	510	#define emith_jump_cond(cond, ptr) { \
	511	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
	512	EMIT(0x0f, u8); \
	513	EMIT_OP(0x80 \| (cond)); \
	514	EMIT(disp, u32); \
	515	}
	516
44e6452e	517	#define emith_jump_cond_patchable(cond, target) \
44e6452e	518	emith_jump_cond(cond, target)
18b94127	519
18b94127	520	#define emith_jump_patch(ptr, target) do { \
44e6452e	521	u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
	522	u32 offs_ = ((u8 )(ptr) == 0x0f) ? 2 : 1; \
	523	EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
18b94127	524	} while (0)
18b94127	525
a2b8c5a5	526	#define emith_jump_at(ptr, target) { \
	527	u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
	528	EMIT_PTR(ptr, 0xe9, u8); \
	529	EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
	530	}
	531
679af8a3	532	#define emith_call(ptr) { \
18b94127	533	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
e898de13	534	EMIT_OP(0xe8); \
679af8a3	535	EMIT(disp, u32); \
	536	}
	537
f0d7b1fa	538	#define emith_call_cond(cond, ptr) \
	539	emith_call(ptr)
	540
e05b81fc	541	#define emith_call_reg(r) \
	542	EMIT_OP_MODRM(0xff, 3, 2, r)
	543
	544	#define emith_call_ctx(offs) { \
b081408f	545	EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
e05b81fc	546	EMIT(offs, u32); \
	547	}
	548
	549	#define emith_ret() \
	550	EMIT_OP(0xc3)
	551
8796b7ee	552	#define emith_jump_reg(r) \
	553	EMIT_OP_MODRM(0xff, 3, 4, r)
	554
e05b81fc	555	#define emith_jump_ctx(offs) { \
b081408f	556	EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
e05b81fc	557	EMIT(offs, u32); \
	558	}
	559
a2b8c5a5	560	#define emith_push_ret()
	561
	562	#define emith_pop_and_ret() \
	563	emith_ret()
	564
8796b7ee	565	#define EMITH_JMP_START(cond) { \
80599a42	566	u8 *cond_ptr; \
	567	JMP8_POS(cond_ptr)
	568
8796b7ee	569	#define EMITH_JMP_END(cond) \
80599a42	570	JMP8_EMIT(cond, cond_ptr); \
679af8a3	571	}
679af8a3	572
b081408f	573	#define EMITH_JMP3_START(cond) { \
	574	u8 cond_ptr, else_ptr; \
	575	JMP8_POS(cond_ptr)
	576
	577	#define EMITH_JMP3_MID(cond) \
	578	JMP8_POS(else_ptr); \
	579	JMP8_EMIT(cond, cond_ptr);
	580
	581	#define EMITH_JMP3_END() \
	582	JMP8_EMIT_NC(else_ptr); \
	583	}
	584
8796b7ee	585	// "simple" jump (no more then a few insns)
b081408f	586	// ARM will use conditional instructions here
8796b7ee	587	#define EMITH_SJMP_START EMITH_JMP_START
	588	#define EMITH_SJMP_END EMITH_JMP_END
	589
b081408f	590	#define EMITH_SJMP3_START EMITH_JMP3_START
	591	#define EMITH_SJMP3_MID EMITH_JMP3_MID
	592	#define EMITH_SJMP3_END EMITH_JMP3_END
	593
f4bb5d6b	594	#define emith_pass_arg_r(arg, reg) { \
f4bb5d6b	595	int rd = 7; \
80599a42	596	host_arg2reg(rd, arg); \
f4bb5d6b	597	emith_move_r_r(rd, reg); \
	598	}
	599
	600	#define emith_pass_arg_imm(arg, imm) { \
	601	int rd = 7; \
80599a42	602	host_arg2reg(rd, arg); \
f4bb5d6b	603	emith_move_r_imm(rd, imm); \
679af8a3	604	}
679af8a3	605
a2b8c5a5	606	#define host_instructions_updated(base, end)
	607
	608	#define host_arg2reg(rd, arg) \
	609	switch (arg) { \
	610	case 0: rd = xAX; break; \
	611	case 1: rd = xDX; break; \
	612	case 2: rd = xCX; break; \
	613	}
	614
65c75cb0	615	/* SH2 drc specific */
8796b7ee	616	#define emith_sh2_drc_entry() { \
	617	emith_push(xBX); \
	618	emith_push(xBP); \
8b4f38f4	619	emith_push(xSI); \
8b4f38f4	620	emith_push(xDI); \
8796b7ee	621	}
	622
	623	#define emith_sh2_drc_exit() { \
8b4f38f4	624	emith_pop(xDI); \
8b4f38f4	625	emith_pop(xSI); \
8796b7ee	626	emith_pop(xBP); \
8796b7ee	627	emith_pop(xBX); \
e05b81fc	628	emith_ret(); \
	629	}
	630
	631	// assumes EBX is free temporary
bf092a36	632	#define emith_sh2_wcall(a, tab) { \
e05b81fc	633	int arg2_; \
	634	host_arg2reg(arg2_, 2); \
	635	emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
	636	EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
	637	EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
f81107f5	638	emith_move_r_r(arg2_, CONTEXT_REG); \
e05b81fc	639	emith_jump_reg(xBX); \
8796b7ee	640	}
8796b7ee	641
80599a42	642	#define emith_sh2_dtbf_loop() { \
	643	u8 jmp0; / negative cycles check */ \
	644	u8 jmp1; / unsinged overflow check */ \
	645	int cr, rn; \
52d759c3	646	int tmp_ = rcache_get_tmp(); \
80599a42	647	cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
	648	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	649	emith_sub_r_imm(rn, 1); \
	650	emith_sub_r_imm(cr, (cycles+1) << 12); \
	651	cycles = 0; \
52d759c3	652	emith_asr(tmp_, cr, 2+12); \
80599a42	653	JMP8_POS(jmp0); /* no negative cycles */ \
52d759c3	654	emith_move_r_imm(tmp_, 0); \
18b94127	655	JMP8_EMIT(ICOND_JNS, jmp0); \
80599a42	656	emith_and_r_imm(cr, 0xffe); \
52d759c3	657	emith_subf_r_r(rn, tmp_); \
80599a42	658	JMP8_POS(jmp1); /* no overflow */ \
	659	emith_neg_r(rn); /* count left */ \
	660	emith_lsl(rn, rn, 2+12); \
	661	emith_or_r_r(cr, rn); \
	662	emith_or_r_imm(cr, 1); \
	663	emith_move_r_imm(rn, 0); \
18b94127	664	JMP8_EMIT(ICOND_JA, jmp1); \
52d759c3	665	rcache_free_tmp(tmp_); \
65c75cb0	666	}
65c75cb0	667
18b94127	668	#define emith_write_sr(sr, srcr) { \
52d759c3	669	int tmp_ = rcache_get_tmp(); \
18b94127	670	emith_clear_msb(tmp_, srcr, 22); \
	671	emith_bic_r_imm(sr, 0x3ff); \
	672	emith_or_r_r(sr, tmp_); \
52d759c3	673	rcache_free_tmp(tmp_); \
ed8cf79b	674	}
ed8cf79b	675
8b4f38f4	676	#define emith_tpop_carry(sr, is_sub) \
	677	emith_lsr(sr, sr, 1)
	678
	679	#define emith_tpush_carry(sr, is_sub) \
	680	emith_adc_r_r(sr, sr)
ed8cf79b	681
f0d7b1fa	682	/*
	683	* if Q
	684	* t = carry(Rn += Rm)
	685	* else
	686	* t = carry(Rn -= Rm)
	687	* T ^= t
	688	*/
	689	#define emith_sh2_div1_step(rn, rm, sr) { \
	690	u8 jmp0, jmp1; \
	691	int tmp_ = rcache_get_tmp(); \
8b4f38f4	692	emith_eor_r_r(tmp_, tmp_); \
f0d7b1fa	693	emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
	694	JMP8_POS(jmp0); /* je do_sub */ \
	695	emith_add_r_r(rn, rm); \
	696	JMP8_POS(jmp1); /* jmp done */ \
18b94127	697	JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
f0d7b1fa	698	emith_sub_r_r(rn, rm); \
18b94127	699	JMP8_EMIT_NC(jmp1); /* done: */ \
f0d7b1fa	700	emith_setc(tmp_); \
8b4f38f4	701	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
f0d7b1fa	702	rcache_free_tmp(tmp_); \
	703	}
	704