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68k cores: fix bcd instructions
[picodrive.git] / cpu / musashi / m68k_in.c
CommitLineData
cc68a136 1/*\r
2must fix:\r
3 callm\r
4 chk\r
5*/\r
6/* ======================================================================== */\r
7/* ========================= LICENSING & COPYRIGHT ======================== */\r
8/* ======================================================================== */\r
9/*\r
10 * MUSASHI\r
c6a4c892 11 * Version 3.31\r
cc68a136 12 *\r
13 * A portable Motorola M680x0 processor emulation engine.\r
c6a4c892 14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.\r
cc68a136 15 *\r
16 * This code may be freely used for non-commercial purposes as long as this\r
17 * copyright notice remains unaltered in the source code and any binary files\r
18 * containing this code in compiled form.\r
19 *\r
20 * All other lisencing terms must be negotiated with the author\r
21 * (Karl Stenerud).\r
22 *\r
23 * The latest version of this code can be obtained at:\r
24 * http://kstenerud.cjb.net\r
25 */\r
26\r
27/* Special thanks to Bart Trzynadlowski for his insight into the\r
28 * undocumented features of this chip:\r
29 *\r
30 * http://dynarec.com/~bart/files/68knotes.txt\r
31 */\r
32\r
33\r
34/* Input file for m68kmake\r
35 * -----------------------\r
36 *\r
37 * All sections begin with 80 X's in a row followed by an end-of-line\r
38 * sequence.\r
39 * After this, m68kmake will expect to find one of the following section\r
40 * identifiers:\r
41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes\r
42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes\r
43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable\r
44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable\r
45 * M68KMAKE_TABLE_BODY - the table itself\r
46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation\r
47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation\r
48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation\r
49 *\r
50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and\r
51 * M68KMAKE_TABLE_BODY must be second last in the file.\r
52 *\r
53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler\r
54 * primitives themselves. Each opcode handler begins with:\r
55 * M68KMAKE_OP(A, B, C, D)\r
56 *\r
57 * where A is the opcode handler name, B is the size of the operation,\r
58 * C denotes any special processing mode, and D denotes a specific\r
59 * addressing mode.\r
60 * For C and D where nothing is specified, use "."\r
61 *\r
62 * Example:\r
63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA\r
64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7\r
65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing\r
66 *\r
67 * All opcode handler primitives end with a closing curly brace "}" at column 1\r
68 *\r
69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,\r
70 * and do not put a closing curly brace at column 1 unless it is\r
71 * marking the end of the handler!\r
72 *\r
73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,\r
74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple\r
75 * opcode handlers to handle variations in the opcode handler.\r
76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.\r
77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only\r
78 * be interpreted on instructions where the corresponding table entry\r
79 * specifies multiple effective addressing modes.\r
80 * Example:\r
81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4\r
82 *\r
83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).\r
84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for\r
85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.\r
86 */\r
87\r
88XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
89M68KMAKE_PROTOTYPE_HEADER\r
90\r
91#ifndef M68KOPS__HEADER\r
92#define M68KOPS__HEADER\r
93\r
94/* ======================================================================== */\r
95/* ============================ OPCODE HANDLERS =========================== */\r
96/* ======================================================================== */\r
97\r
98\r
99\r
100XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
101M68KMAKE_PROTOTYPE_FOOTER\r
102\r
103\r
104/* Build the opcode handler table */\r
105void m68ki_build_opcode_table(void);\r
106\r
107extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
108extern unsigned char m68ki_cycles[][0x10000];\r
109\r
110\r
111/* ======================================================================== */\r
112/* ============================== END OF FILE ============================= */\r
113/* ======================================================================== */\r
114\r
115#endif /* M68KOPS__HEADER */\r
116\r
117\r
118\r
119XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
120M68KMAKE_TABLE_HEADER\r
121\r
122/* ======================================================================== */\r
123/* ========================= OPCODE TABLE BUILDER ========================= */\r
124/* ======================================================================== */\r
125\r
126#include "m68kops.h"\r
127\r
128#define NUM_CPU_TYPES 4\r
129\r
130void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
131unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */\r
132\r
133/* This is used to generate the opcode handler jump table */\r
134typedef struct\r
135{\r
136 void (*opcode_handler)(void); /* handler function */\r
137 unsigned int mask; /* mask on opcode */\r
138 unsigned int match; /* what to match after masking */\r
139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */\r
140} opcode_handler_struct;\r
141\r
142\r
143/* Opcode handler table */\r
144static opcode_handler_struct m68k_opcode_handler_table[] =\r
145{\r
146/* function mask match 000 010 020 040 */\r
147\r
148\r
149\r
150XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
151M68KMAKE_TABLE_FOOTER\r
152\r
153 {0, 0, 0, {0, 0, 0, 0}}\r
154};\r
155\r
156\r
157/* Build the opcode handler jump table */\r
158void m68ki_build_opcode_table(void)\r
159{\r
160 opcode_handler_struct *ostruct;\r
161 int instr;\r
162 int i;\r
163 int j;\r
164 int k;\r
165\r
166 for(i = 0; i < 0x10000; i++)\r
167 {\r
168 /* default to illegal */\r
169 m68ki_instruction_jump_table[i] = m68k_op_illegal;\r
170 for(k=0;k<NUM_CPU_TYPES;k++)\r
171 m68ki_cycles[k][i] = 0;\r
172 }\r
173\r
174 ostruct = m68k_opcode_handler_table;\r
175 while(ostruct->mask != 0xff00)\r
176 {\r
177 for(i = 0;i < 0x10000;i++)\r
178 {\r
179 if((i & ostruct->mask) == ostruct->match)\r
180 {\r
181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;\r
182 for(k=0;k<NUM_CPU_TYPES;k++)\r
183 m68ki_cycles[k][i] = ostruct->cycles[k];\r
184 }\r
185 }\r
186 ostruct++;\r
187 }\r
188 while(ostruct->mask == 0xff00)\r
189 {\r
190 for(i = 0;i <= 0xff;i++)\r
191 {\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
193 for(k=0;k<NUM_CPU_TYPES;k++)\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
195 }\r
196 ostruct++;\r
197 }\r
198 while(ostruct->mask == 0xf1f8)\r
199 {\r
200 for(i = 0;i < 8;i++)\r
201 {\r
202 for(j = 0;j < 8;j++)\r
203 {\r
204 instr = ostruct->match | (i << 9) | j;\r
205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;\r
206 for(k=0;k<NUM_CPU_TYPES;k++)\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];\r
208 }\r
209 }\r
210 ostruct++;\r
211 }\r
212 while(ostruct->mask == 0xfff0)\r
213 {\r
214 for(i = 0;i <= 0x0f;i++)\r
215 {\r
216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
217 for(k=0;k<NUM_CPU_TYPES;k++)\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
219 }\r
220 ostruct++;\r
221 }\r
222 while(ostruct->mask == 0xf1ff)\r
223 {\r
224 for(i = 0;i <= 0x07;i++)\r
225 {\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;\r
227 for(k=0;k<NUM_CPU_TYPES;k++)\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];\r
229 }\r
230 ostruct++;\r
231 }\r
232 while(ostruct->mask == 0xfff8)\r
233 {\r
234 for(i = 0;i <= 0x07;i++)\r
235 {\r
236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
237 for(k=0;k<NUM_CPU_TYPES;k++)\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
239 }\r
240 ostruct++;\r
241 }\r
242 while(ostruct->mask == 0xffff)\r
243 {\r
244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;\r
245 for(k=0;k<NUM_CPU_TYPES;k++)\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];\r
247 ostruct++;\r
248 }\r
249}\r
250\r
251\r
252/* ======================================================================== */\r
253/* ============================== END OF FILE ============================= */\r
254/* ======================================================================== */\r
255\r
256\r
257\r
258XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
259M68KMAKE_OPCODE_HANDLER_HEADER\r
260\r
261#include "m68kcpu.h"\r
c6a4c892 262extern void m68040_fpu_op0(void);\r
263extern void m68040_fpu_op1(void);\r
cc68a136 264\r
265/* ======================================================================== */\r
266/* ========================= INSTRUCTION HANDLERS ========================= */\r
267/* ======================================================================== */\r
268\r
269\r
270\r
271XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
272M68KMAKE_OPCODE_HANDLER_FOOTER\r
273\r
274/* ======================================================================== */\r
275/* ============================== END OF FILE ============================= */\r
276/* ======================================================================== */\r
277\r
278\r
279\r
280XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
281M68KMAKE_TABLE_BODY\r
282\r
283The following table is arranged as follows:\r
284\r
285name: Opcode mnemonic\r
286\r
287size: Operation size\r
288\r
289spec proc: Special processing mode:\r
290 .: normal\r
291 s: static operand\r
292 r: register operand\r
293 rr: register to register\r
294 mm: memory to memory\r
295 er: effective address to register\r
296 re: register to effective address\r
297 dd: data register to data register\r
298 da: data register to address register\r
299 aa: address register to address register\r
300 cr: control register to register\r
301 rc: register to control register\r
302 toc: to condition code register\r
303 tos: to status register\r
304 tou: to user stack pointer\r
305 frc: from condition code register\r
306 frs: from status register\r
307 fru: from user stack pointer\r
308 * for move.x, the special processing mode is a specific\r
309 destination effective addressing mode.\r
310\r
311spec ea: Specific effective addressing mode:\r
312 .: normal\r
313 i: immediate\r
314 d: data register\r
315 a: address register\r
316 ai: address register indirect\r
317 pi: address register indirect with postincrement\r
318 pd: address register indirect with predecrement\r
319 di: address register indirect with displacement\r
320 ix: address register indirect with index\r
321 aw: absolute word address\r
322 al: absolute long address\r
323 pcdi: program counter relative with displacement\r
324 pcix: program counter relative with index\r
325 a7: register specified in instruction is A7\r
326 ax7: register field X of instruction is A7\r
327 ay7: register field Y of instruction is A7\r
328 axy7: register fields X and Y of instruction are A7\r
329\r
330bit pattern: Pattern to recognize this opcode. "." means don't care.\r
331\r
332allowed ea: List of allowed addressing modes:\r
333 .: not present\r
334 A: address register indirect\r
335 +: ARI (address register indirect) with postincrement\r
336 -: ARI with predecrement\r
337 D: ARI with displacement\r
338 X: ARI with index\r
339 W: absolute word address\r
340 L: absolute long address\r
341 d: program counter indirect with displacement\r
342 x: program counter indirect with index\r
343 I: immediate\r
344mode: CPU operating mode for each cpu type. U = user or supervisor,\r
345 S = supervisor only, "." = opcode not present.\r
346\r
347cpu cycles: Base number of cycles required to execute this opcode on the\r
348 specified CPU type.\r
349 Use "." if CPU does not have this opcode.\r
350\r
351\r
352\r
353 spec spec allowed ea mode cpu cycles\r
354name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments\r
355====== ==== ==== ==== ================ ========== = = = = === === === === =============\r
356M68KMAKE_TABLE_START\r
3571010 0 . . 1010............ .......... U U U U 4 4 4 4\r
3581111 0 . . 1111............ .......... U U U U 4 4 4 4\r
c6a4c892 359040fpu0 32 . . 11110010........ .......... . . . U . . . 0\r
360040fpu1 32 . . 11110011........ .......... . . . U . . . 0\r
cc68a136 361abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4\r
362abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16\r
363abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16\r
364abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16\r
365abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16\r
366add 8 er d 1101...000000... .......... U U U U 4 4 2 2\r
367add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2\r
368add 16 er d 1101...001000... .......... U U U U 4 4 2 2\r
369add 16 er a 1101...001001... .......... U U U U 4 4 2 2\r
370add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2\r
371add 32 er d 1101...010000... .......... U U U U 6 6 2 2\r
372add 32 er a 1101...010001... .......... U U U U 6 6 2 2\r
373add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2\r
374add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4\r
375add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4\r
376add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4\r
377adda 16 . d 1101...011000... .......... U U U U 8 8 2 2\r
378adda 16 . a 1101...011001... .......... U U U U 8 8 2 2\r
379adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2\r
380adda 32 . d 1101...111000... .......... U U U U 6 6 2 2\r
381adda 32 . a 1101...111001... .......... U U U U 6 6 2 2\r
382adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2\r
383addi 8 . d 0000011000000... .......... U U U U 8 8 2 2\r
384addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4\r
385addi 16 . d 0000011001000... .......... U U U U 8 8 2 2\r
386addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4\r
387addi 32 . d 0000011010000... .......... U U U U 16 14 2 2\r
388addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4\r
389addq 8 . d 0101...000000... .......... U U U U 4 4 2 2\r
390addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4\r
391addq 16 . d 0101...001000... .......... U U U U 4 4 2 2\r
392addq 16 . a 0101...001001... .......... U U U U 4 4 2 2\r
393addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4\r
394addq 32 . d 0101...010000... .......... U U U U 8 8 2 2\r
395addq 32 . a 0101...010001... .......... U U U U 8 8 2 2\r
396addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4\r
397addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2\r
398addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2\r
399addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2\r
400addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12\r
401addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12\r
402addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12\r
403addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12\r
404addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12\r
405addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12\r
406and 8 er d 1100...000000... .......... U U U U 4 4 2 2\r
407and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2\r
408and 16 er d 1100...001000... .......... U U U U 4 4 2 2\r
409and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2\r
410and 32 er d 1100...010000... .......... U U U U 6 6 2 2\r
411and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2\r
412and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4\r
413and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4\r
414and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4\r
415andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12\r
416andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12\r
417andi 8 . d 0000001000000... .......... U U U U 8 8 2 2\r
418andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4\r
419andi 16 . d 0000001001000... .......... U U U U 8 8 2 2\r
420andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4\r
421andi 32 . d 0000001010000... .......... U U U U 14 14 2 2\r
422andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4\r
423asr 8 s . 1110...000000... .......... U U U U 6 6 6 6\r
424asr 16 s . 1110...001000... .......... U U U U 6 6 6 6\r
425asr 32 s . 1110...010000... .......... U U U U 8 8 6 6\r
426asr 8 r . 1110...000100... .......... U U U U 6 6 6 6\r
427asr 16 r . 1110...001100... .......... U U U U 6 6 6 6\r
428asr 32 r . 1110...010100... .......... U U U U 8 8 6 6\r
429asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5\r
430asl 8 s . 1110...100000... .......... U U U U 6 6 8 8\r
431asl 16 s . 1110...101000... .......... U U U U 6 6 8 8\r
432asl 32 s . 1110...110000... .......... U U U U 8 8 8 8\r
433asl 8 r . 1110...100100... .......... U U U U 6 6 8 8\r
434asl 16 r . 1110...101100... .......... U U U U 6 6 8 8\r
435asl 32 r . 1110...110100... .......... U U U U 8 8 8 8\r
436asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6\r
437bcc 8 . . 0110............ .......... U U U U 10 10 6 6\r
438bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6\r
439bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6\r
440bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4\r
441bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4\r
442bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4\r
443bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4\r
444bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4\r
445bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4\r
446bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4\r
447bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4\r
448bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct\r
449bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20\r
450bfclr 32 . d 1110110011000... .......... . . U U . . 12 12\r
451bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20\r
452bfexts 32 . d 1110101111000... .......... . . U U . . 8 8\r
453bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15\r
454bfextu 32 . d 1110100111000... .......... . . U U . . 8 8\r
455bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15\r
456bfffo 32 . d 1110110111000... .......... . . U U . . 18 18\r
457bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28\r
458bfins 32 . d 1110111111000... .......... . . U U . . 10 10\r
459bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17\r
460bfset 32 . d 1110111011000... .......... . . U U . . 12 12\r
461bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20\r
462bftst 32 . d 1110100011000... .......... . . U U . . 6 6\r
463bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13\r
464bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10\r
465bra 8 . . 01100000........ .......... U U U U 10 10 10 10\r
466bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10\r
467bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10\r
468bset 32 r d 0000...111000... .......... U U U U 8 8 4 4\r
469bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4\r
470bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4\r
471bset 32 s d 0000100011000... .......... U U U U 12 12 4 4\r
472bsr 8 . . 01100001........ .......... U U U U 18 18 7 7\r
473bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7\r
474bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7\r
475btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4\r
476btst 32 r d 0000...100000... .......... U U U U 6 6 4 4\r
477btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4\r
478btst 32 s d 0000100000000... .......... U U U U 10 10 4 4\r
479callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated\r
480cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12\r
481cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12\r
482cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12\r
483cas2 16 . . 0000110011111100 .......... . . U U . . 12 12\r
484cas2 32 . . 0000111011111100 .......... . . U U . . 12 12\r
485chk 16 . d 0100...110000... .......... U U U U 10 8 8 8\r
486chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8\r
487chk 32 . d 0100...100000... .......... . . U U . . 8 8\r
488chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8\r
489chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23\r
490chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23\r
491chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18\r
492chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23\r
493chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23\r
494chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18\r
495chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23\r
496chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23\r
497chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18\r
498clr 8 . d 0100001000000... .......... U U U U 4 4 2 2\r
d5715559 499clr 8 . . 0100001000...... A+-DXWL... U U U U 8 4 4 4\r
cc68a136 500clr 16 . d 0100001001000... .......... U U U U 4 4 2 2\r
d5715559 501clr 16 . . 0100001001...... A+-DXWL... U U U U 8 4 4 4\r
cc68a136 502clr 32 . d 0100001010000... .......... U U U U 6 6 2 2\r
503clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4\r
504cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2\r
505cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
506cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2\r
507cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2\r
508cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
509cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2\r
510cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2\r
511cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2\r
512cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4\r
513cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4\r
514cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4\r
515cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4\r
516cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4\r
517cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4\r
518cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2\r
519cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2\r
520cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7\r
521cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9\r
522cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2\r
523cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2\r
524cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7\r
525cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9\r
526cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2\r
527cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2\r
528cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7\r
529cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9\r
530cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9\r
531cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9\r
532cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9\r
533cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9\r
534cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9\r
535cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9\r
536cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated\r
537cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated\r
538cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated\r
539cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated\r
540cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated\r
541dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6\r
542dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6\r
543dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6\r
544divs 16 . d 1000...111000... .......... U U U U 158 122 56 56\r
545divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56\r
546divu 16 . d 1000...011000... .......... U U U U 140 108 44 44\r
547divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44\r
548divl 32 . d 0100110001000... .......... . . U U . . 84 84\r
549divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84\r
550eor 8 . d 1011...100000... .......... U U U U 4 4 2 2\r
551eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4\r
552eor 16 . d 1011...101000... .......... U U U U 4 4 2 2\r
553eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4\r
554eor 32 . d 1011...110000... .......... U U U U 8 6 2 2\r
555eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4\r
556eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12\r
557eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12\r
558eori 8 . d 0000101000000... .......... U U U U 8 8 2 2\r
559eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4\r
560eori 16 . d 0000101001000... .......... U U U U 8 8 2 2\r
561eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4\r
562eori 32 . d 0000101010000... .......... U U U U 16 14 2 2\r
563eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4\r
564exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2\r
565exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2\r
566exg 32 da . 1100...110001... .......... U U U U 6 6 2 2\r
567ext 16 . . 0100100010000... .......... U U U U 4 4 4 4\r
568ext 32 . . 0100100011000... .......... U U U U 4 4 4 4\r
569extb 32 . . 0100100111000... .......... . . U U . . 4 4\r
570illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4\r
571jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0\r
572jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0\r
573lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2\r
574link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5\r
575link 16 . . 0100111001010... .......... U U U U 16 16 5 5\r
576link 32 . a7 0100100000001111 .......... . . U U . . 6 6\r
577link 32 . . 0100100000001... .......... . . U U . . 6 6\r
578lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4\r
579lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4\r
580lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4\r
581lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6\r
582lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6\r
583lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6\r
584lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5\r
585lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4\r
586lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4\r
587lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4\r
588lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6\r
589lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6\r
590lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6\r
591lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5\r
592move 8 d d 0001...000000... .......... U U U U 4 4 2 2\r
593move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
594move 8 ai d 0001...010000... .......... U U U U 8 8 4 4\r
595move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4\r
596move 8 pi d 0001...011000... .......... U U U U 8 8 4 4\r
597move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4\r
598move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4\r
599move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4\r
600move 8 pd d 0001...100000... .......... U U U U 8 8 5 5\r
601move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5\r
602move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5\r
603move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5\r
604move 8 di d 0001...101000... .......... U U U U 12 12 5 5\r
605move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5\r
606move 8 ix d 0001...110000... .......... U U U U 14 14 7 7\r
607move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7\r
608move 8 aw d 0001000111000... .......... U U U U 12 12 4 4\r
609move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4\r
610move 8 al d 0001001111000... .......... U U U U 16 16 6 6\r
611move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6\r
612move 16 d d 0011...000000... .......... U U U U 4 4 2 2\r
613move 16 d a 0011...000001... .......... U U U U 4 4 2 2\r
614move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
615move 16 ai d 0011...010000... .......... U U U U 8 8 4 4\r
616move 16 ai a 0011...010001... .......... U U U U 8 8 4 4\r
617move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4\r
618move 16 pi d 0011...011000... .......... U U U U 8 8 4 4\r
619move 16 pi a 0011...011001... .......... U U U U 8 8 4 4\r
620move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4\r
621move 16 pd d 0011...100000... .......... U U U U 8 8 5 5\r
622move 16 pd a 0011...100001... .......... U U U U 8 8 5 5\r
623move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5\r
624move 16 di d 0011...101000... .......... U U U U 12 12 5 5\r
625move 16 di a 0011...101001... .......... U U U U 12 12 5 5\r
626move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5\r
627move 16 ix d 0011...110000... .......... U U U U 14 14 7 7\r
628move 16 ix a 0011...110001... .......... U U U U 14 14 7 7\r
629move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7\r
630move 16 aw d 0011000111000... .......... U U U U 12 12 4 4\r
631move 16 aw a 0011000111001... .......... U U U U 12 12 4 4\r
632move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4\r
633move 16 al d 0011001111000... .......... U U U U 16 16 6 6\r
634move 16 al a 0011001111001... .......... U U U U 16 16 6 6\r
635move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6\r
636move 32 d d 0010...000000... .......... U U U U 4 4 2 2\r
637move 32 d a 0010...000001... .......... U U U U 4 4 2 2\r
638move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2\r
639move 32 ai d 0010...010000... .......... U U U U 12 12 4 4\r
640move 32 ai a 0010...010001... .......... U U U U 12 12 4 4\r
641move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4\r
642move 32 pi d 0010...011000... .......... U U U U 12 12 4 4\r
643move 32 pi a 0010...011001... .......... U U U U 12 12 4 4\r
644move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4\r
645move 32 pd d 0010...100000... .......... U U U U 12 14 5 5\r
646move 32 pd a 0010...100001... .......... U U U U 12 14 5 5\r
647move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5\r
648move 32 di d 0010...101000... .......... U U U U 16 16 5 5\r
649move 32 di a 0010...101001... .......... U U U U 16 16 5 5\r
650move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5\r
651move 32 ix d 0010...110000... .......... U U U U 18 18 7 7\r
652move 32 ix a 0010...110001... .......... U U U U 18 18 7 7\r
653move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7\r
654move 32 aw d 0010000111000... .......... U U U U 16 16 4 4\r
655move 32 aw a 0010000111001... .......... U U U U 16 16 4 4\r
656move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4\r
657move 32 al d 0010001111000... .......... U U U U 20 20 6 6\r
658move 32 al a 0010001111001... .......... U U U U 20 20 6 6\r
659move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6\r
660movea 16 . d 0011...001000... .......... U U U U 4 4 2 2\r
661movea 16 . a 0011...001001... .......... U U U U 4 4 2 2\r
662movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
663movea 32 . d 0010...001000... .......... U U U U 4 4 2 2\r
664movea 32 . a 0010...001001... .......... U U U U 4 4 2 2\r
665movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2\r
666move 16 frc d 0100001011000... .......... . U U U . 4 4 4\r
667move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4\r
668move 16 toc d 0100010011000... .......... U U U U 12 12 4 4\r
669move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4\r
670move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000\r
671move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000\r
672move 16 tos d 0100011011000... .......... S S S S 12 12 8 8\r
673move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8\r
674move 32 fru . 0100111001101... .......... S S S S 4 6 2 2\r
675move 32 tou . 0100111001100... .......... S S S S 4 6 2 2\r
676movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6\r
677movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12\r
678movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4\r
679movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4\r
680movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4\r
681movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4\r
682movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8\r
683movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9\r
684movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11\r
685movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8\r
686movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8\r
687movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9\r
688movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11\r
689movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8\r
690movep 16 er . 0000...100001... .......... U U U U 16 16 12 12\r
691movep 32 er . 0000...101001... .......... U U U U 24 24 18 18\r
692movep 16 re . 0000...110001... .......... U U U U 16 16 11 11\r
693movep 32 re . 0000...111001... .......... U U U U 24 24 17 17\r
694moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2\r
695moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5\r
696moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5\r
697moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5\r
698move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing\r
699muls 16 . d 1100...111000... .......... U U U U 54 32 27 27\r
700muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27\r
701mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27\r
702mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27\r
703mull 32 . d 0100110000000... .......... . . U U . . 43 43\r
704mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43\r
705nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6\r
706nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6\r
707neg 8 . d 0100010000000... .......... U U U U 4 4 2 2\r
708neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4\r
709neg 16 . d 0100010001000... .......... U U U U 4 4 2 2\r
710neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4\r
711neg 32 . d 0100010010000... .......... U U U U 6 6 2 2\r
712neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4\r
713negx 8 . d 0100000000000... .......... U U U U 4 4 2 2\r
714negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4\r
715negx 16 . d 0100000001000... .......... U U U U 4 4 2 2\r
716negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4\r
717negx 32 . d 0100000010000... .......... U U U U 6 6 2 2\r
718negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4\r
719nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2\r
720not 8 . d 0100011000000... .......... U U U U 4 4 2 2\r
721not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4\r
722not 16 . d 0100011001000... .......... U U U U 4 4 2 2\r
723not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4\r
724not 32 . d 0100011010000... .......... U U U U 6 6 2 2\r
725not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4\r
726or 8 er d 1000...000000... .......... U U U U 4 4 2 2\r
727or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2\r
728or 16 er d 1000...001000... .......... U U U U 4 4 2 2\r
729or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2\r
730or 32 er d 1000...010000... .......... U U U U 6 6 2 2\r
731or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2\r
732or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4\r
733or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4\r
734or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4\r
735ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12\r
736ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12\r
737ori 8 . d 0000000000000... .......... U U U U 8 8 2 2\r
738ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4\r
739ori 16 . d 0000000001000... .......... U U U U 8 8 2 2\r
740ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4\r
741ori 32 . d 0000000010000... .......... U U U U 16 14 2 2\r
742ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4\r
743pack 16 rr . 1000...101000... .......... . . U U . . 6 6\r
744pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13\r
745pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13\r
746pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13\r
747pack 16 mm . 1000...101001... .......... . . U U . . 13 13\r
748pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5\r
749pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing\r
750reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0\r
751ror 8 s . 1110...000011... .......... U U U U 6 6 8 8\r
752ror 16 s . 1110...001011... .......... U U U U 6 6 8 8\r
753ror 32 s . 1110...010011... .......... U U U U 8 8 8 8\r
754ror 8 r . 1110...000111... .......... U U U U 6 6 8 8\r
755ror 16 r . 1110...001111... .......... U U U U 6 6 8 8\r
756ror 32 r . 1110...010111... .......... U U U U 8 8 8 8\r
757ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7\r
758rol 8 s . 1110...100011... .......... U U U U 6 6 8 8\r
759rol 16 s . 1110...101011... .......... U U U U 6 6 8 8\r
760rol 32 s . 1110...110011... .......... U U U U 8 8 8 8\r
761rol 8 r . 1110...100111... .......... U U U U 6 6 8 8\r
762rol 16 r . 1110...101111... .......... U U U U 6 6 8 8\r
763rol 32 r . 1110...110111... .......... U U U U 8 8 8 8\r
764rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7\r
765roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12\r
766roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12\r
767roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12\r
768roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12\r
769roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12\r
770roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12\r
771roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5\r
772roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12\r
773roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12\r
774roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12\r
775roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12\r
776roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12\r
777roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12\r
778roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5\r
779rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10\r
780rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated\r
781rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated\r
782rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14\r
783rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10\r
784sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4\r
785sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16\r
786sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16\r
787sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16\r
788sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16\r
789st 8 . d 0101000011000... .......... U U U U 6 4 4 4\r
790st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6\r
791sf 8 . d 0101000111000... .......... U U U U 4 4 4 4\r
792sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6\r
793scc 8 . d 0101....11000... .......... U U U U 4 4 4 4\r
794scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6\r
795stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8\r
796sub 8 er d 1001...000000... .......... U U U U 4 4 2 2\r
797sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
798sub 16 er d 1001...001000... .......... U U U U 4 4 2 2\r
799sub 16 er a 1001...001001... .......... U U U U 4 4 2 2\r
800sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2\r
801sub 32 er d 1001...010000... .......... U U U U 6 6 2 2\r
802sub 32 er a 1001...010001... .......... U U U U 6 6 2 2\r
803sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2\r
804sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4\r
805sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4\r
806sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4\r
807suba 16 . d 1001...011000... .......... U U U U 8 8 2 2\r
808suba 16 . a 1001...011001... .......... U U U U 8 8 2 2\r
809suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2\r
810suba 32 . d 1001...111000... .......... U U U U 6 6 2 2\r
811suba 32 . a 1001...111001... .......... U U U U 6 6 2 2\r
812suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2\r
813subi 8 . d 0000010000000... .......... U U U U 8 8 2 2\r
814subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4\r
815subi 16 . d 0000010001000... .......... U U U U 8 8 2 2\r
816subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4\r
817subi 32 . d 0000010010000... .......... U U U U 16 14 2 2\r
818subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4\r
819subq 8 . d 0101...100000... .......... U U U U 4 4 2 2\r
820subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4\r
821subq 16 . d 0101...101000... .......... U U U U 4 4 2 2\r
822subq 16 . a 0101...101001... .......... U U U U 8 4 2 2\r
823subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4\r
824subq 32 . d 0101...110000... .......... U U U U 8 8 2 2\r
825subq 32 . a 0101...110001... .......... U U U U 8 8 2 2\r
826subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4\r
827subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2\r
828subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2\r
829subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2\r
830subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12\r
831subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12\r
832subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12\r
833subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12\r
834subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12\r
835subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12\r
836swap 32 . . 0100100001000... .......... U U U U 4 4 4 4\r
837tas 8 . d 0100101011000... .......... U U U U 4 4 4 4\r
838tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12\r
839trap 0 . . 010011100100.... .......... U U U U 4 4 4 4\r
840trapt 0 . . 0101000011111100 .......... . . U U . . 4 4\r
841trapt 16 . . 0101000011111010 .......... . . U U . . 6 6\r
842trapt 32 . . 0101000011111011 .......... . . U U . . 8 8\r
843trapf 0 . . 0101000111111100 .......... . . U U . . 4 4\r
844trapf 16 . . 0101000111111010 .......... . . U U . . 6 6\r
845trapf 32 . . 0101000111111011 .......... . . U U . . 8 8\r
846trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4\r
847trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6\r
848trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8\r
849trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4\r
850tst 8 . d 0100101000000... .......... U U U U 4 4 2 2\r
851tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2\r
852tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7\r
853tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9\r
854tst 8 . i 0100101000111100 .......... . . U U . . 6 6\r
855tst 16 . d 0100101001000... .......... U U U U 4 4 2 2\r
856tst 16 . a 0100101001001... .......... . . U U . . 2 2\r
857tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2\r
858tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7\r
859tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9\r
860tst 16 . i 0100101001111100 .......... . . U U . . 6 6\r
861tst 32 . d 0100101010000... .......... U U U U 4 4 2 2\r
862tst 32 . a 0100101010001... .......... . . U U . . 2 2\r
863tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2\r
864tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7\r
865tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9\r
866tst 32 . i 0100101010111100 .......... . . U U . . 6 6\r
867unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6\r
868unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6\r
869unpk 16 rr . 1000...110000... .......... . . U U . . 8 8\r
870unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13\r
871unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13\r
872unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13\r
873unpk 16 mm . 1000...110001... .......... . . U U . . 13 13\r
874\r
875\r
876\r
877XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
878M68KMAKE_OPCODE_HANDLER_BODY\r
879\r
880M68KMAKE_OP(1010, 0, ., .)\r
881{\r
882 m68ki_exception_1010();\r
883}\r
884\r
885\r
886M68KMAKE_OP(1111, 0, ., .)\r
887{\r
888 m68ki_exception_1111();\r
889}\r
890\r
891\r
c6a4c892 892M68KMAKE_OP(040fpu0, 32, ., .)\r
893{\r
894 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
895 {\r
896 m68040_fpu_op0();\r
897 return;\r
898 }\r
899 m68ki_exception_1111();\r
900}\r
901\r
902\r
903M68KMAKE_OP(040fpu1, 32, ., .)\r
904{\r
905 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
906 {\r
907 m68040_fpu_op1();\r
908 return;\r
909 }\r
910 m68ki_exception_1111();\r
911}\r
912\r
913\r
914\r
cc68a136 915M68KMAKE_OP(abcd, 8, rr, .)\r
916{\r
917 uint* r_dst = &DX;\r
918 uint src = DY;\r
919 uint dst = *r_dst;\r
920 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
c6e1e977 921 uint corf = 0;\r
cc68a136 922\r
923 if(res > 9)\r
c6e1e977 924 corf = 6;\r
cc68a136 925 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
c6e1e977 926 FLAG_V = ~res; /* Undefined V behavior */\r
927\r
928 res += corf;\r
929 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
cc68a136 930 if(FLAG_C)\r
931 res -= 0xa0;\r
932\r
933 FLAG_V &= res; /* Undefined V behavior part II */\r
934 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
935\r
936 res = MASK_OUT_ABOVE_8(res);\r
937 FLAG_Z |= res;\r
938\r
939 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
940}\r
941\r
942\r
943M68KMAKE_OP(abcd, 8, mm, ax7)\r
944{\r
945 uint src = OPER_AY_PD_8();\r
946 uint ea = EA_A7_PD_8();\r
947 uint dst = m68ki_read_8(ea);\r
948 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
c6e1e977 949 uint corf = 0;\r
cc68a136 950\r
951 if(res > 9)\r
c6e1e977 952 corf = 6;\r
cc68a136 953 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
c6e1e977 954 FLAG_V = ~res; /* Undefined V behavior */\r
955\r
956 res += corf;\r
957 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
cc68a136 958 if(FLAG_C)\r
959 res -= 0xa0;\r
960\r
961 FLAG_V &= res; /* Undefined V behavior part II */\r
962 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
963\r
964 res = MASK_OUT_ABOVE_8(res);\r
965 FLAG_Z |= res;\r
966\r
967 m68ki_write_8(ea, res);\r
968}\r
969\r
970\r
971M68KMAKE_OP(abcd, 8, mm, ay7)\r
972{\r
973 uint src = OPER_A7_PD_8();\r
974 uint ea = EA_AX_PD_8();\r
975 uint dst = m68ki_read_8(ea);\r
976 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
c6e1e977 977 uint corf = 0;\r
cc68a136 978\r
979 if(res > 9)\r
c6e1e977 980 corf = 6;\r
cc68a136 981 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
c6e1e977 982 FLAG_V = ~res; /* Undefined V behavior */\r
983\r
984 res += corf;\r
985 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
cc68a136 986 if(FLAG_C)\r
987 res -= 0xa0;\r
988\r
989 FLAG_V &= res; /* Undefined V behavior part II */\r
990 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
991\r
992 res = MASK_OUT_ABOVE_8(res);\r
993 FLAG_Z |= res;\r
994\r
995 m68ki_write_8(ea, res);\r
996}\r
997\r
998\r
999M68KMAKE_OP(abcd, 8, mm, axy7)\r
1000{\r
1001 uint src = OPER_A7_PD_8();\r
1002 uint ea = EA_A7_PD_8();\r
1003 uint dst = m68ki_read_8(ea);\r
1004 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
c6e1e977 1005 uint corf = 0;\r
cc68a136 1006\r
1007 if(res > 9)\r
c6e1e977 1008 corf = 6;\r
cc68a136 1009 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
c6e1e977 1010 FLAG_V = ~res; /* Undefined V behavior */\r
1011\r
1012 res += corf;\r
1013 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
cc68a136 1014 if(FLAG_C)\r
1015 res -= 0xa0;\r
1016\r
1017 FLAG_V &= res; /* Undefined V behavior part II */\r
1018 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1019\r
1020 res = MASK_OUT_ABOVE_8(res);\r
1021 FLAG_Z |= res;\r
1022\r
1023 m68ki_write_8(ea, res);\r
1024}\r
1025\r
1026\r
1027M68KMAKE_OP(abcd, 8, mm, .)\r
1028{\r
1029 uint src = OPER_AY_PD_8();\r
1030 uint ea = EA_AX_PD_8();\r
1031 uint dst = m68ki_read_8(ea);\r
1032 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
c6e1e977 1033 uint corf = 0;\r
cc68a136 1034\r
1035 if(res > 9)\r
c6e1e977 1036 corf = 6;\r
cc68a136 1037 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
c6e1e977 1038 FLAG_V = ~res; /* Undefined V behavior */\r
1039\r
1040 res += corf;\r
1041 FLAG_X = FLAG_C = (res > 0x9f) << 8;\r
cc68a136 1042 if(FLAG_C)\r
1043 res -= 0xa0;\r
1044\r
1045 FLAG_V &= res; /* Undefined V behavior part II */\r
1046 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1047\r
1048 res = MASK_OUT_ABOVE_8(res);\r
1049 FLAG_Z |= res;\r
1050\r
1051 m68ki_write_8(ea, res);\r
1052}\r
1053\r
1054\r
1055M68KMAKE_OP(add, 8, er, d)\r
1056{\r
1057 uint* r_dst = &DX;\r
1058 uint src = MASK_OUT_ABOVE_8(DY);\r
1059 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1060 uint res = src + dst;\r
1061\r
1062 FLAG_N = NFLAG_8(res);\r
1063 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1064 FLAG_X = FLAG_C = CFLAG_8(res);\r
1065 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1066\r
1067 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1068}\r
1069\r
1070\r
1071M68KMAKE_OP(add, 8, er, .)\r
1072{\r
1073 uint* r_dst = &DX;\r
1074 uint src = M68KMAKE_GET_OPER_AY_8;\r
1075 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1076 uint res = src + dst;\r
1077\r
1078 FLAG_N = NFLAG_8(res);\r
1079 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1080 FLAG_X = FLAG_C = CFLAG_8(res);\r
1081 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1082\r
1083 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1084}\r
1085\r
1086\r
1087M68KMAKE_OP(add, 16, er, d)\r
1088{\r
1089 uint* r_dst = &DX;\r
1090 uint src = MASK_OUT_ABOVE_16(DY);\r
1091 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1092 uint res = src + dst;\r
1093\r
1094 FLAG_N = NFLAG_16(res);\r
1095 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1096 FLAG_X = FLAG_C = CFLAG_16(res);\r
1097 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1098\r
1099 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1100}\r
1101\r
1102\r
1103M68KMAKE_OP(add, 16, er, a)\r
1104{\r
1105 uint* r_dst = &DX;\r
1106 uint src = MASK_OUT_ABOVE_16(AY);\r
1107 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1108 uint res = src + dst;\r
1109\r
1110 FLAG_N = NFLAG_16(res);\r
1111 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1112 FLAG_X = FLAG_C = CFLAG_16(res);\r
1113 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1114\r
1115 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1116}\r
1117\r
1118\r
1119M68KMAKE_OP(add, 16, er, .)\r
1120{\r
1121 uint* r_dst = &DX;\r
1122 uint src = M68KMAKE_GET_OPER_AY_16;\r
1123 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1124 uint res = src + dst;\r
1125\r
1126 FLAG_N = NFLAG_16(res);\r
1127 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1128 FLAG_X = FLAG_C = CFLAG_16(res);\r
1129 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1130\r
1131 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1132}\r
1133\r
1134\r
1135M68KMAKE_OP(add, 32, er, d)\r
1136{\r
1137 uint* r_dst = &DX;\r
1138 uint src = DY;\r
1139 uint dst = *r_dst;\r
1140 uint res = src + dst;\r
1141\r
1142 FLAG_N = NFLAG_32(res);\r
1143 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1144 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1145 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1146\r
1147 *r_dst = FLAG_Z;\r
1148}\r
1149\r
1150\r
1151M68KMAKE_OP(add, 32, er, a)\r
1152{\r
1153 uint* r_dst = &DX;\r
1154 uint src = AY;\r
1155 uint dst = *r_dst;\r
1156 uint res = src + dst;\r
1157\r
1158 FLAG_N = NFLAG_32(res);\r
1159 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1160 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1161 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1162\r
1163 *r_dst = FLAG_Z;\r
1164}\r
1165\r
1166\r
1167M68KMAKE_OP(add, 32, er, .)\r
1168{\r
1169 uint* r_dst = &DX;\r
1170 uint src = M68KMAKE_GET_OPER_AY_32;\r
1171 uint dst = *r_dst;\r
1172 uint res = src + dst;\r
1173\r
1174 FLAG_N = NFLAG_32(res);\r
1175 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1176 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1177 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1178\r
1179 *r_dst = FLAG_Z;\r
1180}\r
1181\r
1182\r
1183M68KMAKE_OP(add, 8, re, .)\r
1184{\r
1185 uint ea = M68KMAKE_GET_EA_AY_8;\r
1186 uint src = MASK_OUT_ABOVE_8(DX);\r
1187 uint dst = m68ki_read_8(ea);\r
1188 uint res = src + dst;\r
1189\r
1190 FLAG_N = NFLAG_8(res);\r
1191 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1192 FLAG_X = FLAG_C = CFLAG_8(res);\r
1193 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1194\r
1195 m68ki_write_8(ea, FLAG_Z);\r
1196}\r
1197\r
1198\r
1199M68KMAKE_OP(add, 16, re, .)\r
1200{\r
1201 uint ea = M68KMAKE_GET_EA_AY_16;\r
1202 uint src = MASK_OUT_ABOVE_16(DX);\r
1203 uint dst = m68ki_read_16(ea);\r
1204 uint res = src + dst;\r
1205\r
1206 FLAG_N = NFLAG_16(res);\r
1207 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1208 FLAG_X = FLAG_C = CFLAG_16(res);\r
1209 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1210\r
1211 m68ki_write_16(ea, FLAG_Z);\r
1212}\r
1213\r
1214\r
1215M68KMAKE_OP(add, 32, re, .)\r
1216{\r
1217 uint ea = M68KMAKE_GET_EA_AY_32;\r
1218 uint src = DX;\r
1219 uint dst = m68ki_read_32(ea);\r
1220 uint res = src + dst;\r
1221\r
1222 FLAG_N = NFLAG_32(res);\r
1223 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1224 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1225 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1226\r
1227 m68ki_write_32(ea, FLAG_Z);\r
1228}\r
1229\r
1230\r
1231M68KMAKE_OP(adda, 16, ., d)\r
1232{\r
1233 uint* r_dst = &AX;\r
1234\r
1235 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));\r
1236}\r
1237\r
1238\r
1239M68KMAKE_OP(adda, 16, ., a)\r
1240{\r
1241 uint* r_dst = &AX;\r
1242\r
1243 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));\r
1244}\r
1245\r
1246\r
1247M68KMAKE_OP(adda, 16, ., .)\r
1248{\r
1249 uint* r_dst = &AX;\r
c6a4c892 1250 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
cc68a136 1251\r
c6a4c892 1252 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);\r
cc68a136 1253}\r
1254\r
1255\r
1256M68KMAKE_OP(adda, 32, ., d)\r
1257{\r
1258 uint* r_dst = &AX;\r
1259\r
1260 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);\r
1261}\r
1262\r
1263\r
1264M68KMAKE_OP(adda, 32, ., a)\r
1265{\r
1266 uint* r_dst = &AX;\r
1267\r
1268 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);\r
1269}\r
1270\r
1271\r
1272M68KMAKE_OP(adda, 32, ., .)\r
1273{\r
1274 uint* r_dst = &AX;\r
3335750a 1275 uint src = M68KMAKE_GET_OPER_AY_32; // notaz\r
cc68a136 1276\r
3335750a 1277 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);\r
cc68a136 1278}\r
1279\r
1280\r
1281M68KMAKE_OP(addi, 8, ., d)\r
1282{\r
1283 uint* r_dst = &DY;\r
1284 uint src = OPER_I_8();\r
1285 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1286 uint res = src + dst;\r
1287\r
1288 FLAG_N = NFLAG_8(res);\r
1289 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1290 FLAG_X = FLAG_C = CFLAG_8(res);\r
1291 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1292\r
1293 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1294}\r
1295\r
1296\r
1297M68KMAKE_OP(addi, 8, ., .)\r
1298{\r
1299 uint src = OPER_I_8();\r
1300 uint ea = M68KMAKE_GET_EA_AY_8;\r
1301 uint dst = m68ki_read_8(ea);\r
1302 uint res = src + dst;\r
1303\r
1304 FLAG_N = NFLAG_8(res);\r
1305 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1306 FLAG_X = FLAG_C = CFLAG_8(res);\r
1307 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1308\r
1309 m68ki_write_8(ea, FLAG_Z);\r
1310}\r
1311\r
1312\r
1313M68KMAKE_OP(addi, 16, ., d)\r
1314{\r
1315 uint* r_dst = &DY;\r
1316 uint src = OPER_I_16();\r
1317 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1318 uint res = src + dst;\r
1319\r
1320 FLAG_N = NFLAG_16(res);\r
1321 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1322 FLAG_X = FLAG_C = CFLAG_16(res);\r
1323 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1324\r
1325 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1326}\r
1327\r
1328\r
1329M68KMAKE_OP(addi, 16, ., .)\r
1330{\r
1331 uint src = OPER_I_16();\r
1332 uint ea = M68KMAKE_GET_EA_AY_16;\r
1333 uint dst = m68ki_read_16(ea);\r
1334 uint res = src + dst;\r
1335\r
1336 FLAG_N = NFLAG_16(res);\r
1337 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1338 FLAG_X = FLAG_C = CFLAG_16(res);\r
1339 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1340\r
1341 m68ki_write_16(ea, FLAG_Z);\r
1342}\r
1343\r
1344\r
1345M68KMAKE_OP(addi, 32, ., d)\r
1346{\r
1347 uint* r_dst = &DY;\r
1348 uint src = OPER_I_32();\r
1349 uint dst = *r_dst;\r
1350 uint res = src + dst;\r
1351\r
1352 FLAG_N = NFLAG_32(res);\r
1353 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1354 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1355 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1356\r
1357 *r_dst = FLAG_Z;\r
1358}\r
1359\r
1360\r
1361M68KMAKE_OP(addi, 32, ., .)\r
1362{\r
1363 uint src = OPER_I_32();\r
1364 uint ea = M68KMAKE_GET_EA_AY_32;\r
1365 uint dst = m68ki_read_32(ea);\r
1366 uint res = src + dst;\r
1367\r
1368 FLAG_N = NFLAG_32(res);\r
1369 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1370 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1371 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1372\r
1373 m68ki_write_32(ea, FLAG_Z);\r
1374}\r
1375\r
1376\r
1377M68KMAKE_OP(addq, 8, ., d)\r
1378{\r
1379 uint* r_dst = &DY;\r
1380 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1381 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1382 uint res = src + dst;\r
1383\r
1384 FLAG_N = NFLAG_8(res);\r
1385 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1386 FLAG_X = FLAG_C = CFLAG_8(res);\r
1387 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1388\r
1389 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1390}\r
1391\r
1392\r
1393M68KMAKE_OP(addq, 8, ., .)\r
1394{\r
1395 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1396 uint ea = M68KMAKE_GET_EA_AY_8;\r
1397 uint dst = m68ki_read_8(ea);\r
1398 uint res = src + dst;\r
1399\r
1400 FLAG_N = NFLAG_8(res);\r
1401 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1402 FLAG_X = FLAG_C = CFLAG_8(res);\r
1403 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1404\r
1405 m68ki_write_8(ea, FLAG_Z);\r
1406}\r
1407\r
1408\r
1409M68KMAKE_OP(addq, 16, ., d)\r
1410{\r
1411 uint* r_dst = &DY;\r
1412 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1413 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1414 uint res = src + dst;\r
1415\r
1416 FLAG_N = NFLAG_16(res);\r
1417 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1418 FLAG_X = FLAG_C = CFLAG_16(res);\r
1419 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1420\r
1421 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1422}\r
1423\r
1424\r
1425M68KMAKE_OP(addq, 16, ., a)\r
1426{\r
1427 uint* r_dst = &AY;\r
1428\r
1429 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1430}\r
1431\r
1432\r
1433M68KMAKE_OP(addq, 16, ., .)\r
1434{\r
1435 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1436 uint ea = M68KMAKE_GET_EA_AY_16;\r
1437 uint dst = m68ki_read_16(ea);\r
1438 uint res = src + dst;\r
1439\r
1440 FLAG_N = NFLAG_16(res);\r
1441 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1442 FLAG_X = FLAG_C = CFLAG_16(res);\r
1443 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1444\r
1445 m68ki_write_16(ea, FLAG_Z);\r
1446}\r
1447\r
1448\r
1449M68KMAKE_OP(addq, 32, ., d)\r
1450{\r
1451 uint* r_dst = &DY;\r
1452 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1453 uint dst = *r_dst;\r
1454 uint res = src + dst;\r
1455\r
1456 FLAG_N = NFLAG_32(res);\r
1457 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1458 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1459 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1460\r
1461 *r_dst = FLAG_Z;\r
1462}\r
1463\r
1464\r
1465M68KMAKE_OP(addq, 32, ., a)\r
1466{\r
1467 uint* r_dst = &AY;\r
1468\r
1469 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1470}\r
1471\r
1472\r
1473M68KMAKE_OP(addq, 32, ., .)\r
1474{\r
1475 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1476 uint ea = M68KMAKE_GET_EA_AY_32;\r
1477 uint dst = m68ki_read_32(ea);\r
1478 uint res = src + dst;\r
1479\r
1480\r
1481 FLAG_N = NFLAG_32(res);\r
1482 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1483 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1484 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1485\r
1486 m68ki_write_32(ea, FLAG_Z);\r
1487}\r
1488\r
1489\r
1490M68KMAKE_OP(addx, 8, rr, .)\r
1491{\r
1492 uint* r_dst = &DX;\r
1493 uint src = MASK_OUT_ABOVE_8(DY);\r
1494 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1495 uint res = src + dst + XFLAG_AS_1();\r
1496\r
1497 FLAG_N = NFLAG_8(res);\r
1498 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1499 FLAG_X = FLAG_C = CFLAG_8(res);\r
1500\r
1501 res = MASK_OUT_ABOVE_8(res);\r
1502 FLAG_Z |= res;\r
1503\r
1504 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1505}\r
1506\r
1507\r
1508M68KMAKE_OP(addx, 16, rr, .)\r
1509{\r
1510 uint* r_dst = &DX;\r
1511 uint src = MASK_OUT_ABOVE_16(DY);\r
1512 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1513 uint res = src + dst + XFLAG_AS_1();\r
1514\r
1515 FLAG_N = NFLAG_16(res);\r
1516 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1517 FLAG_X = FLAG_C = CFLAG_16(res);\r
1518\r
1519 res = MASK_OUT_ABOVE_16(res);\r
1520 FLAG_Z |= res;\r
1521\r
1522 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1523}\r
1524\r
1525\r
1526M68KMAKE_OP(addx, 32, rr, .)\r
1527{\r
1528 uint* r_dst = &DX;\r
1529 uint src = DY;\r
1530 uint dst = *r_dst;\r
1531 uint res = src + dst + XFLAG_AS_1();\r
1532\r
1533 FLAG_N = NFLAG_32(res);\r
1534 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1535 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1536\r
1537 res = MASK_OUT_ABOVE_32(res);\r
1538 FLAG_Z |= res;\r
1539\r
1540 *r_dst = res;\r
1541}\r
1542\r
1543\r
1544M68KMAKE_OP(addx, 8, mm, ax7)\r
1545{\r
1546 uint src = OPER_AY_PD_8();\r
1547 uint ea = EA_A7_PD_8();\r
1548 uint dst = m68ki_read_8(ea);\r
1549 uint res = src + dst + XFLAG_AS_1();\r
1550\r
1551 FLAG_N = NFLAG_8(res);\r
1552 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1553 FLAG_X = FLAG_C = CFLAG_8(res);\r
1554\r
1555 res = MASK_OUT_ABOVE_8(res);\r
1556 FLAG_Z |= res;\r
1557\r
1558 m68ki_write_8(ea, res);\r
1559}\r
1560\r
1561\r
1562M68KMAKE_OP(addx, 8, mm, ay7)\r
1563{\r
1564 uint src = OPER_A7_PD_8();\r
1565 uint ea = EA_AX_PD_8();\r
1566 uint dst = m68ki_read_8(ea);\r
1567 uint res = src + dst + XFLAG_AS_1();\r
1568\r
1569 FLAG_N = NFLAG_8(res);\r
1570 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1571 FLAG_X = FLAG_C = CFLAG_8(res);\r
1572\r
1573 res = MASK_OUT_ABOVE_8(res);\r
1574 FLAG_Z |= res;\r
1575\r
1576 m68ki_write_8(ea, res);\r
1577}\r
1578\r
1579\r
1580M68KMAKE_OP(addx, 8, mm, axy7)\r
1581{\r
1582 uint src = OPER_A7_PD_8();\r
1583 uint ea = EA_A7_PD_8();\r
1584 uint dst = m68ki_read_8(ea);\r
1585 uint res = src + dst + XFLAG_AS_1();\r
1586\r
1587 FLAG_N = NFLAG_8(res);\r
1588 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1589 FLAG_X = FLAG_C = CFLAG_8(res);\r
1590\r
1591 res = MASK_OUT_ABOVE_8(res);\r
1592 FLAG_Z |= res;\r
1593\r
1594 m68ki_write_8(ea, res);\r
1595}\r
1596\r
1597\r
1598M68KMAKE_OP(addx, 8, mm, .)\r
1599{\r
1600 uint src = OPER_AY_PD_8();\r
1601 uint ea = EA_AX_PD_8();\r
1602 uint dst = m68ki_read_8(ea);\r
1603 uint res = src + dst + XFLAG_AS_1();\r
1604\r
1605 FLAG_N = NFLAG_8(res);\r
1606 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1607 FLAG_X = FLAG_C = CFLAG_8(res);\r
1608\r
1609 res = MASK_OUT_ABOVE_8(res);\r
1610 FLAG_Z |= res;\r
1611\r
1612 m68ki_write_8(ea, res);\r
1613}\r
1614\r
1615\r
1616M68KMAKE_OP(addx, 16, mm, .)\r
1617{\r
1618 uint src = OPER_AY_PD_16();\r
1619 uint ea = EA_AX_PD_16();\r
1620 uint dst = m68ki_read_16(ea);\r
1621 uint res = src + dst + XFLAG_AS_1();\r
1622\r
1623 FLAG_N = NFLAG_16(res);\r
1624 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1625 FLAG_X = FLAG_C = CFLAG_16(res);\r
1626\r
1627 res = MASK_OUT_ABOVE_16(res);\r
1628 FLAG_Z |= res;\r
1629\r
1630 m68ki_write_16(ea, res);\r
1631}\r
1632\r
1633\r
1634M68KMAKE_OP(addx, 32, mm, .)\r
1635{\r
1636 uint src = OPER_AY_PD_32();\r
1637 uint ea = EA_AX_PD_32();\r
1638 uint dst = m68ki_read_32(ea);\r
1639 uint res = src + dst + XFLAG_AS_1();\r
1640\r
1641 FLAG_N = NFLAG_32(res);\r
1642 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1643 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1644\r
1645 res = MASK_OUT_ABOVE_32(res);\r
1646 FLAG_Z |= res;\r
1647\r
1648 m68ki_write_32(ea, res);\r
1649}\r
1650\r
1651\r
1652M68KMAKE_OP(and, 8, er, d)\r
1653{\r
1654 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));\r
1655\r
1656 FLAG_N = NFLAG_8(FLAG_Z);\r
1657 FLAG_C = CFLAG_CLEAR;\r
1658 FLAG_V = VFLAG_CLEAR;\r
1659}\r
1660\r
1661\r
1662M68KMAKE_OP(and, 8, er, .)\r
1663{\r
1664 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));\r
1665\r
1666 FLAG_N = NFLAG_8(FLAG_Z);\r
1667 FLAG_C = CFLAG_CLEAR;\r
1668 FLAG_V = VFLAG_CLEAR;\r
1669}\r
1670\r
1671\r
1672M68KMAKE_OP(and, 16, er, d)\r
1673{\r
1674 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));\r
1675\r
1676 FLAG_N = NFLAG_16(FLAG_Z);\r
1677 FLAG_C = CFLAG_CLEAR;\r
1678 FLAG_V = VFLAG_CLEAR;\r
1679}\r
1680\r
1681\r
1682M68KMAKE_OP(and, 16, er, .)\r
1683{\r
1684 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));\r
1685\r
1686 FLAG_N = NFLAG_16(FLAG_Z);\r
1687 FLAG_C = CFLAG_CLEAR;\r
1688 FLAG_V = VFLAG_CLEAR;\r
1689}\r
1690\r
1691\r
1692M68KMAKE_OP(and, 32, er, d)\r
1693{\r
1694 FLAG_Z = DX &= DY;\r
1695\r
1696 FLAG_N = NFLAG_32(FLAG_Z);\r
1697 FLAG_C = CFLAG_CLEAR;\r
1698 FLAG_V = VFLAG_CLEAR;\r
1699}\r
1700\r
1701\r
1702M68KMAKE_OP(and, 32, er, .)\r
1703{\r
1704 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;\r
1705\r
1706 FLAG_N = NFLAG_32(FLAG_Z);\r
1707 FLAG_C = CFLAG_CLEAR;\r
1708 FLAG_V = VFLAG_CLEAR;\r
1709}\r
1710\r
1711\r
1712M68KMAKE_OP(and, 8, re, .)\r
1713{\r
1714 uint ea = M68KMAKE_GET_EA_AY_8;\r
1715 uint res = DX & m68ki_read_8(ea);\r
1716\r
1717 FLAG_N = NFLAG_8(res);\r
1718 FLAG_C = CFLAG_CLEAR;\r
1719 FLAG_V = VFLAG_CLEAR;\r
1720 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1721\r
1722 m68ki_write_8(ea, FLAG_Z);\r
1723}\r
1724\r
1725\r
1726M68KMAKE_OP(and, 16, re, .)\r
1727{\r
1728 uint ea = M68KMAKE_GET_EA_AY_16;\r
1729 uint res = DX & m68ki_read_16(ea);\r
1730\r
1731 FLAG_N = NFLAG_16(res);\r
1732 FLAG_C = CFLAG_CLEAR;\r
1733 FLAG_V = VFLAG_CLEAR;\r
1734 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1735\r
1736 m68ki_write_16(ea, FLAG_Z);\r
1737}\r
1738\r
1739\r
1740M68KMAKE_OP(and, 32, re, .)\r
1741{\r
1742 uint ea = M68KMAKE_GET_EA_AY_32;\r
1743 uint res = DX & m68ki_read_32(ea);\r
1744\r
1745 FLAG_N = NFLAG_32(res);\r
1746 FLAG_Z = res;\r
1747 FLAG_C = CFLAG_CLEAR;\r
1748 FLAG_V = VFLAG_CLEAR;\r
1749\r
1750 m68ki_write_32(ea, res);\r
1751}\r
1752\r
1753\r
1754M68KMAKE_OP(andi, 8, ., d)\r
1755{\r
1756 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));\r
1757\r
1758 FLAG_N = NFLAG_8(FLAG_Z);\r
1759 FLAG_C = CFLAG_CLEAR;\r
1760 FLAG_V = VFLAG_CLEAR;\r
1761}\r
1762\r
1763\r
1764M68KMAKE_OP(andi, 8, ., .)\r
1765{\r
1766 uint src = OPER_I_8();\r
1767 uint ea = M68KMAKE_GET_EA_AY_8;\r
1768 uint res = src & m68ki_read_8(ea);\r
1769\r
1770 FLAG_N = NFLAG_8(res);\r
1771 FLAG_Z = res;\r
1772 FLAG_C = CFLAG_CLEAR;\r
1773 FLAG_V = VFLAG_CLEAR;\r
1774\r
1775 m68ki_write_8(ea, res);\r
1776}\r
1777\r
1778\r
1779M68KMAKE_OP(andi, 16, ., d)\r
1780{\r
1781 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));\r
1782\r
1783 FLAG_N = NFLAG_16(FLAG_Z);\r
1784 FLAG_C = CFLAG_CLEAR;\r
1785 FLAG_V = VFLAG_CLEAR;\r
1786}\r
1787\r
1788\r
1789M68KMAKE_OP(andi, 16, ., .)\r
1790{\r
1791 uint src = OPER_I_16();\r
1792 uint ea = M68KMAKE_GET_EA_AY_16;\r
1793 uint res = src & m68ki_read_16(ea);\r
1794\r
1795 FLAG_N = NFLAG_16(res);\r
1796 FLAG_Z = res;\r
1797 FLAG_C = CFLAG_CLEAR;\r
1798 FLAG_V = VFLAG_CLEAR;\r
1799\r
1800 m68ki_write_16(ea, res);\r
1801}\r
1802\r
1803\r
1804M68KMAKE_OP(andi, 32, ., d)\r
1805{\r
1806 FLAG_Z = DY &= (OPER_I_32());\r
1807\r
1808 FLAG_N = NFLAG_32(FLAG_Z);\r
1809 FLAG_C = CFLAG_CLEAR;\r
1810 FLAG_V = VFLAG_CLEAR;\r
1811}\r
1812\r
1813\r
1814M68KMAKE_OP(andi, 32, ., .)\r
1815{\r
1816 uint src = OPER_I_32();\r
1817 uint ea = M68KMAKE_GET_EA_AY_32;\r
1818 uint res = src & m68ki_read_32(ea);\r
1819\r
1820 FLAG_N = NFLAG_32(res);\r
1821 FLAG_Z = res;\r
1822 FLAG_C = CFLAG_CLEAR;\r
1823 FLAG_V = VFLAG_CLEAR;\r
1824\r
1825 m68ki_write_32(ea, res);\r
1826}\r
1827\r
1828\r
1829M68KMAKE_OP(andi, 16, toc, .)\r
1830{\r
1831 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());\r
1832}\r
1833\r
1834\r
1835M68KMAKE_OP(andi, 16, tos, .)\r
1836{\r
1837 if(FLAG_S)\r
1838 {\r
1839 uint src = OPER_I_16();\r
1840 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
1841 m68ki_set_sr(m68ki_get_sr() & src);\r
1842 return;\r
1843 }\r
1844 m68ki_exception_privilege_violation();\r
1845}\r
1846\r
1847\r
1848M68KMAKE_OP(asr, 8, s, .)\r
1849{\r
1850 uint* r_dst = &DY;\r
1851 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1852 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1853 uint res = src >> shift;\r
1854\r
1855 if(shift != 0)\r
1856 USE_CYCLES(shift<<CYC_SHIFT);\r
1857\r
1858 if(GET_MSB_8(src))\r
1859 res |= m68ki_shift_8_table[shift];\r
1860\r
1861 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1862\r
1863 FLAG_N = NFLAG_8(res);\r
1864 FLAG_Z = res;\r
1865 FLAG_V = VFLAG_CLEAR;\r
1866 FLAG_X = FLAG_C = src << (9-shift);\r
1867}\r
1868\r
1869\r
1870M68KMAKE_OP(asr, 16, s, .)\r
1871{\r
1872 uint* r_dst = &DY;\r
1873 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1874 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1875 uint res = src >> shift;\r
1876\r
1877 if(shift != 0)\r
1878 USE_CYCLES(shift<<CYC_SHIFT);\r
1879\r
1880 if(GET_MSB_16(src))\r
1881 res |= m68ki_shift_16_table[shift];\r
1882\r
1883 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1884\r
1885 FLAG_N = NFLAG_16(res);\r
1886 FLAG_Z = res;\r
1887 FLAG_V = VFLAG_CLEAR;\r
1888 FLAG_X = FLAG_C = src << (9-shift);\r
1889}\r
1890\r
1891\r
1892M68KMAKE_OP(asr, 32, s, .)\r
1893{\r
1894 uint* r_dst = &DY;\r
1895 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1896 uint src = *r_dst;\r
1897 uint res = src >> shift;\r
1898\r
1899 if(shift != 0)\r
1900 USE_CYCLES(shift<<CYC_SHIFT);\r
1901\r
1902 if(GET_MSB_32(src))\r
1903 res |= m68ki_shift_32_table[shift];\r
1904\r
1905 *r_dst = res;\r
1906\r
1907 FLAG_N = NFLAG_32(res);\r
1908 FLAG_Z = res;\r
1909 FLAG_V = VFLAG_CLEAR;\r
1910 FLAG_X = FLAG_C = src << (9-shift);\r
1911}\r
1912\r
1913\r
1914M68KMAKE_OP(asr, 8, r, .)\r
1915{\r
1916 uint* r_dst = &DY;\r
1917 uint shift = DX & 0x3f;\r
1918 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1919 uint res = src >> shift;\r
1920\r
1921 if(shift != 0)\r
1922 {\r
1923 USE_CYCLES(shift<<CYC_SHIFT);\r
1924\r
1925 if(shift < 8)\r
1926 {\r
1927 if(GET_MSB_8(src))\r
1928 res |= m68ki_shift_8_table[shift];\r
1929\r
1930 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1931\r
1932 FLAG_X = FLAG_C = src << (9-shift);\r
1933 FLAG_N = NFLAG_8(res);\r
1934 FLAG_Z = res;\r
1935 FLAG_V = VFLAG_CLEAR;\r
1936 return;\r
1937 }\r
1938\r
1939 if(GET_MSB_8(src))\r
1940 {\r
1941 *r_dst |= 0xff;\r
1942 FLAG_C = CFLAG_SET;\r
1943 FLAG_X = XFLAG_SET;\r
1944 FLAG_N = NFLAG_SET;\r
1945 FLAG_Z = ZFLAG_CLEAR;\r
1946 FLAG_V = VFLAG_CLEAR;\r
1947 return;\r
1948 }\r
1949\r
1950 *r_dst &= 0xffffff00;\r
1951 FLAG_C = CFLAG_CLEAR;\r
1952 FLAG_X = XFLAG_CLEAR;\r
1953 FLAG_N = NFLAG_CLEAR;\r
1954 FLAG_Z = ZFLAG_SET;\r
1955 FLAG_V = VFLAG_CLEAR;\r
1956 return;\r
1957 }\r
1958\r
1959 FLAG_C = CFLAG_CLEAR;\r
1960 FLAG_N = NFLAG_8(src);\r
1961 FLAG_Z = src;\r
1962 FLAG_V = VFLAG_CLEAR;\r
1963}\r
1964\r
1965\r
1966M68KMAKE_OP(asr, 16, r, .)\r
1967{\r
1968 uint* r_dst = &DY;\r
1969 uint shift = DX & 0x3f;\r
1970 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1971 uint res = src >> shift;\r
1972\r
1973 if(shift != 0)\r
1974 {\r
1975 USE_CYCLES(shift<<CYC_SHIFT);\r
1976\r
1977 if(shift < 16)\r
1978 {\r
1979 if(GET_MSB_16(src))\r
1980 res |= m68ki_shift_16_table[shift];\r
1981\r
1982 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1983\r
1984 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
1985 FLAG_N = NFLAG_16(res);\r
1986 FLAG_Z = res;\r
1987 FLAG_V = VFLAG_CLEAR;\r
1988 return;\r
1989 }\r
1990\r
1991 if(GET_MSB_16(src))\r
1992 {\r
1993 *r_dst |= 0xffff;\r
1994 FLAG_C = CFLAG_SET;\r
1995 FLAG_X = XFLAG_SET;\r
1996 FLAG_N = NFLAG_SET;\r
1997 FLAG_Z = ZFLAG_CLEAR;\r
1998 FLAG_V = VFLAG_CLEAR;\r
1999 return;\r
2000 }\r
2001\r
2002 *r_dst &= 0xffff0000;\r
2003 FLAG_C = CFLAG_CLEAR;\r
2004 FLAG_X = XFLAG_CLEAR;\r
2005 FLAG_N = NFLAG_CLEAR;\r
2006 FLAG_Z = ZFLAG_SET;\r
2007 FLAG_V = VFLAG_CLEAR;\r
2008 return;\r
2009 }\r
2010\r
2011 FLAG_C = CFLAG_CLEAR;\r
2012 FLAG_N = NFLAG_16(src);\r
2013 FLAG_Z = src;\r
2014 FLAG_V = VFLAG_CLEAR;\r
2015}\r
2016\r
2017\r
2018M68KMAKE_OP(asr, 32, r, .)\r
2019{\r
2020 uint* r_dst = &DY;\r
2021 uint shift = DX & 0x3f;\r
2022 uint src = *r_dst;\r
2023 uint res = src >> shift;\r
2024\r
2025 if(shift != 0)\r
2026 {\r
2027 USE_CYCLES(shift<<CYC_SHIFT);\r
2028\r
2029 if(shift < 32)\r
2030 {\r
2031 if(GET_MSB_32(src))\r
2032 res |= m68ki_shift_32_table[shift];\r
2033\r
2034 *r_dst = res;\r
2035\r
2036 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
2037 FLAG_N = NFLAG_32(res);\r
2038 FLAG_Z = res;\r
2039 FLAG_V = VFLAG_CLEAR;\r
2040 return;\r
2041 }\r
2042\r
2043 if(GET_MSB_32(src))\r
2044 {\r
2045 *r_dst = 0xffffffff;\r
2046 FLAG_C = CFLAG_SET;\r
2047 FLAG_X = XFLAG_SET;\r
2048 FLAG_N = NFLAG_SET;\r
2049 FLAG_Z = ZFLAG_CLEAR;\r
2050 FLAG_V = VFLAG_CLEAR;\r
2051 return;\r
2052 }\r
2053\r
2054 *r_dst = 0;\r
2055 FLAG_C = CFLAG_CLEAR;\r
2056 FLAG_X = XFLAG_CLEAR;\r
2057 FLAG_N = NFLAG_CLEAR;\r
2058 FLAG_Z = ZFLAG_SET;\r
2059 FLAG_V = VFLAG_CLEAR;\r
2060 return;\r
2061 }\r
2062\r
2063 FLAG_C = CFLAG_CLEAR;\r
2064 FLAG_N = NFLAG_32(src);\r
2065 FLAG_Z = src;\r
2066 FLAG_V = VFLAG_CLEAR;\r
2067}\r
2068\r
2069\r
2070M68KMAKE_OP(asr, 16, ., .)\r
2071{\r
2072 uint ea = M68KMAKE_GET_EA_AY_16;\r
2073 uint src = m68ki_read_16(ea);\r
2074 uint res = src >> 1;\r
2075\r
2076 if(GET_MSB_16(src))\r
2077 res |= 0x8000;\r
2078\r
2079 m68ki_write_16(ea, res);\r
2080\r
2081 FLAG_N = NFLAG_16(res);\r
2082 FLAG_Z = res;\r
2083 FLAG_V = VFLAG_CLEAR;\r
2084 FLAG_C = FLAG_X = src << 8;\r
2085}\r
2086\r
2087\r
2088M68KMAKE_OP(asl, 8, s, .)\r
2089{\r
2090 uint* r_dst = &DY;\r
2091 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2092 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2093 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2094\r
2095 if(shift != 0)\r
2096 USE_CYCLES(shift<<CYC_SHIFT);\r
2097\r
2098 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2099\r
2100 FLAG_X = FLAG_C = src << shift;\r
2101 FLAG_N = NFLAG_8(res);\r
2102 FLAG_Z = res;\r
2103 src &= m68ki_shift_8_table[shift + 1];\r
2104 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;\r
2105}\r
2106\r
2107\r
2108M68KMAKE_OP(asl, 16, s, .)\r
2109{\r
2110 uint* r_dst = &DY;\r
2111 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2112 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2113 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2114\r
2115 if(shift != 0)\r
2116 USE_CYCLES(shift<<CYC_SHIFT);\r
2117\r
2118 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2119\r
2120 FLAG_N = NFLAG_16(res);\r
2121 FLAG_Z = res;\r
2122 FLAG_X = FLAG_C = src >> (8-shift);\r
2123 src &= m68ki_shift_16_table[shift + 1];\r
2124 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2125}\r
2126\r
2127\r
2128M68KMAKE_OP(asl, 32, s, .)\r
2129{\r
2130 uint* r_dst = &DY;\r
2131 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2132 uint src = *r_dst;\r
2133 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2134\r
2135 if(shift != 0)\r
2136 USE_CYCLES(shift<<CYC_SHIFT);\r
2137\r
2138 *r_dst = res;\r
2139\r
2140 FLAG_N = NFLAG_32(res);\r
2141 FLAG_Z = res;\r
2142 FLAG_X = FLAG_C = src >> (24-shift);\r
2143 src &= m68ki_shift_32_table[shift + 1];\r
2144 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2145}\r
2146\r
2147\r
2148M68KMAKE_OP(asl, 8, r, .)\r
2149{\r
2150 uint* r_dst = &DY;\r
2151 uint shift = DX & 0x3f;\r
2152 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2153 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2154\r
2155 if(shift != 0)\r
2156 {\r
2157 USE_CYCLES(shift<<CYC_SHIFT);\r
2158\r
2159 if(shift < 8)\r
2160 {\r
2161 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2162 FLAG_X = FLAG_C = src << shift;\r
2163 FLAG_N = NFLAG_8(res);\r
2164 FLAG_Z = res;\r
2165 src &= m68ki_shift_8_table[shift + 1];\r
2166 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;\r
2167 return;\r
2168 }\r
2169\r
2170 *r_dst &= 0xffffff00;\r
2171 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;\r
2172 FLAG_N = NFLAG_CLEAR;\r
2173 FLAG_Z = ZFLAG_SET;\r
2174 FLAG_V = (!(src == 0))<<7;\r
2175 return;\r
2176 }\r
2177\r
2178 FLAG_C = CFLAG_CLEAR;\r
2179 FLAG_N = NFLAG_8(src);\r
2180 FLAG_Z = src;\r
2181 FLAG_V = VFLAG_CLEAR;\r
2182}\r
2183\r
2184\r
2185M68KMAKE_OP(asl, 16, r, .)\r
2186{\r
2187 uint* r_dst = &DY;\r
2188 uint shift = DX & 0x3f;\r
2189 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2190 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2191\r
2192 if(shift != 0)\r
2193 {\r
2194 USE_CYCLES(shift<<CYC_SHIFT);\r
2195\r
2196 if(shift < 16)\r
2197 {\r
2198 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2199 FLAG_X = FLAG_C = (src << shift) >> 8;\r
2200 FLAG_N = NFLAG_16(res);\r
2201 FLAG_Z = res;\r
2202 src &= m68ki_shift_16_table[shift + 1];\r
2203 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2204 return;\r
2205 }\r
2206\r
2207 *r_dst &= 0xffff0000;\r
2208 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;\r
2209 FLAG_N = NFLAG_CLEAR;\r
2210 FLAG_Z = ZFLAG_SET;\r
2211 FLAG_V = (!(src == 0))<<7;\r
2212 return;\r
2213 }\r
2214\r
2215 FLAG_C = CFLAG_CLEAR;\r
2216 FLAG_N = NFLAG_16(src);\r
2217 FLAG_Z = src;\r
2218 FLAG_V = VFLAG_CLEAR;\r
2219}\r
2220\r
2221\r
2222M68KMAKE_OP(asl, 32, r, .)\r
2223{\r
2224 uint* r_dst = &DY;\r
2225 uint shift = DX & 0x3f;\r
2226 uint src = *r_dst;\r
2227 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2228\r
2229 if(shift != 0)\r
2230 {\r
2231 USE_CYCLES(shift<<CYC_SHIFT);\r
2232\r
2233 if(shift < 32)\r
2234 {\r
2235 *r_dst = res;\r
2236 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
2237 FLAG_N = NFLAG_32(res);\r
2238 FLAG_Z = res;\r
2239 src &= m68ki_shift_32_table[shift + 1];\r
2240 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2241 return;\r
2242 }\r
2243\r
2244 *r_dst = 0;\r
2245 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
2246 FLAG_N = NFLAG_CLEAR;\r
2247 FLAG_Z = ZFLAG_SET;\r
2248 FLAG_V = (!(src == 0))<<7;\r
2249 return;\r
2250 }\r
2251\r
2252 FLAG_C = CFLAG_CLEAR;\r
2253 FLAG_N = NFLAG_32(src);\r
2254 FLAG_Z = src;\r
2255 FLAG_V = VFLAG_CLEAR;\r
2256}\r
2257\r
2258\r
2259M68KMAKE_OP(asl, 16, ., .)\r
2260{\r
2261 uint ea = M68KMAKE_GET_EA_AY_16;\r
2262 uint src = m68ki_read_16(ea);\r
2263 uint res = MASK_OUT_ABOVE_16(src << 1);\r
2264\r
2265 m68ki_write_16(ea, res);\r
2266\r
2267 FLAG_N = NFLAG_16(res);\r
2268 FLAG_Z = res;\r
2269 FLAG_X = FLAG_C = src >> 7;\r
2270 src &= 0xc000;\r
2271 FLAG_V = (!(src == 0 || src == 0xc000))<<7;\r
2272}\r
2273\r
2274\r
2275M68KMAKE_OP(bcc, 8, ., .)\r
2276{\r
2277 if(M68KMAKE_CC)\r
2278 {\r
2279 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2280 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2281 return;\r
2282 }\r
2283 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2284}\r
2285\r
2286\r
2287M68KMAKE_OP(bcc, 16, ., .)\r
2288{\r
2289 if(M68KMAKE_CC)\r
2290 {\r
2291 uint offset = OPER_I_16();\r
2292 REG_PC -= 2;\r
2293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2294 m68ki_branch_16(offset);\r
2295 return;\r
2296 }\r
2297 REG_PC += 2;\r
2298 USE_CYCLES(CYC_BCC_NOTAKE_W);\r
2299}\r
2300\r
2301\r
2302M68KMAKE_OP(bcc, 32, ., .)\r
2303{\r
2304 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2305 {\r
2306 if(M68KMAKE_CC)\r
2307 {\r
2308 uint offset = OPER_I_32();\r
2309 REG_PC -= 4;\r
2310 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2311 m68ki_branch_32(offset);\r
2312 return;\r
2313 }\r
2314 REG_PC += 4;\r
2315 return;\r
2316 }\r
2317 else\r
2318 {\r
2319 if(M68KMAKE_CC)\r
2320 {\r
2321 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2322 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2323 return;\r
2324 }\r
2325 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2326 }\r
2327}\r
2328\r
2329\r
2330M68KMAKE_OP(bchg, 32, r, d)\r
2331{\r
2332 uint* r_dst = &DY;\r
2333 uint mask = 1 << (DX & 0x1f);\r
2334\r
2335 FLAG_Z = *r_dst & mask;\r
2336 *r_dst ^= mask;\r
2337}\r
2338\r
2339\r
2340M68KMAKE_OP(bchg, 8, r, .)\r
2341{\r
2342 uint ea = M68KMAKE_GET_EA_AY_8;\r
2343 uint src = m68ki_read_8(ea);\r
2344 uint mask = 1 << (DX & 7);\r
2345\r
2346 FLAG_Z = src & mask;\r
2347 m68ki_write_8(ea, src ^ mask);\r
2348}\r
2349\r
2350\r
2351M68KMAKE_OP(bchg, 32, s, d)\r
2352{\r
2353 uint* r_dst = &DY;\r
2354 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2355\r
2356 FLAG_Z = *r_dst & mask;\r
2357 *r_dst ^= mask;\r
2358}\r
2359\r
2360\r
2361M68KMAKE_OP(bchg, 8, s, .)\r
2362{\r
2363 uint mask = 1 << (OPER_I_8() & 7);\r
2364 uint ea = M68KMAKE_GET_EA_AY_8;\r
2365 uint src = m68ki_read_8(ea);\r
2366\r
2367 FLAG_Z = src & mask;\r
2368 m68ki_write_8(ea, src ^ mask);\r
2369}\r
2370\r
2371\r
2372M68KMAKE_OP(bclr, 32, r, d)\r
2373{\r
2374 uint* r_dst = &DY;\r
2375 uint mask = 1 << (DX & 0x1f);\r
2376\r
2377 FLAG_Z = *r_dst & mask;\r
2378 *r_dst &= ~mask;\r
2379}\r
2380\r
2381\r
2382M68KMAKE_OP(bclr, 8, r, .)\r
2383{\r
2384 uint ea = M68KMAKE_GET_EA_AY_8;\r
2385 uint src = m68ki_read_8(ea);\r
2386 uint mask = 1 << (DX & 7);\r
2387\r
2388 FLAG_Z = src & mask;\r
2389 m68ki_write_8(ea, src & ~mask);\r
2390}\r
2391\r
2392\r
2393M68KMAKE_OP(bclr, 32, s, d)\r
2394{\r
2395 uint* r_dst = &DY;\r
2396 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2397\r
2398 FLAG_Z = *r_dst & mask;\r
2399 *r_dst &= ~mask;\r
2400}\r
2401\r
2402\r
2403M68KMAKE_OP(bclr, 8, s, .)\r
2404{\r
2405 uint mask = 1 << (OPER_I_8() & 7);\r
2406 uint ea = M68KMAKE_GET_EA_AY_8;\r
2407 uint src = m68ki_read_8(ea);\r
2408\r
2409 FLAG_Z = src & mask;\r
2410 m68ki_write_8(ea, src & ~mask);\r
2411}\r
2412\r
2413\r
2414M68KMAKE_OP(bfchg, 32, ., d)\r
2415{\r
2416 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2417 {\r
2418 uint word2 = OPER_I_16();\r
2419 uint offset = (word2>>6)&31;\r
2420 uint width = word2;\r
2421 uint* data = &DY;\r
2422 uint64 mask;\r
2423\r
2424\r
2425 if(BIT_B(word2))\r
2426 offset = REG_D[offset&7];\r
2427 if(BIT_5(word2))\r
2428 width = REG_D[width&7];\r
2429\r
2430 offset &= 31;\r
2431 width = ((width-1) & 31) + 1;\r
2432\r
2433 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2434 mask = ROR_32(mask, offset);\r
2435\r
2436 FLAG_N = NFLAG_32(*data<<offset);\r
2437 FLAG_Z = *data & mask;\r
2438 FLAG_V = VFLAG_CLEAR;\r
2439 FLAG_C = CFLAG_CLEAR;\r
2440\r
2441 *data ^= mask;\r
2442\r
2443 return;\r
2444 }\r
2445 m68ki_exception_illegal();\r
2446}\r
2447\r
2448\r
2449M68KMAKE_OP(bfchg, 32, ., .)\r
2450{\r
2451 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2452 {\r
2453 uint word2 = OPER_I_16();\r
2454 sint offset = (word2>>6)&31;\r
2455 uint width = word2;\r
2456 uint mask_base;\r
2457 uint data_long;\r
2458 uint mask_long;\r
2459 uint data_byte = 0;\r
2460 uint mask_byte = 0;\r
2461 uint ea = M68KMAKE_GET_EA_AY_8;\r
2462\r
2463\r
2464 if(BIT_B(word2))\r
2465 offset = MAKE_INT_32(REG_D[offset&7]);\r
2466 if(BIT_5(word2))\r
2467 width = REG_D[width&7];\r
2468\r
2469 /* Offset is signed so we have to use ugly math =( */\r
2470 ea += offset / 8;\r
2471 offset %= 8;\r
2472 if(offset < 0)\r
2473 {\r
2474 offset += 8;\r
2475 ea--;\r
2476 }\r
2477 width = ((width-1) & 31) + 1;\r
2478\r
2479 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2480 mask_long = mask_base >> offset;\r
2481\r
2482 data_long = m68ki_read_32(ea);\r
2483 FLAG_N = NFLAG_32(data_long << offset);\r
2484 FLAG_Z = data_long & mask_long;\r
2485 FLAG_V = VFLAG_CLEAR;\r
2486 FLAG_C = CFLAG_CLEAR;\r
2487\r
2488 m68ki_write_32(ea, data_long ^ mask_long);\r
2489\r
2490 if((width + offset) > 32)\r
2491 {\r
2492 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2493 data_byte = m68ki_read_8(ea+4);\r
2494 FLAG_Z |= (data_byte & mask_byte);\r
2495 m68ki_write_8(ea+4, data_byte ^ mask_byte);\r
2496 }\r
2497 return;\r
2498 }\r
2499 m68ki_exception_illegal();\r
2500}\r
2501\r
2502\r
2503M68KMAKE_OP(bfclr, 32, ., d)\r
2504{\r
2505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2506 {\r
2507 uint word2 = OPER_I_16();\r
2508 uint offset = (word2>>6)&31;\r
2509 uint width = word2;\r
2510 uint* data = &DY;\r
2511 uint64 mask;\r
2512\r
2513\r
2514 if(BIT_B(word2))\r
2515 offset = REG_D[offset&7];\r
2516 if(BIT_5(word2))\r
2517 width = REG_D[width&7];\r
2518\r
2519\r
2520 offset &= 31;\r
2521 width = ((width-1) & 31) + 1;\r
2522\r
2523\r
2524 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2525 mask = ROR_32(mask, offset);\r
2526\r
2527 FLAG_N = NFLAG_32(*data<<offset);\r
2528 FLAG_Z = *data & mask;\r
2529 FLAG_V = VFLAG_CLEAR;\r
2530 FLAG_C = CFLAG_CLEAR;\r
2531\r
2532 *data &= ~mask;\r
2533\r
2534 return;\r
2535 }\r
2536 m68ki_exception_illegal();\r
2537}\r
2538\r
2539\r
2540M68KMAKE_OP(bfclr, 32, ., .)\r
2541{\r
2542 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2543 {\r
2544 uint word2 = OPER_I_16();\r
2545 sint offset = (word2>>6)&31;\r
2546 uint width = word2;\r
2547 uint mask_base;\r
2548 uint data_long;\r
2549 uint mask_long;\r
2550 uint data_byte = 0;\r
2551 uint mask_byte = 0;\r
2552 uint ea = M68KMAKE_GET_EA_AY_8;\r
2553\r
2554\r
2555 if(BIT_B(word2))\r
2556 offset = MAKE_INT_32(REG_D[offset&7]);\r
2557 if(BIT_5(word2))\r
2558 width = REG_D[width&7];\r
2559\r
2560 /* Offset is signed so we have to use ugly math =( */\r
2561 ea += offset / 8;\r
2562 offset %= 8;\r
2563 if(offset < 0)\r
2564 {\r
2565 offset += 8;\r
2566 ea--;\r
2567 }\r
2568 width = ((width-1) & 31) + 1;\r
2569\r
2570 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2571 mask_long = mask_base >> offset;\r
2572\r
2573 data_long = m68ki_read_32(ea);\r
2574 FLAG_N = NFLAG_32(data_long << offset);\r
2575 FLAG_Z = data_long & mask_long;\r
2576 FLAG_V = VFLAG_CLEAR;\r
2577 FLAG_C = CFLAG_CLEAR;\r
2578\r
2579 m68ki_write_32(ea, data_long & ~mask_long);\r
2580\r
2581 if((width + offset) > 32)\r
2582 {\r
2583 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2584 data_byte = m68ki_read_8(ea+4);\r
2585 FLAG_Z |= (data_byte & mask_byte);\r
2586 m68ki_write_8(ea+4, data_byte & ~mask_byte);\r
2587 }\r
2588 return;\r
2589 }\r
2590 m68ki_exception_illegal();\r
2591}\r
2592\r
2593\r
2594M68KMAKE_OP(bfexts, 32, ., d)\r
2595{\r
2596 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2597 {\r
2598 uint word2 = OPER_I_16();\r
2599 uint offset = (word2>>6)&31;\r
2600 uint width = word2;\r
2601 uint64 data = DY;\r
2602\r
2603\r
2604 if(BIT_B(word2))\r
2605 offset = REG_D[offset&7];\r
2606 if(BIT_5(word2))\r
2607 width = REG_D[width&7];\r
2608\r
2609 offset &= 31;\r
2610 width = ((width-1) & 31) + 1;\r
2611\r
2612 data = ROL_32(data, offset);\r
2613 FLAG_N = NFLAG_32(data);\r
2614 data = MAKE_INT_32(data) >> (32 - width);\r
2615\r
2616 FLAG_Z = data;\r
2617 FLAG_V = VFLAG_CLEAR;\r
2618 FLAG_C = CFLAG_CLEAR;\r
2619\r
2620 REG_D[(word2>>12)&7] = data;\r
2621\r
2622 return;\r
2623 }\r
2624 m68ki_exception_illegal();\r
2625}\r
2626\r
2627\r
2628M68KMAKE_OP(bfexts, 32, ., .)\r
2629{\r
2630 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2631 {\r
2632 uint word2 = OPER_I_16();\r
2633 sint offset = (word2>>6)&31;\r
2634 uint width = word2;\r
2635 uint data;\r
2636 uint ea = M68KMAKE_GET_EA_AY_8;\r
2637\r
2638\r
2639 if(BIT_B(word2))\r
2640 offset = MAKE_INT_32(REG_D[offset&7]);\r
2641 if(BIT_5(word2))\r
2642 width = REG_D[width&7];\r
2643\r
2644 /* Offset is signed so we have to use ugly math =( */\r
2645 ea += offset / 8;\r
2646 offset %= 8;\r
2647 if(offset < 0)\r
2648 {\r
2649 offset += 8;\r
2650 ea--;\r
2651 }\r
2652 width = ((width-1) & 31) + 1;\r
2653\r
2654 data = m68ki_read_32(ea);\r
2655\r
2656 data = MASK_OUT_ABOVE_32(data<<offset);\r
2657\r
2658 if((offset+width) > 32)\r
2659 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2660\r
2661 FLAG_N = NFLAG_32(data);\r
2662 data = MAKE_INT_32(data) >> (32 - width);\r
2663\r
2664 FLAG_Z = data;\r
2665 FLAG_V = VFLAG_CLEAR;\r
2666 FLAG_C = CFLAG_CLEAR;\r
2667\r
2668 REG_D[(word2 >> 12) & 7] = data;\r
2669\r
2670 return;\r
2671 }\r
2672 m68ki_exception_illegal();\r
2673}\r
2674\r
2675\r
2676M68KMAKE_OP(bfextu, 32, ., d)\r
2677{\r
2678 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2679 {\r
2680 uint word2 = OPER_I_16();\r
2681 uint offset = (word2>>6)&31;\r
2682 uint width = word2;\r
2683 uint64 data = DY;\r
2684\r
2685\r
2686 if(BIT_B(word2))\r
2687 offset = REG_D[offset&7];\r
2688 if(BIT_5(word2))\r
2689 width = REG_D[width&7];\r
2690\r
2691 offset &= 31;\r
2692 width = ((width-1) & 31) + 1;\r
2693\r
2694 data = ROL_32(data, offset);\r
2695 FLAG_N = NFLAG_32(data);\r
2696 data >>= 32 - width;\r
2697\r
2698 FLAG_Z = data;\r
2699 FLAG_V = VFLAG_CLEAR;\r
2700 FLAG_C = CFLAG_CLEAR;\r
2701\r
2702 REG_D[(word2>>12)&7] = data;\r
2703\r
2704 return;\r
2705 }\r
2706 m68ki_exception_illegal();\r
2707}\r
2708\r
2709\r
2710M68KMAKE_OP(bfextu, 32, ., .)\r
2711{\r
2712 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2713 {\r
2714 uint word2 = OPER_I_16();\r
2715 sint offset = (word2>>6)&31;\r
2716 uint width = word2;\r
2717 uint data;\r
2718 uint ea = M68KMAKE_GET_EA_AY_8;\r
2719\r
2720\r
2721 if(BIT_B(word2))\r
2722 offset = MAKE_INT_32(REG_D[offset&7]);\r
2723 if(BIT_5(word2))\r
2724 width = REG_D[width&7];\r
2725\r
2726 /* Offset is signed so we have to use ugly math =( */\r
2727 ea += offset / 8;\r
2728 offset %= 8;\r
2729 if(offset < 0)\r
2730 {\r
2731 offset += 8;\r
2732 ea--;\r
2733 }\r
2734 width = ((width-1) & 31) + 1;\r
2735\r
2736 data = m68ki_read_32(ea);\r
2737 data = MASK_OUT_ABOVE_32(data<<offset);\r
2738\r
2739 if((offset+width) > 32)\r
2740 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2741\r
2742 FLAG_N = NFLAG_32(data);\r
2743 data >>= (32 - width);\r
2744\r
2745 FLAG_Z = data;\r
2746 FLAG_V = VFLAG_CLEAR;\r
2747 FLAG_C = CFLAG_CLEAR;\r
2748\r
2749 REG_D[(word2 >> 12) & 7] = data;\r
2750\r
2751 return;\r
2752 }\r
2753 m68ki_exception_illegal();\r
2754}\r
2755\r
2756\r
2757M68KMAKE_OP(bfffo, 32, ., d)\r
2758{\r
2759 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2760 {\r
2761 uint word2 = OPER_I_16();\r
2762 uint offset = (word2>>6)&31;\r
2763 uint width = word2;\r
2764 uint64 data = DY;\r
2765 uint bit;\r
2766\r
2767\r
2768 if(BIT_B(word2))\r
2769 offset = REG_D[offset&7];\r
2770 if(BIT_5(word2))\r
2771 width = REG_D[width&7];\r
2772\r
2773 offset &= 31;\r
2774 width = ((width-1) & 31) + 1;\r
2775\r
2776 data = ROL_32(data, offset);\r
2777 FLAG_N = NFLAG_32(data);\r
2778 data >>= 32 - width;\r
2779\r
2780 FLAG_Z = data;\r
2781 FLAG_V = VFLAG_CLEAR;\r
2782 FLAG_C = CFLAG_CLEAR;\r
2783\r
2784 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2785 offset++;\r
2786\r
2787 REG_D[(word2>>12)&7] = offset;\r
2788\r
2789 return;\r
2790 }\r
2791 m68ki_exception_illegal();\r
2792}\r
2793\r
2794\r
2795M68KMAKE_OP(bfffo, 32, ., .)\r
2796{\r
2797 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2798 {\r
2799 uint word2 = OPER_I_16();\r
2800 sint offset = (word2>>6)&31;\r
2801 sint local_offset;\r
2802 uint width = word2;\r
2803 uint data;\r
2804 uint bit;\r
2805 uint ea = M68KMAKE_GET_EA_AY_8;\r
2806\r
2807\r
2808 if(BIT_B(word2))\r
2809 offset = MAKE_INT_32(REG_D[offset&7]);\r
2810 if(BIT_5(word2))\r
2811 width = REG_D[width&7];\r
2812\r
2813 /* Offset is signed so we have to use ugly math =( */\r
2814 ea += offset / 8;\r
2815 local_offset = offset % 8;\r
2816 if(local_offset < 0)\r
2817 {\r
2818 local_offset += 8;\r
2819 ea--;\r
2820 }\r
2821 width = ((width-1) & 31) + 1;\r
2822\r
2823 data = m68ki_read_32(ea);\r
2824 data = MASK_OUT_ABOVE_32(data<<local_offset);\r
2825\r
2826 if((local_offset+width) > 32)\r
2827 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;\r
2828\r
2829 FLAG_N = NFLAG_32(data);\r
2830 data >>= (32 - width);\r
2831\r
2832 FLAG_Z = data;\r
2833 FLAG_V = VFLAG_CLEAR;\r
2834 FLAG_C = CFLAG_CLEAR;\r
2835\r
2836 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2837 offset++;\r
2838\r
2839 REG_D[(word2>>12)&7] = offset;\r
2840\r
2841 return;\r
2842 }\r
2843 m68ki_exception_illegal();\r
2844}\r
2845\r
2846\r
2847M68KMAKE_OP(bfins, 32, ., d)\r
2848{\r
2849 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2850 {\r
2851 uint word2 = OPER_I_16();\r
2852 uint offset = (word2>>6)&31;\r
2853 uint width = word2;\r
2854 uint* data = &DY;\r
2855 uint64 mask;\r
2856 uint64 insert = REG_D[(word2>>12)&7];\r
2857\r
2858\r
2859 if(BIT_B(word2))\r
2860 offset = REG_D[offset&7];\r
2861 if(BIT_5(word2))\r
2862 width = REG_D[width&7];\r
2863\r
2864\r
2865 offset &= 31;\r
2866 width = ((width-1) & 31) + 1;\r
2867\r
2868\r
2869 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2870 mask = ROR_32(mask, offset);\r
2871\r
2872 insert = MASK_OUT_ABOVE_32(insert << (32 - width));\r
2873 FLAG_N = NFLAG_32(insert);\r
2874 FLAG_Z = insert;\r
2875 insert = ROR_32(insert, offset);\r
2876\r
2877 FLAG_V = VFLAG_CLEAR;\r
2878 FLAG_C = CFLAG_CLEAR;\r
2879\r
2880 *data &= ~mask;\r
2881 *data |= insert;\r
2882\r
2883 return;\r
2884 }\r
2885 m68ki_exception_illegal();\r
2886}\r
2887\r
2888\r
2889M68KMAKE_OP(bfins, 32, ., .)\r
2890{\r
2891 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2892 {\r
2893 uint word2 = OPER_I_16();\r
2894 sint offset = (word2>>6)&31;\r
2895 uint width = word2;\r
2896 uint insert_base = REG_D[(word2>>12)&7];\r
2897 uint insert_long;\r
2898 uint insert_byte;\r
2899 uint mask_base;\r
2900 uint data_long;\r
2901 uint mask_long;\r
2902 uint data_byte = 0;\r
2903 uint mask_byte = 0;\r
2904 uint ea = M68KMAKE_GET_EA_AY_8;\r
2905\r
2906\r
2907 if(BIT_B(word2))\r
2908 offset = MAKE_INT_32(REG_D[offset&7]);\r
2909 if(BIT_5(word2))\r
2910 width = REG_D[width&7];\r
2911\r
2912 /* Offset is signed so we have to use ugly math =( */\r
2913 ea += offset / 8;\r
2914 offset %= 8;\r
2915 if(offset < 0)\r
2916 {\r
2917 offset += 8;\r
2918 ea--;\r
2919 }\r
2920 width = ((width-1) & 31) + 1;\r
2921\r
2922 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2923 mask_long = mask_base >> offset;\r
2924\r
2925 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));\r
2926 FLAG_N = NFLAG_32(insert_base);\r
2927 FLAG_Z = insert_base;\r
2928 insert_long = insert_base >> offset;\r
2929\r
2930 data_long = m68ki_read_32(ea);\r
2931 FLAG_V = VFLAG_CLEAR;\r
2932 FLAG_C = CFLAG_CLEAR;\r
2933\r
2934 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);\r
2935\r
2936 if((width + offset) > 32)\r
2937 {\r
2938 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2939 insert_byte = MASK_OUT_ABOVE_8(insert_base);\r
2940 data_byte = m68ki_read_8(ea+4);\r
2941 FLAG_Z |= (data_byte & mask_byte);\r
2942 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);\r
2943 }\r
2944 return;\r
2945 }\r
2946 m68ki_exception_illegal();\r
2947}\r
2948\r
2949\r
2950M68KMAKE_OP(bfset, 32, ., d)\r
2951{\r
2952 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2953 {\r
2954 uint word2 = OPER_I_16();\r
2955 uint offset = (word2>>6)&31;\r
2956 uint width = word2;\r
2957 uint* data = &DY;\r
2958 uint64 mask;\r
2959\r
2960\r
2961 if(BIT_B(word2))\r
2962 offset = REG_D[offset&7];\r
2963 if(BIT_5(word2))\r
2964 width = REG_D[width&7];\r
2965\r
2966\r
2967 offset &= 31;\r
2968 width = ((width-1) & 31) + 1;\r
2969\r
2970\r
2971 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2972 mask = ROR_32(mask, offset);\r
2973\r
2974 FLAG_N = NFLAG_32(*data<<offset);\r
2975 FLAG_Z = *data & mask;\r
2976 FLAG_V = VFLAG_CLEAR;\r
2977 FLAG_C = CFLAG_CLEAR;\r
2978\r
2979 *data |= mask;\r
2980\r
2981 return;\r
2982 }\r
2983 m68ki_exception_illegal();\r
2984}\r
2985\r
2986\r
2987M68KMAKE_OP(bfset, 32, ., .)\r
2988{\r
2989 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2990 {\r
2991 uint word2 = OPER_I_16();\r
2992 sint offset = (word2>>6)&31;\r
2993 uint width = word2;\r
2994 uint mask_base;\r
2995 uint data_long;\r
2996 uint mask_long;\r
2997 uint data_byte = 0;\r
2998 uint mask_byte = 0;\r
2999 uint ea = M68KMAKE_GET_EA_AY_8;\r
3000\r
3001\r
3002 if(BIT_B(word2))\r
3003 offset = MAKE_INT_32(REG_D[offset&7]);\r
3004 if(BIT_5(word2))\r
3005 width = REG_D[width&7];\r
3006\r
3007 /* Offset is signed so we have to use ugly math =( */\r
3008 ea += offset / 8;\r
3009 offset %= 8;\r
3010 if(offset < 0)\r
3011 {\r
3012 offset += 8;\r
3013 ea--;\r
3014 }\r
3015 width = ((width-1) & 31) + 1;\r
3016\r
3017\r
3018 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3019 mask_long = mask_base >> offset;\r
3020\r
3021 data_long = m68ki_read_32(ea);\r
3022 FLAG_N = NFLAG_32(data_long << offset);\r
3023 FLAG_Z = data_long & mask_long;\r
3024 FLAG_V = VFLAG_CLEAR;\r
3025 FLAG_C = CFLAG_CLEAR;\r
3026\r
3027 m68ki_write_32(ea, data_long | mask_long);\r
3028\r
3029 if((width + offset) > 32)\r
3030 {\r
3031 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3032 data_byte = m68ki_read_8(ea+4);\r
3033 FLAG_Z |= (data_byte & mask_byte);\r
3034 m68ki_write_8(ea+4, data_byte | mask_byte);\r
3035 }\r
3036 return;\r
3037 }\r
3038 m68ki_exception_illegal();\r
3039}\r
3040\r
3041\r
3042M68KMAKE_OP(bftst, 32, ., d)\r
3043{\r
3044 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3045 {\r
3046 uint word2 = OPER_I_16();\r
3047 uint offset = (word2>>6)&31;\r
3048 uint width = word2;\r
3049 uint* data = &DY;\r
3050 uint64 mask;\r
3051\r
3052\r
3053 if(BIT_B(word2))\r
3054 offset = REG_D[offset&7];\r
3055 if(BIT_5(word2))\r
3056 width = REG_D[width&7];\r
3057\r
3058\r
3059 offset &= 31;\r
3060 width = ((width-1) & 31) + 1;\r
3061\r
3062\r
3063 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3064 mask = ROR_32(mask, offset);\r
3065\r
3066 FLAG_N = NFLAG_32(*data<<offset);\r
3067 FLAG_Z = *data & mask;\r
3068 FLAG_V = VFLAG_CLEAR;\r
3069 FLAG_C = CFLAG_CLEAR;\r
3070\r
3071 return;\r
3072 }\r
3073 m68ki_exception_illegal();\r
3074}\r
3075\r
3076\r
3077M68KMAKE_OP(bftst, 32, ., .)\r
3078{\r
3079 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3080 {\r
3081 uint word2 = OPER_I_16();\r
3082 sint offset = (word2>>6)&31;\r
3083 uint width = word2;\r
3084 uint mask_base;\r
3085 uint data_long;\r
3086 uint mask_long;\r
3087 uint data_byte = 0;\r
3088 uint mask_byte = 0;\r
3089 uint ea = M68KMAKE_GET_EA_AY_8;\r
3090\r
3091 if(BIT_B(word2))\r
3092 offset = MAKE_INT_32(REG_D[offset&7]);\r
3093 if(BIT_5(word2))\r
3094 width = REG_D[width&7];\r
3095\r
3096 /* Offset is signed so we have to use ugly math =( */\r
3097 ea += offset / 8;\r
3098 offset %= 8;\r
3099 if(offset < 0)\r
3100 {\r
3101 offset += 8;\r
3102 ea--;\r
3103 }\r
3104 width = ((width-1) & 31) + 1;\r
3105\r
3106\r
3107 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3108 mask_long = mask_base >> offset;\r
3109\r
3110 data_long = m68ki_read_32(ea);\r
3111 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;\r
3112 FLAG_Z = data_long & mask_long;\r
3113 FLAG_V = VFLAG_CLEAR;\r
3114 FLAG_C = CFLAG_CLEAR;\r
3115\r
3116 if((width + offset) > 32)\r
3117 {\r
3118 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3119 data_byte = m68ki_read_8(ea+4);\r
3120 FLAG_Z |= (data_byte & mask_byte);\r
3121 }\r
3122 return;\r
3123 }\r
3124 m68ki_exception_illegal();\r
3125}\r
3126\r
3127\r
3128M68KMAKE_OP(bkpt, 0, ., .)\r
3129{\r
3130 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
3131 {\r
3132 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */\r
3133 }\r
3134 m68ki_exception_illegal();\r
3135}\r
3136\r
3137\r
3138M68KMAKE_OP(bra, 8, ., .)\r
3139{\r
3140 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3141 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
c6a4c892 3142 if(REG_PC == REG_PPC)\r
3143 USE_ALL_CYCLES();\r
cc68a136 3144}\r
3145\r
3146\r
3147M68KMAKE_OP(bra, 16, ., .)\r
3148{\r
3149 uint offset = OPER_I_16();\r
3150 REG_PC -= 2;\r
3151 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3152 m68ki_branch_16(offset);\r
c6a4c892 3153 if(REG_PC == REG_PPC)\r
3154 USE_ALL_CYCLES();\r
cc68a136 3155}\r
3156\r
3157\r
3158M68KMAKE_OP(bra, 32, ., .)\r
3159{\r
3160 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3161 {\r
3162 uint offset = OPER_I_32();\r
3163 REG_PC -= 4;\r
3164 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3165 m68ki_branch_32(offset);\r
3166 if(REG_PC == REG_PPC)\r
3167 USE_ALL_CYCLES();\r
3168 return;\r
3169 }\r
3170 else\r
3171 {\r
3172 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3173 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
c6a4c892 3174 if(REG_PC == REG_PPC)\r
3175 USE_ALL_CYCLES();\r
cc68a136 3176 }\r
3177}\r
3178\r
3179\r
3180M68KMAKE_OP(bset, 32, r, d)\r
3181{\r
3182 uint* r_dst = &DY;\r
3183 uint mask = 1 << (DX & 0x1f);\r
3184\r
3185 FLAG_Z = *r_dst & mask;\r
3186 *r_dst |= mask;\r
3187}\r
3188\r
3189\r
3190M68KMAKE_OP(bset, 8, r, .)\r
3191{\r
3192 uint ea = M68KMAKE_GET_EA_AY_8;\r
3193 uint src = m68ki_read_8(ea);\r
3194 uint mask = 1 << (DX & 7);\r
3195\r
3196 FLAG_Z = src & mask;\r
3197 m68ki_write_8(ea, src | mask);\r
3198}\r
3199\r
3200\r
3201M68KMAKE_OP(bset, 32, s, d)\r
3202{\r
3203 uint* r_dst = &DY;\r
3204 uint mask = 1 << (OPER_I_8() & 0x1f);\r
3205\r
3206 FLAG_Z = *r_dst & mask;\r
3207 *r_dst |= mask;\r
3208}\r
3209\r
3210\r
3211M68KMAKE_OP(bset, 8, s, .)\r
3212{\r
3213 uint mask = 1 << (OPER_I_8() & 7);\r
3214 uint ea = M68KMAKE_GET_EA_AY_8;\r
3215 uint src = m68ki_read_8(ea);\r
3216\r
3217 FLAG_Z = src & mask;\r
3218 m68ki_write_8(ea, src | mask);\r
3219}\r
3220\r
3221\r
3222M68KMAKE_OP(bsr, 8, ., .)\r
3223{\r
3224 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3225 m68ki_push_32(REG_PC);\r
3226 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3227}\r
3228\r
3229\r
3230M68KMAKE_OP(bsr, 16, ., .)\r
3231{\r
3232 uint offset = OPER_I_16();\r
3233 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3234 m68ki_push_32(REG_PC);\r
3235 REG_PC -= 2;\r
3236 m68ki_branch_16(offset);\r
3237}\r
3238\r
3239\r
3240M68KMAKE_OP(bsr, 32, ., .)\r
3241{\r
3242 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3243 {\r
3244 uint offset = OPER_I_32();\r
3245 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3246 m68ki_push_32(REG_PC);\r
3247 REG_PC -= 4;\r
3248 m68ki_branch_32(offset);\r
3249 return;\r
3250 }\r
3251 else\r
3252 {\r
3253 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3254 m68ki_push_32(REG_PC);\r
3255 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3256 }\r
3257}\r
3258\r
3259\r
3260M68KMAKE_OP(btst, 32, r, d)\r
3261{\r
3262 FLAG_Z = DY & (1 << (DX & 0x1f));\r
3263}\r
3264\r
3265\r
3266M68KMAKE_OP(btst, 8, r, .)\r
3267{\r
3268 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));\r
3269}\r
3270\r
3271\r
3272M68KMAKE_OP(btst, 32, s, d)\r
3273{\r
3274 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));\r
3275}\r
3276\r
3277\r
3278M68KMAKE_OP(btst, 8, s, .)\r
3279{\r
3280 uint bit = OPER_I_8() & 7;\r
3281\r
3282 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);\r
3283}\r
3284\r
3285\r
3286M68KMAKE_OP(callm, 32, ., .)\r
3287{\r
3288 /* note: watch out for pcrelative modes */\r
3289 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
3290 {\r
3291 uint ea = M68KMAKE_GET_EA_AY_32;\r
3292\r
3293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3294 REG_PC += 2;\r
3295(void)ea; /* just to avoid an 'unused variable' warning */\r
3296 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
3297 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
3298 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
3299 return;\r
3300 }\r
3301 m68ki_exception_illegal();\r
3302}\r
3303\r
3304\r
3305M68KMAKE_OP(cas, 8, ., .)\r
3306{\r
3307 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3308 {\r
3309 uint word2 = OPER_I_16();\r
3310 uint ea = M68KMAKE_GET_EA_AY_8;\r
3311 uint dest = m68ki_read_8(ea);\r
3312 uint* compare = &REG_D[word2 & 7];\r
3313 uint res = dest - MASK_OUT_ABOVE_8(*compare);\r
3314\r
3315 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3316 FLAG_N = NFLAG_8(res);\r
3317 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3318 FLAG_V = VFLAG_SUB_8(*compare, dest, res);\r
3319 FLAG_C = CFLAG_8(res);\r
3320\r
3321 if(COND_NE())\r
3322 *compare = MASK_OUT_BELOW_8(*compare) | dest;\r
3323 else\r
3324 {\r
3325 USE_CYCLES(3);\r
3326 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));\r
3327 }\r
3328 return;\r
3329 }\r
3330 m68ki_exception_illegal();\r
3331}\r
3332\r
3333\r
3334M68KMAKE_OP(cas, 16, ., .)\r
3335{\r
3336 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3337 {\r
3338 uint word2 = OPER_I_16();\r
3339 uint ea = M68KMAKE_GET_EA_AY_16;\r
3340 uint dest = m68ki_read_16(ea);\r
3341 uint* compare = &REG_D[word2 & 7];\r
3342 uint res = dest - MASK_OUT_ABOVE_16(*compare);\r
3343\r
3344 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3345 FLAG_N = NFLAG_16(res);\r
3346 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3347 FLAG_V = VFLAG_SUB_16(*compare, dest, res);\r
3348 FLAG_C = CFLAG_16(res);\r
3349\r
3350 if(COND_NE())\r
3351 *compare = MASK_OUT_BELOW_16(*compare) | dest;\r
3352 else\r
3353 {\r
3354 USE_CYCLES(3);\r
3355 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));\r
3356 }\r
3357 return;\r
3358 }\r
3359 m68ki_exception_illegal();\r
3360}\r
3361\r
3362\r
3363M68KMAKE_OP(cas, 32, ., .)\r
3364{\r
3365 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3366 {\r
3367 uint word2 = OPER_I_16();\r
3368 uint ea = M68KMAKE_GET_EA_AY_32;\r
3369 uint dest = m68ki_read_32(ea);\r
3370 uint* compare = &REG_D[word2 & 7];\r
3371 uint res = dest - *compare;\r
3372\r
3373 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3374 FLAG_N = NFLAG_32(res);\r
3375 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3376 FLAG_V = VFLAG_SUB_32(*compare, dest, res);\r
3377 FLAG_C = CFLAG_SUB_32(*compare, dest, res);\r
3378\r
3379 if(COND_NE())\r
3380 *compare = dest;\r
3381 else\r
3382 {\r
3383 USE_CYCLES(3);\r
3384 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);\r
3385 }\r
3386 return;\r
3387 }\r
3388 m68ki_exception_illegal();\r
3389}\r
3390\r
3391\r
3392M68KMAKE_OP(cas2, 16, ., .)\r
3393{\r
3394 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3395 {\r
3396 uint word2 = OPER_I_32();\r
3397 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3398 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3399 uint dest1 = m68ki_read_16(ea1);\r
3400 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);\r
3401 uint* compare2 = &REG_D[word2 & 7];\r
3402 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3403 uint dest2 = m68ki_read_16(ea2);\r
3404 uint res2;\r
3405\r
3406 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3407 FLAG_N = NFLAG_16(res1);\r
3408 FLAG_Z = MASK_OUT_ABOVE_16(res1);\r
3409 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);\r
3410 FLAG_C = CFLAG_16(res1);\r
3411\r
3412 if(COND_EQ())\r
3413 {\r
3414 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);\r
3415\r
3416 FLAG_N = NFLAG_16(res2);\r
3417 FLAG_Z = MASK_OUT_ABOVE_16(res2);\r
3418 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);\r
3419 FLAG_C = CFLAG_16(res2);\r
3420\r
3421 if(COND_EQ())\r
3422 {\r
3423 USE_CYCLES(3);\r
3424 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);\r
3425 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);\r
3426 return;\r
3427 }\r
3428 }\r
3429 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;\r
3430 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;\r
3431 return;\r
3432 }\r
3433 m68ki_exception_illegal();\r
3434}\r
3435\r
3436\r
3437M68KMAKE_OP(cas2, 32, ., .)\r
3438{\r
3439 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3440 {\r
3441 uint word2 = OPER_I_32();\r
3442 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3443 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3444 uint dest1 = m68ki_read_32(ea1);\r
3445 uint res1 = dest1 - *compare1;\r
3446 uint* compare2 = &REG_D[word2 & 7];\r
3447 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3448 uint dest2 = m68ki_read_32(ea2);\r
3449 uint res2;\r
3450\r
3451 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3452 FLAG_N = NFLAG_32(res1);\r
3453 FLAG_Z = MASK_OUT_ABOVE_32(res1);\r
3454 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);\r
3455 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);\r
3456\r
3457 if(COND_EQ())\r
3458 {\r
3459 res2 = dest2 - *compare2;\r
3460\r
3461 FLAG_N = NFLAG_32(res2);\r
3462 FLAG_Z = MASK_OUT_ABOVE_32(res2);\r
3463 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);\r
3464 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);\r
3465\r
3466 if(COND_EQ())\r
3467 {\r
3468 USE_CYCLES(3);\r
3469 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);\r
3470 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);\r
3471 return;\r
3472 }\r
3473 }\r
3474 *compare1 = dest1;\r
3475 *compare2 = dest2;\r
3476 return;\r
3477 }\r
3478 m68ki_exception_illegal();\r
3479}\r
3480\r
3481\r
3482M68KMAKE_OP(chk, 16, ., d)\r
3483{\r
3484 sint src = MAKE_INT_16(DX);\r
3485 sint bound = MAKE_INT_16(DY);\r
3486\r
3487 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3488 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3489 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3490\r
3491 if(src >= 0 && src <= bound)\r
3492 {\r
3493 return;\r
3494 }\r
3495 FLAG_N = (src < 0)<<7;\r
3496 m68ki_exception_trap(EXCEPTION_CHK);\r
3497}\r
3498\r
3499\r
3500M68KMAKE_OP(chk, 16, ., .)\r
3501{\r
3502 sint src = MAKE_INT_16(DX);\r
3503 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
3504\r
3505 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3506 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3507 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3508\r
3509 if(src >= 0 && src <= bound)\r
3510 {\r
3511 return;\r
3512 }\r
3513 FLAG_N = (src < 0)<<7;\r
3514 m68ki_exception_trap(EXCEPTION_CHK);\r
3515}\r
3516\r
3517\r
3518M68KMAKE_OP(chk, 32, ., d)\r
3519{\r
3520 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3521 {\r
3522 sint src = MAKE_INT_32(DX);\r
3523 sint bound = MAKE_INT_32(DY);\r
3524\r
3525 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3526 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3527 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3528\r
3529 if(src >= 0 && src <= bound)\r
3530 {\r
3531 return;\r
3532 }\r
3533 FLAG_N = (src < 0)<<7;\r
3534 m68ki_exception_trap(EXCEPTION_CHK);\r
3535 return;\r
3536 }\r
3537 m68ki_exception_illegal();\r
3538}\r
3539\r
3540\r
3541M68KMAKE_OP(chk, 32, ., .)\r
3542{\r
3543 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3544 {\r
3545 sint src = MAKE_INT_32(DX);\r
3546 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);\r
3547\r
3548 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3549 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3550 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3551\r
3552 if(src >= 0 && src <= bound)\r
3553 {\r
3554 return;\r
3555 }\r
3556 FLAG_N = (src < 0)<<7;\r
3557 m68ki_exception_trap(EXCEPTION_CHK);\r
3558 return;\r
3559 }\r
3560 m68ki_exception_illegal();\r
3561}\r
3562\r
3563\r
3564M68KMAKE_OP(chk2cmp2, 8, ., pcdi)\r
3565{\r
3566 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3567 {\r
3568 uint word2 = OPER_I_16();\r
3569 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3570 uint ea = EA_PCDI_8();\r
3571 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3572 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3573\r
3574 if(!BIT_F(word2))\r
3575 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3576 else\r
3577 FLAG_C = compare - lower_bound;\r
3578 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3579 if(COND_CS())\r
3580 {\r
3581 if(BIT_B(word2))\r
3582 m68ki_exception_trap(EXCEPTION_CHK);\r
3583 return;\r
3584 }\r
3585\r
3586 FLAG_C = upper_bound - compare;\r
3587 if(COND_CS() && BIT_B(word2))\r
3588 m68ki_exception_trap(EXCEPTION_CHK);\r
3589 return;\r
3590 }\r
3591 m68ki_exception_illegal();\r
3592}\r
3593\r
3594\r
3595M68KMAKE_OP(chk2cmp2, 8, ., pcix)\r
3596{\r
3597 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3598 {\r
3599 uint word2 = OPER_I_16();\r
3600 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3601 uint ea = EA_PCIX_8();\r
3602 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3603 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3604\r
3605 if(!BIT_F(word2))\r
3606 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3607 else\r
3608 FLAG_C = compare - lower_bound;\r
3609 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3610 if(COND_CS())\r
3611 {\r
3612 if(BIT_B(word2))\r
3613 m68ki_exception_trap(EXCEPTION_CHK);\r
3614 return;\r
3615 }\r
3616\r
3617 FLAG_C = upper_bound - compare;\r
3618 if(COND_CS() && BIT_B(word2))\r
3619 m68ki_exception_trap(EXCEPTION_CHK);\r
3620 return;\r
3621 }\r
3622 m68ki_exception_illegal();\r
3623}\r
3624\r
3625\r
3626M68KMAKE_OP(chk2cmp2, 8, ., .)\r
3627{\r
3628 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3629 {\r
3630 uint word2 = OPER_I_16();\r
3631 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3632 uint ea = M68KMAKE_GET_EA_AY_8;\r
3633 uint lower_bound = m68ki_read_8(ea);\r
3634 uint upper_bound = m68ki_read_8(ea + 1);\r
3635\r
3636 if(!BIT_F(word2))\r
3637 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3638 else\r
3639 FLAG_C = compare - lower_bound;\r
3640 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3641 if(COND_CS())\r
3642 {\r
3643 if(BIT_B(word2))\r
3644 m68ki_exception_trap(EXCEPTION_CHK);\r
3645 return;\r
3646 }\r
3647\r
3648 FLAG_C = upper_bound - compare;\r
3649 if(COND_CS() && BIT_B(word2))\r
3650 m68ki_exception_trap(EXCEPTION_CHK);\r
3651 return;\r
3652 }\r
3653 m68ki_exception_illegal();\r
3654}\r
3655\r
3656\r
3657M68KMAKE_OP(chk2cmp2, 16, ., pcdi)\r
3658{\r
3659 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3660 {\r
3661 uint word2 = OPER_I_16();\r
3662 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3663 uint ea = EA_PCDI_16();\r
3664 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3665 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3666\r
3667 if(!BIT_F(word2))\r
3668 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3669 else\r
3670 FLAG_C = compare - lower_bound;\r
3671 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3672 FLAG_C = CFLAG_16(FLAG_C);\r
3673 if(COND_CS())\r
3674 {\r
3675 if(BIT_B(word2))\r
3676 m68ki_exception_trap(EXCEPTION_CHK);\r
3677 return;\r
3678 }\r
3679\r
3680 if(!BIT_F(word2))\r
3681 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3682 else\r
3683 FLAG_C = upper_bound - compare;\r
3684 FLAG_C = CFLAG_16(FLAG_C);\r
3685 if(COND_CS() && BIT_B(word2))\r
3686 m68ki_exception_trap(EXCEPTION_CHK);\r
3687 return;\r
3688 }\r
3689 m68ki_exception_illegal();\r
3690}\r
3691\r
3692\r
3693M68KMAKE_OP(chk2cmp2, 16, ., pcix)\r
3694{\r
3695 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3696 {\r
3697 uint word2 = OPER_I_16();\r
3698 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3699 uint ea = EA_PCIX_16();\r
3700 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3701 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3702\r
3703 if(!BIT_F(word2))\r
3704 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3705 else\r
3706 FLAG_C = compare - lower_bound;\r
3707 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3708 FLAG_C = CFLAG_16(FLAG_C);\r
3709 if(COND_CS())\r
3710 {\r
3711 if(BIT_B(word2))\r
3712 m68ki_exception_trap(EXCEPTION_CHK);\r
3713 return;\r
3714 }\r
3715\r
3716 if(!BIT_F(word2))\r
3717 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3718 else\r
3719 FLAG_C = upper_bound - compare;\r
3720 FLAG_C = CFLAG_16(FLAG_C);\r
3721 if(COND_CS() && BIT_B(word2))\r
3722 m68ki_exception_trap(EXCEPTION_CHK);\r
3723 return;\r
3724 }\r
3725 m68ki_exception_illegal();\r
3726}\r
3727\r
3728\r
3729M68KMAKE_OP(chk2cmp2, 16, ., .)\r
3730{\r
3731 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3732 {\r
3733 uint word2 = OPER_I_16();\r
3734 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3735 uint ea = M68KMAKE_GET_EA_AY_16;\r
3736 uint lower_bound = m68ki_read_16(ea);\r
3737 uint upper_bound = m68ki_read_16(ea + 2);\r
3738\r
3739 if(!BIT_F(word2))\r
3740 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3741 else\r
3742 FLAG_C = compare - lower_bound;\r
3743\r
3744 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3745 FLAG_C = CFLAG_16(FLAG_C);\r
3746 if(COND_CS())\r
3747 {\r
3748 if(BIT_B(word2))\r
3749 m68ki_exception_trap(EXCEPTION_CHK);\r
3750 return;\r
3751 }\r
3752 if(!BIT_F(word2))\r
3753 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3754 else\r
3755 FLAG_C = upper_bound - compare;\r
3756\r
3757 FLAG_C = CFLAG_16(FLAG_C);\r
3758 if(COND_CS() && BIT_B(word2))\r
3759 m68ki_exception_trap(EXCEPTION_CHK);\r
3760 return;\r
3761 }\r
3762 m68ki_exception_illegal();\r
3763}\r
3764\r
3765\r
3766M68KMAKE_OP(chk2cmp2, 32, ., pcdi)\r
3767{\r
3768 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3769 {\r
3770 uint word2 = OPER_I_16();\r
3771 uint compare = REG_DA[(word2 >> 12) & 15];\r
3772 uint ea = EA_PCDI_32();\r
3773 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3774 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3775\r
3776 FLAG_C = compare - lower_bound;\r
3777 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3778 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3779 if(COND_CS())\r
3780 {\r
3781 if(BIT_B(word2))\r
3782 m68ki_exception_trap(EXCEPTION_CHK);\r
3783 return;\r
3784 }\r
3785\r
3786 FLAG_C = upper_bound - compare;\r
3787 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3788 if(COND_CS() && BIT_B(word2))\r
3789 m68ki_exception_trap(EXCEPTION_CHK);\r
3790 return;\r
3791 }\r
3792 m68ki_exception_illegal();\r
3793}\r
3794\r
3795\r
3796M68KMAKE_OP(chk2cmp2, 32, ., pcix)\r
3797{\r
3798 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3799 {\r
3800 uint word2 = OPER_I_16();\r
3801 uint compare = REG_DA[(word2 >> 12) & 15];\r
3802 uint ea = EA_PCIX_32();\r
3803 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3804 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3805\r
3806 FLAG_C = compare - lower_bound;\r
3807 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3808 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3809 if(COND_CS())\r
3810 {\r
3811 if(BIT_B(word2))\r
3812 m68ki_exception_trap(EXCEPTION_CHK);\r
3813 return;\r
3814 }\r
3815\r
3816 FLAG_C = upper_bound - compare;\r
3817 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3818 if(COND_CS() && BIT_B(word2))\r
3819 m68ki_exception_trap(EXCEPTION_CHK);\r
3820 return;\r
3821 }\r
3822 m68ki_exception_illegal();\r
3823}\r
3824\r
3825\r
3826M68KMAKE_OP(chk2cmp2, 32, ., .)\r
3827{\r
3828 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3829 {\r
3830 uint word2 = OPER_I_16();\r
3831 uint compare = REG_DA[(word2 >> 12) & 15];\r
3832 uint ea = M68KMAKE_GET_EA_AY_32;\r
3833 uint lower_bound = m68ki_read_32(ea);\r
3834 uint upper_bound = m68ki_read_32(ea + 4);\r
3835\r
3836 FLAG_C = compare - lower_bound;\r
3837 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3838 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3839 if(COND_CS())\r
3840 {\r
3841 if(BIT_B(word2))\r
3842 m68ki_exception_trap(EXCEPTION_CHK);\r
3843 return;\r
3844 }\r
3845\r
3846 FLAG_C = upper_bound - compare;\r
3847 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3848 if(COND_CS() && BIT_B(word2))\r
3849 m68ki_exception_trap(EXCEPTION_CHK);\r
3850 return;\r
3851 }\r
3852 m68ki_exception_illegal();\r
3853}\r
3854\r
3855\r
3856M68KMAKE_OP(clr, 8, ., d)\r
3857{\r
3858 DY &= 0xffffff00;\r
3859\r
3860 FLAG_N = NFLAG_CLEAR;\r
3861 FLAG_V = VFLAG_CLEAR;\r
3862 FLAG_C = CFLAG_CLEAR;\r
3863 FLAG_Z = ZFLAG_SET;\r
3864}\r
3865\r
3866\r
3867M68KMAKE_OP(clr, 8, ., .)\r
3868{\r
3869 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
3870\r
3871 FLAG_N = NFLAG_CLEAR;\r
3872 FLAG_V = VFLAG_CLEAR;\r
3873 FLAG_C = CFLAG_CLEAR;\r
3874 FLAG_Z = ZFLAG_SET;\r
3875}\r
3876\r
3877\r
3878M68KMAKE_OP(clr, 16, ., d)\r
3879{\r
3880 DY &= 0xffff0000;\r
3881\r
3882 FLAG_N = NFLAG_CLEAR;\r
3883 FLAG_V = VFLAG_CLEAR;\r
3884 FLAG_C = CFLAG_CLEAR;\r
3885 FLAG_Z = ZFLAG_SET;\r
3886}\r
3887\r
3888\r
3889M68KMAKE_OP(clr, 16, ., .)\r
3890{\r
3891 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);\r
3892\r
3893 FLAG_N = NFLAG_CLEAR;\r
3894 FLAG_V = VFLAG_CLEAR;\r
3895 FLAG_C = CFLAG_CLEAR;\r
3896 FLAG_Z = ZFLAG_SET;\r
3897}\r
3898\r
3899\r
3900M68KMAKE_OP(clr, 32, ., d)\r
3901{\r
3902 DY = 0;\r
3903\r
3904 FLAG_N = NFLAG_CLEAR;\r
3905 FLAG_V = VFLAG_CLEAR;\r
3906 FLAG_C = CFLAG_CLEAR;\r
3907 FLAG_Z = ZFLAG_SET;\r
3908}\r
3909\r
3910\r
3911M68KMAKE_OP(clr, 32, ., .)\r
3912{\r
3913 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);\r
3914\r
3915 FLAG_N = NFLAG_CLEAR;\r
3916 FLAG_V = VFLAG_CLEAR;\r
3917 FLAG_C = CFLAG_CLEAR;\r
3918 FLAG_Z = ZFLAG_SET;\r
3919}\r
3920\r
3921\r
3922M68KMAKE_OP(cmp, 8, ., d)\r
3923{\r
3924 uint src = MASK_OUT_ABOVE_8(DY);\r
3925 uint dst = MASK_OUT_ABOVE_8(DX);\r
3926 uint res = dst - src;\r
3927\r
3928 FLAG_N = NFLAG_8(res);\r
3929 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3930 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3931 FLAG_C = CFLAG_8(res);\r
3932}\r
3933\r
3934\r
3935M68KMAKE_OP(cmp, 8, ., .)\r
3936{\r
3937 uint src = M68KMAKE_GET_OPER_AY_8;\r
3938 uint dst = MASK_OUT_ABOVE_8(DX);\r
3939 uint res = dst - src;\r
3940\r
3941 FLAG_N = NFLAG_8(res);\r
3942 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3943 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3944 FLAG_C = CFLAG_8(res);\r
3945}\r
3946\r
3947\r
3948M68KMAKE_OP(cmp, 16, ., d)\r
3949{\r
3950 uint src = MASK_OUT_ABOVE_16(DY);\r
3951 uint dst = MASK_OUT_ABOVE_16(DX);\r
3952 uint res = dst - src;\r
3953\r
3954 FLAG_N = NFLAG_16(res);\r
3955 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3956 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3957 FLAG_C = CFLAG_16(res);\r
3958}\r
3959\r
3960\r
3961M68KMAKE_OP(cmp, 16, ., a)\r
3962{\r
3963 uint src = MASK_OUT_ABOVE_16(AY);\r
3964 uint dst = MASK_OUT_ABOVE_16(DX);\r
3965 uint res = dst - src;\r
3966\r
3967 FLAG_N = NFLAG_16(res);\r
3968 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3969 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3970 FLAG_C = CFLAG_16(res);\r
3971}\r
3972\r
3973\r
3974M68KMAKE_OP(cmp, 16, ., .)\r
3975{\r
3976 uint src = M68KMAKE_GET_OPER_AY_16;\r
3977 uint dst = MASK_OUT_ABOVE_16(DX);\r
3978 uint res = dst - src;\r
3979\r
3980 FLAG_N = NFLAG_16(res);\r
3981 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3982 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3983 FLAG_C = CFLAG_16(res);\r
3984}\r
3985\r
3986\r
3987M68KMAKE_OP(cmp, 32, ., d)\r
3988{\r
3989 uint src = DY;\r
3990 uint dst = DX;\r
3991 uint res = dst - src;\r
3992\r
3993 FLAG_N = NFLAG_32(res);\r
3994 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3995 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3996 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
3997}\r
3998\r
3999\r
4000M68KMAKE_OP(cmp, 32, ., a)\r
4001{\r
4002 uint src = AY;\r
4003 uint dst = DX;\r
4004 uint res = dst - src;\r
4005\r
4006 FLAG_N = NFLAG_32(res);\r
4007 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4008 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4009 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4010}\r
4011\r
4012\r
4013M68KMAKE_OP(cmp, 32, ., .)\r
4014{\r
4015 uint src = M68KMAKE_GET_OPER_AY_32;\r
4016 uint dst = DX;\r
4017 uint res = dst - src;\r
4018\r
4019 FLAG_N = NFLAG_32(res);\r
4020 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4021 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4022 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4023}\r
4024\r
4025\r
4026M68KMAKE_OP(cmpa, 16, ., d)\r
4027{\r
4028 uint src = MAKE_INT_16(DY);\r
4029 uint dst = AX;\r
4030 uint res = dst - src;\r
4031\r
4032 FLAG_N = NFLAG_32(res);\r
4033 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4034 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4035 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4036}\r
4037\r
4038\r
4039M68KMAKE_OP(cmpa, 16, ., a)\r
4040{\r
4041 uint src = MAKE_INT_16(AY);\r
4042 uint dst = AX;\r
4043 uint res = dst - src;\r
4044\r
4045 FLAG_N = NFLAG_32(res);\r
4046 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4047 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4048 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4049}\r
4050\r
4051\r
4052M68KMAKE_OP(cmpa, 16, ., .)\r
4053{\r
4054 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4055 uint dst = AX;\r
4056 uint res = dst - src;\r
4057\r
4058 FLAG_N = NFLAG_32(res);\r
4059 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4060 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4061 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4062}\r
4063\r
4064\r
4065M68KMAKE_OP(cmpa, 32, ., d)\r
4066{\r
4067 uint src = DY;\r
4068 uint dst = AX;\r
4069 uint res = dst - src;\r
4070\r
4071 FLAG_N = NFLAG_32(res);\r
4072 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4073 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4074 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4075}\r
4076\r
4077\r
4078M68KMAKE_OP(cmpa, 32, ., a)\r
4079{\r
4080 uint src = AY;\r
4081 uint dst = AX;\r
4082 uint res = dst - src;\r
4083\r
4084 FLAG_N = NFLAG_32(res);\r
4085 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4086 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4087 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4088}\r
4089\r
4090\r
4091M68KMAKE_OP(cmpa, 32, ., .)\r
4092{\r
4093 uint src = M68KMAKE_GET_OPER_AY_32;\r
4094 uint dst = AX;\r
4095 uint res = dst - src;\r
4096\r
4097 FLAG_N = NFLAG_32(res);\r
4098 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4099 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4100 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4101}\r
4102\r
4103\r
4104M68KMAKE_OP(cmpi, 8, ., d)\r
4105{\r
4106 uint src = OPER_I_8();\r
4107 uint dst = MASK_OUT_ABOVE_8(DY);\r
4108 uint res = dst - src;\r
4109\r
4110 FLAG_N = NFLAG_8(res);\r
4111 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4112 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4113 FLAG_C = CFLAG_8(res);\r
4114}\r
4115\r
4116\r
4117M68KMAKE_OP(cmpi, 8, ., .)\r
4118{\r
4119 uint src = OPER_I_8();\r
4120 uint dst = M68KMAKE_GET_OPER_AY_8;\r
4121 uint res = dst - src;\r
4122\r
4123 FLAG_N = NFLAG_8(res);\r
4124 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4125 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4126 FLAG_C = CFLAG_8(res);\r
4127}\r
4128\r
4129\r
4130M68KMAKE_OP(cmpi, 8, ., pcdi)\r
4131{\r
4132 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4133 {\r
4134 uint src = OPER_I_8();\r
4135 uint dst = OPER_PCDI_8();\r
4136 uint res = dst - src;\r
4137\r
4138 FLAG_N = NFLAG_8(res);\r
4139 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4140 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4141 FLAG_C = CFLAG_8(res);\r
4142 return;\r
4143 }\r
4144 m68ki_exception_illegal();\r
4145}\r
4146\r
4147\r
4148M68KMAKE_OP(cmpi, 8, ., pcix)\r
4149{\r
4150 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4151 {\r
4152 uint src = OPER_I_8();\r
4153 uint dst = OPER_PCIX_8();\r
4154 uint res = dst - src;\r
4155\r
4156 FLAG_N = NFLAG_8(res);\r
4157 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4158 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4159 FLAG_C = CFLAG_8(res);\r
4160 return;\r
4161 }\r
4162 m68ki_exception_illegal();\r
4163}\r
4164\r
4165\r
4166M68KMAKE_OP(cmpi, 16, ., d)\r
4167{\r
4168 uint src = OPER_I_16();\r
4169 uint dst = MASK_OUT_ABOVE_16(DY);\r
4170 uint res = dst - src;\r
4171\r
4172 FLAG_N = NFLAG_16(res);\r
4173 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4174 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4175 FLAG_C = CFLAG_16(res);\r
4176}\r
4177\r
4178\r
4179M68KMAKE_OP(cmpi, 16, ., .)\r
4180{\r
4181 uint src = OPER_I_16();\r
4182 uint dst = M68KMAKE_GET_OPER_AY_16;\r
4183 uint res = dst - src;\r
4184\r
4185 FLAG_N = NFLAG_16(res);\r
4186 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4187 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4188 FLAG_C = CFLAG_16(res);\r
4189}\r
4190\r
4191\r
4192M68KMAKE_OP(cmpi, 16, ., pcdi)\r
4193{\r
4194 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4195 {\r
4196 uint src = OPER_I_16();\r
4197 uint dst = OPER_PCDI_16();\r
4198 uint res = dst - src;\r
4199\r
4200 FLAG_N = NFLAG_16(res);\r
4201 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4202 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4203 FLAG_C = CFLAG_16(res);\r
4204 return;\r
4205 }\r
4206 m68ki_exception_illegal();\r
4207}\r
4208\r
4209\r
4210M68KMAKE_OP(cmpi, 16, ., pcix)\r
4211{\r
4212 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4213 {\r
4214 uint src = OPER_I_16();\r
4215 uint dst = OPER_PCIX_16();\r
4216 uint res = dst - src;\r
4217\r
4218 FLAG_N = NFLAG_16(res);\r
4219 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4220 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4221 FLAG_C = CFLAG_16(res);\r
4222 return;\r
4223 }\r
4224 m68ki_exception_illegal();\r
4225}\r
4226\r
4227\r
4228M68KMAKE_OP(cmpi, 32, ., d)\r
4229{\r
4230 uint src = OPER_I_32();\r
4231 uint dst = DY;\r
4232 uint res = dst - src;\r
4233\r
4234 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */\r
4235\r
4236 FLAG_N = NFLAG_32(res);\r
4237 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4238 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4239 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4240}\r
4241\r
4242\r
4243M68KMAKE_OP(cmpi, 32, ., .)\r
4244{\r
4245 uint src = OPER_I_32();\r
4246 uint dst = M68KMAKE_GET_OPER_AY_32;\r
4247 uint res = dst - src;\r
4248\r
4249 FLAG_N = NFLAG_32(res);\r
4250 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4251 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4252 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4253}\r
4254\r
4255\r
4256M68KMAKE_OP(cmpi, 32, ., pcdi)\r
4257{\r
4258 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4259 {\r
4260 uint src = OPER_I_32();\r
4261 uint dst = OPER_PCDI_32();\r
4262 uint res = dst - src;\r
4263\r
4264 FLAG_N = NFLAG_32(res);\r
4265 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4266 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4267 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4268 return;\r
4269 }\r
4270 m68ki_exception_illegal();\r
4271}\r
4272\r
4273\r
4274M68KMAKE_OP(cmpi, 32, ., pcix)\r
4275{\r
4276 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4277 {\r
4278 uint src = OPER_I_32();\r
4279 uint dst = OPER_PCIX_32();\r
4280 uint res = dst - src;\r
4281\r
4282 FLAG_N = NFLAG_32(res);\r
4283 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4284 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4285 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4286 return;\r
4287 }\r
4288 m68ki_exception_illegal();\r
4289}\r
4290\r
4291\r
4292M68KMAKE_OP(cmpm, 8, ., ax7)\r
4293{\r
4294 uint src = OPER_AY_PI_8();\r
4295 uint dst = OPER_A7_PI_8();\r
4296 uint res = dst - src;\r
4297\r
4298 FLAG_N = NFLAG_8(res);\r
4299 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4300 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4301 FLAG_C = CFLAG_8(res);\r
4302}\r
4303\r
4304\r
4305M68KMAKE_OP(cmpm, 8, ., ay7)\r
4306{\r
4307 uint src = OPER_A7_PI_8();\r
4308 uint dst = OPER_AX_PI_8();\r
4309 uint res = dst - src;\r
4310\r
4311 FLAG_N = NFLAG_8(res);\r
4312 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4313 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4314 FLAG_C = CFLAG_8(res);\r
4315}\r
4316\r
4317\r
4318M68KMAKE_OP(cmpm, 8, ., axy7)\r
4319{\r
4320 uint src = OPER_A7_PI_8();\r
4321 uint dst = OPER_A7_PI_8();\r
4322 uint res = dst - src;\r
4323\r
4324 FLAG_N = NFLAG_8(res);\r
4325 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4326 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4327 FLAG_C = CFLAG_8(res);\r
4328}\r
4329\r
4330\r
4331M68KMAKE_OP(cmpm, 8, ., .)\r
4332{\r
4333 uint src = OPER_AY_PI_8();\r
4334 uint dst = OPER_AX_PI_8();\r
4335 uint res = dst - src;\r
4336\r
4337 FLAG_N = NFLAG_8(res);\r
4338 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4339 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4340 FLAG_C = CFLAG_8(res);\r
4341}\r
4342\r
4343\r
4344M68KMAKE_OP(cmpm, 16, ., .)\r
4345{\r
4346 uint src = OPER_AY_PI_16();\r
4347 uint dst = OPER_AX_PI_16();\r
4348 uint res = dst - src;\r
4349\r
4350 FLAG_N = NFLAG_16(res);\r
4351 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4352 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4353 FLAG_C = CFLAG_16(res);\r
4354}\r
4355\r
4356\r
4357M68KMAKE_OP(cmpm, 32, ., .)\r
4358{\r
4359 uint src = OPER_AY_PI_32();\r
4360 uint dst = OPER_AX_PI_32();\r
4361 uint res = dst - src;\r
4362\r
4363 FLAG_N = NFLAG_32(res);\r
4364 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4365 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4366 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4367}\r
4368\r
4369\r
4370M68KMAKE_OP(cpbcc, 32, ., .)\r
4371{\r
4372 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4373 {\r
4374 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4375 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4376 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4377 return;\r
4378 }\r
4379 m68ki_exception_1111();\r
4380}\r
4381\r
4382\r
4383M68KMAKE_OP(cpdbcc, 32, ., .)\r
4384{\r
4385 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4386 {\r
4387 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4388 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4389 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4390 return;\r
4391 }\r
4392 m68ki_exception_1111();\r
4393}\r
4394\r
4395\r
4396M68KMAKE_OP(cpgen, 32, ., .)\r
4397{\r
4398 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4399 {\r
4400 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4401 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4402 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4403 return;\r
4404 }\r
4405 m68ki_exception_1111();\r
4406}\r
4407\r
4408\r
4409M68KMAKE_OP(cpscc, 32, ., .)\r
4410{\r
4411 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4412 {\r
4413 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4414 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4415 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4416 return;\r
4417 }\r
4418 m68ki_exception_1111();\r
4419}\r
4420\r
4421\r
4422M68KMAKE_OP(cptrapcc, 32, ., .)\r
4423{\r
4424 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4425 {\r
4426 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4427 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4428 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4429 return;\r
4430 }\r
4431 m68ki_exception_1111();\r
4432}\r
4433\r
4434\r
4435M68KMAKE_OP(dbt, 16, ., .)\r
4436{\r
4437 REG_PC += 2;\r
4438}\r
4439\r
4440\r
4441M68KMAKE_OP(dbf, 16, ., .)\r
4442{\r
4443 uint* r_dst = &DY;\r
4444 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4445\r
4446 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4447 if(res != 0xffff)\r
4448 {\r
4449 uint offset = OPER_I_16();\r
4450 REG_PC -= 2;\r
4451 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4452 m68ki_branch_16(offset);\r
4453 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4454 return;\r
4455 }\r
4456 REG_PC += 2;\r
4457 USE_CYCLES(CYC_DBCC_F_EXP);\r
4458}\r
4459\r
4460\r
4461M68KMAKE_OP(dbcc, 16, ., .)\r
4462{\r
4463 if(M68KMAKE_NOT_CC)\r
4464 {\r
4465 uint* r_dst = &DY;\r
4466 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4467\r
4468 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4469 if(res != 0xffff)\r
4470 {\r
4471 uint offset = OPER_I_16();\r
4472 REG_PC -= 2;\r
4473 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4474 m68ki_branch_16(offset);\r
4475 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4476 return;\r
4477 }\r
4478 REG_PC += 2;\r
4479 USE_CYCLES(CYC_DBCC_F_EXP);\r
4480 return;\r
4481 }\r
4482 REG_PC += 2;\r
4483}\r
4484\r
4485\r
4486M68KMAKE_OP(divs, 16, ., d)\r
4487{\r
4488 uint* r_dst = &DX;\r
4489 sint src = MAKE_INT_16(DY);\r
4490 sint quotient;\r
4491 sint remainder;\r
4492\r
4493 if(src != 0)\r
4494 {\r
4495 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4496 {\r
4497 FLAG_Z = 0;\r
4498 FLAG_N = NFLAG_CLEAR;\r
4499 FLAG_V = VFLAG_CLEAR;\r
4500 FLAG_C = CFLAG_CLEAR;\r
4501 *r_dst = 0;\r
4502 return;\r
4503 }\r
4504\r
4505 quotient = MAKE_INT_32(*r_dst) / src;\r
4506 remainder = MAKE_INT_32(*r_dst) % src;\r
4507\r
4508 if(quotient == MAKE_INT_16(quotient))\r
4509 {\r
4510 FLAG_Z = quotient;\r
4511 FLAG_N = NFLAG_16(quotient);\r
4512 FLAG_V = VFLAG_CLEAR;\r
4513 FLAG_C = CFLAG_CLEAR;\r
4514 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4515 return;\r
4516 }\r
4517 FLAG_V = VFLAG_SET;\r
4518 return;\r
4519 }\r
4520 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4521}\r
4522\r
4523\r
4524M68KMAKE_OP(divs, 16, ., .)\r
4525{\r
4526 uint* r_dst = &DX;\r
4527 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4528 sint quotient;\r
4529 sint remainder;\r
4530\r
4531 if(src != 0)\r
4532 {\r
4533 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4534 {\r
4535 FLAG_Z = 0;\r
4536 FLAG_N = NFLAG_CLEAR;\r
4537 FLAG_V = VFLAG_CLEAR;\r
4538 FLAG_C = CFLAG_CLEAR;\r
4539 *r_dst = 0;\r
4540 return;\r
4541 }\r
4542\r
4543 quotient = MAKE_INT_32(*r_dst) / src;\r
4544 remainder = MAKE_INT_32(*r_dst) % src;\r
4545\r
4546 if(quotient == MAKE_INT_16(quotient))\r
4547 {\r
4548 FLAG_Z = quotient;\r
4549 FLAG_N = NFLAG_16(quotient);\r
4550 FLAG_V = VFLAG_CLEAR;\r
4551 FLAG_C = CFLAG_CLEAR;\r
4552 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4553 return;\r
4554 }\r
4555 FLAG_V = VFLAG_SET;\r
4556 return;\r
4557 }\r
4558 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4559}\r
4560\r
4561\r
4562M68KMAKE_OP(divu, 16, ., d)\r
4563{\r
4564 uint* r_dst = &DX;\r
4565 uint src = MASK_OUT_ABOVE_16(DY);\r
4566\r
4567 if(src != 0)\r
4568 {\r
4569 uint quotient = *r_dst / src;\r
4570 uint remainder = *r_dst % src;\r
4571\r
4572 if(quotient < 0x10000)\r
4573 {\r
4574 FLAG_Z = quotient;\r
4575 FLAG_N = NFLAG_16(quotient);\r
4576 FLAG_V = VFLAG_CLEAR;\r
4577 FLAG_C = CFLAG_CLEAR;\r
4578 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4579 return;\r
4580 }\r
4581 FLAG_V = VFLAG_SET;\r
4582 return;\r
4583 }\r
4584 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4585}\r
4586\r
4587\r
4588M68KMAKE_OP(divu, 16, ., .)\r
4589{\r
4590 uint* r_dst = &DX;\r
4591 uint src = M68KMAKE_GET_OPER_AY_16;\r
4592\r
4593 if(src != 0)\r
4594 {\r
4595 uint quotient = *r_dst / src;\r
4596 uint remainder = *r_dst % src;\r
4597\r
4598 if(quotient < 0x10000)\r
4599 {\r
4600 FLAG_Z = quotient;\r
4601 FLAG_N = NFLAG_16(quotient);\r
4602 FLAG_V = VFLAG_CLEAR;\r
4603 FLAG_C = CFLAG_CLEAR;\r
4604 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4605 return;\r
4606 }\r
4607 FLAG_V = VFLAG_SET;\r
4608 return;\r
4609 }\r
4610 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4611}\r
4612\r
4613\r
4614M68KMAKE_OP(divl, 32, ., d)\r
4615{\r
4616#if M68K_USE_64_BIT\r
4617\r
4618 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4619 {\r
4620 uint word2 = OPER_I_16();\r
4621 uint64 divisor = DY;\r
4622 uint64 dividend = 0;\r
4623 uint64 quotient = 0;\r
4624 uint64 remainder = 0;\r
4625\r
4626 if(divisor != 0)\r
4627 {\r
4628 if(BIT_A(word2)) /* 64 bit */\r
4629 {\r
4630 dividend = REG_D[word2 & 7];\r
4631 dividend <<= 32;\r
4632 dividend |= REG_D[(word2 >> 12) & 7];\r
4633\r
4634 if(BIT_B(word2)) /* signed */\r
4635 {\r
4636 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4637 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4638 if((sint64)quotient != (sint64)((sint32)quotient))\r
4639 {\r
4640 FLAG_V = VFLAG_SET;\r
4641 return;\r
4642 }\r
4643 }\r
4644 else /* unsigned */\r
4645 {\r
4646 quotient = dividend / divisor;\r
4647 if(quotient > 0xffffffff)\r
4648 {\r
4649 FLAG_V = VFLAG_SET;\r
4650 return;\r
4651 }\r
4652 remainder = dividend % divisor;\r
4653 }\r
4654 }\r
4655 else /* 32 bit */\r
4656 {\r
4657 dividend = REG_D[(word2 >> 12) & 7];\r
4658 if(BIT_B(word2)) /* signed */\r
4659 {\r
4660 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4661 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4662 }\r
4663 else /* unsigned */\r
4664 {\r
4665 quotient = dividend / divisor;\r
4666 remainder = dividend % divisor;\r
4667 }\r
4668 }\r
4669\r
4670 REG_D[word2 & 7] = remainder;\r
4671 REG_D[(word2 >> 12) & 7] = quotient;\r
4672\r
4673 FLAG_N = NFLAG_32(quotient);\r
4674 FLAG_Z = quotient;\r
4675 FLAG_V = VFLAG_CLEAR;\r
4676 FLAG_C = CFLAG_CLEAR;\r
4677 return;\r
4678 }\r
4679 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4680 return;\r
4681 }\r
4682 m68ki_exception_illegal();\r
4683\r
4684#else\r
4685\r
4686 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4687 {\r
4688 uint word2 = OPER_I_16();\r
4689 uint divisor = DY;\r
4690 uint dividend_hi = REG_D[word2 & 7];\r
4691 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4692 uint quotient = 0;\r
4693 uint remainder = 0;\r
4694 uint dividend_neg = 0;\r
4695 uint divisor_neg = 0;\r
4696 sint i;\r
4697 uint overflow;\r
4698\r
4699 if(divisor != 0)\r
4700 {\r
4701 /* quad / long : long quotient, long remainder */\r
4702 if(BIT_A(word2))\r
4703 {\r
4704 if(BIT_B(word2)) /* signed */\r
4705 {\r
4706 /* special case in signed divide */\r
4707 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4708 {\r
4709 REG_D[word2 & 7] = 0;\r
4710 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4711\r
4712 FLAG_N = NFLAG_SET;\r
4713 FLAG_Z = ZFLAG_CLEAR;\r
4714 FLAG_V = VFLAG_CLEAR;\r
4715 FLAG_C = CFLAG_CLEAR;\r
4716 return;\r
4717 }\r
4718 if(GET_MSB_32(dividend_hi))\r
4719 {\r
4720 dividend_neg = 1;\r
4721 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4722 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4723 }\r
4724 if(GET_MSB_32(divisor))\r
4725 {\r
4726 divisor_neg = 1;\r
4727 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4728\r
4729 }\r
4730 }\r
4731\r
4732 /* if the upper long is greater than the divisor, we're overflowing. */\r
4733 if(dividend_hi >= divisor)\r
4734 {\r
4735 FLAG_V = VFLAG_SET;\r
4736 return;\r
4737 }\r
4738\r
4739 for(i = 31; i >= 0; i--)\r
4740 {\r
4741 quotient <<= 1;\r
4742 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4743 if(remainder >= divisor)\r
4744 {\r
4745 remainder -= divisor;\r
4746 quotient++;\r
4747 }\r
4748 }\r
4749 for(i = 31; i >= 0; i--)\r
4750 {\r
4751 quotient <<= 1;\r
4752 overflow = GET_MSB_32(remainder);\r
4753 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4754 if(remainder >= divisor || overflow)\r
4755 {\r
4756 remainder -= divisor;\r
4757 quotient++;\r
4758 }\r
4759 }\r
4760\r
4761 if(BIT_B(word2)) /* signed */\r
4762 {\r
4763 if(quotient > 0x7fffffff)\r
4764 {\r
4765 FLAG_V = VFLAG_SET;\r
4766 return;\r
4767 }\r
4768 if(dividend_neg)\r
4769 {\r
4770 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4771 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4772 }\r
4773 if(divisor_neg)\r
4774 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4775 }\r
4776\r
4777 REG_D[word2 & 7] = remainder;\r
4778 REG_D[(word2 >> 12) & 7] = quotient;\r
4779\r
4780 FLAG_N = NFLAG_32(quotient);\r
4781 FLAG_Z = quotient;\r
4782 FLAG_V = VFLAG_CLEAR;\r
4783 FLAG_C = CFLAG_CLEAR;\r
4784 return;\r
4785 }\r
4786\r
4787 /* long / long: long quotient, maybe long remainder */\r
4788 if(BIT_B(word2)) /* signed */\r
4789 {\r
4790 /* Special case in divide */\r
4791 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4792 {\r
4793 FLAG_N = NFLAG_SET;\r
4794 FLAG_Z = ZFLAG_CLEAR;\r
4795 FLAG_V = VFLAG_CLEAR;\r
4796 FLAG_C = CFLAG_CLEAR;\r
4797 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4798 REG_D[word2 & 7] = 0;\r
4799 return;\r
4800 }\r
4801 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
4802 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
4803 }\r
4804 else\r
4805 {\r
4806 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
4807 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
4808 }\r
4809\r
4810 FLAG_N = NFLAG_32(quotient);\r
4811 FLAG_Z = quotient;\r
4812 FLAG_V = VFLAG_CLEAR;\r
4813 FLAG_C = CFLAG_CLEAR;\r
4814 return;\r
4815 }\r
4816 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4817 return;\r
4818 }\r
4819 m68ki_exception_illegal();\r
4820\r
4821#endif\r
4822}\r
4823\r
4824\r
4825M68KMAKE_OP(divl, 32, ., .)\r
4826{\r
4827#if M68K_USE_64_BIT\r
4828\r
4829 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4830 {\r
4831 uint word2 = OPER_I_16();\r
4832 uint64 divisor = M68KMAKE_GET_OPER_AY_32;\r
4833 uint64 dividend = 0;\r
4834 uint64 quotient = 0;\r
4835 uint64 remainder = 0;\r
4836\r
4837 if(divisor != 0)\r
4838 {\r
4839 if(BIT_A(word2)) /* 64 bit */\r
4840 {\r
4841 dividend = REG_D[word2 & 7];\r
4842 dividend <<= 32;\r
4843 dividend |= REG_D[(word2 >> 12) & 7];\r
4844\r
4845 if(BIT_B(word2)) /* signed */\r
4846 {\r
4847 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4848 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4849 if((sint64)quotient != (sint64)((sint32)quotient))\r
4850 {\r
4851 FLAG_V = VFLAG_SET;\r
4852 return;\r
4853 }\r
4854 }\r
4855 else /* unsigned */\r
4856 {\r
4857 quotient = dividend / divisor;\r
4858 if(quotient > 0xffffffff)\r
4859 {\r
4860 FLAG_V = VFLAG_SET;\r
4861 return;\r
4862 }\r
4863 remainder = dividend % divisor;\r
4864 }\r
4865 }\r
4866 else /* 32 bit */\r
4867 {\r
4868 dividend = REG_D[(word2 >> 12) & 7];\r
4869 if(BIT_B(word2)) /* signed */\r
4870 {\r
4871 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4872 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4873 }\r
4874 else /* unsigned */\r
4875 {\r
4876 quotient = dividend / divisor;\r
4877 remainder = dividend % divisor;\r
4878 }\r
4879 }\r
4880\r
4881 REG_D[word2 & 7] = remainder;\r
4882 REG_D[(word2 >> 12) & 7] = quotient;\r
4883\r
4884 FLAG_N = NFLAG_32(quotient);\r
4885 FLAG_Z = quotient;\r
4886 FLAG_V = VFLAG_CLEAR;\r
4887 FLAG_C = CFLAG_CLEAR;\r
4888 return;\r
4889 }\r
4890 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4891 return;\r
4892 }\r
4893 m68ki_exception_illegal();\r
4894\r
4895#else\r
4896\r
4897 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4898 {\r
4899 uint word2 = OPER_I_16();\r
4900 uint divisor = M68KMAKE_GET_OPER_AY_32;\r
4901 uint dividend_hi = REG_D[word2 & 7];\r
4902 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4903 uint quotient = 0;\r
4904 uint remainder = 0;\r
4905 uint dividend_neg = 0;\r
4906 uint divisor_neg = 0;\r
4907 sint i;\r
4908 uint overflow;\r
4909\r
4910 if(divisor != 0)\r
4911 {\r
4912 /* quad / long : long quotient, long remainder */\r
4913 if(BIT_A(word2))\r
4914 {\r
4915 if(BIT_B(word2)) /* signed */\r
4916 {\r
4917 /* special case in signed divide */\r
4918 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4919 {\r
4920 REG_D[word2 & 7] = 0;\r
4921 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4922\r
4923 FLAG_N = NFLAG_SET;\r
4924 FLAG_Z = ZFLAG_CLEAR;\r
4925 FLAG_V = VFLAG_CLEAR;\r
4926 FLAG_C = CFLAG_CLEAR;\r
4927 return;\r
4928 }\r
4929 if(GET_MSB_32(dividend_hi))\r
4930 {\r
4931 dividend_neg = 1;\r
4932 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4933 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4934 }\r
4935 if(GET_MSB_32(divisor))\r
4936 {\r
4937 divisor_neg = 1;\r
4938 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4939\r
4940 }\r
4941 }\r
4942\r
4943 /* if the upper long is greater than the divisor, we're overflowing. */\r
4944 if(dividend_hi >= divisor)\r
4945 {\r
4946 FLAG_V = VFLAG_SET;\r
4947 return;\r
4948 }\r
4949\r
4950 for(i = 31; i >= 0; i--)\r
4951 {\r
4952 quotient <<= 1;\r
4953 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4954 if(remainder >= divisor)\r
4955 {\r
4956 remainder -= divisor;\r
4957 quotient++;\r
4958 }\r
4959 }\r
4960 for(i = 31; i >= 0; i--)\r
4961 {\r
4962 quotient <<= 1;\r
4963 overflow = GET_MSB_32(remainder);\r
4964 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4965 if(remainder >= divisor || overflow)\r
4966 {\r
4967 remainder -= divisor;\r
4968 quotient++;\r
4969 }\r
4970 }\r
4971\r
4972 if(BIT_B(word2)) /* signed */\r
4973 {\r
4974 if(quotient > 0x7fffffff)\r
4975 {\r
4976 FLAG_V = VFLAG_SET;\r
4977 return;\r
4978 }\r
4979 if(dividend_neg)\r
4980 {\r
4981 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4982 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4983 }\r
4984 if(divisor_neg)\r
4985 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4986 }\r
4987\r
4988 REG_D[word2 & 7] = remainder;\r
4989 REG_D[(word2 >> 12) & 7] = quotient;\r
4990\r
4991 FLAG_N = NFLAG_32(quotient);\r
4992 FLAG_Z = quotient;\r
4993 FLAG_V = VFLAG_CLEAR;\r
4994 FLAG_C = CFLAG_CLEAR;\r
4995 return;\r
4996 }\r
4997\r
4998 /* long / long: long quotient, maybe long remainder */\r
4999 if(BIT_B(word2)) /* signed */\r
5000 {\r
5001 /* Special case in divide */\r
5002 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
5003 {\r
5004 FLAG_N = NFLAG_SET;\r
5005 FLAG_Z = ZFLAG_CLEAR;\r
5006 FLAG_V = VFLAG_CLEAR;\r
5007 FLAG_C = CFLAG_CLEAR;\r
5008 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
5009 REG_D[word2 & 7] = 0;\r
5010 return;\r
5011 }\r
5012 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
5013 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
5014 }\r
5015 else\r
5016 {\r
5017 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
5018 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
5019 }\r
5020\r
5021 FLAG_N = NFLAG_32(quotient);\r
5022 FLAG_Z = quotient;\r
5023 FLAG_V = VFLAG_CLEAR;\r
5024 FLAG_C = CFLAG_CLEAR;\r
5025 return;\r
5026 }\r
5027 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
5028 return;\r
5029 }\r
5030 m68ki_exception_illegal();\r
5031\r
5032#endif\r
5033}\r
5034\r
5035\r
5036M68KMAKE_OP(eor, 8, ., d)\r
5037{\r
5038 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));\r
5039\r
5040 FLAG_N = NFLAG_8(res);\r
5041 FLAG_Z = res;\r
5042 FLAG_C = CFLAG_CLEAR;\r
5043 FLAG_V = VFLAG_CLEAR;\r
5044}\r
5045\r
5046\r
5047M68KMAKE_OP(eor, 8, ., .)\r
5048{\r
5049 uint ea = M68KMAKE_GET_EA_AY_8;\r
5050 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));\r
5051\r
5052 m68ki_write_8(ea, res);\r
5053\r
5054 FLAG_N = NFLAG_8(res);\r
5055 FLAG_Z = res;\r
5056 FLAG_C = CFLAG_CLEAR;\r
5057 FLAG_V = VFLAG_CLEAR;\r
5058}\r
5059\r
5060\r
5061M68KMAKE_OP(eor, 16, ., d)\r
5062{\r
5063 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));\r
5064\r
5065 FLAG_N = NFLAG_16(res);\r
5066 FLAG_Z = res;\r
5067 FLAG_C = CFLAG_CLEAR;\r
5068 FLAG_V = VFLAG_CLEAR;\r
5069}\r
5070\r
5071\r
5072M68KMAKE_OP(eor, 16, ., .)\r
5073{\r
5074 uint ea = M68KMAKE_GET_EA_AY_16;\r
5075 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));\r
5076\r
5077 m68ki_write_16(ea, res);\r
5078\r
5079 FLAG_N = NFLAG_16(res);\r
5080 FLAG_Z = res;\r
5081 FLAG_C = CFLAG_CLEAR;\r
5082 FLAG_V = VFLAG_CLEAR;\r
5083}\r
5084\r
5085\r
5086M68KMAKE_OP(eor, 32, ., d)\r
5087{\r
5088 uint res = DY ^= DX;\r
5089\r
5090 FLAG_N = NFLAG_32(res);\r
5091 FLAG_Z = res;\r
5092 FLAG_C = CFLAG_CLEAR;\r
5093 FLAG_V = VFLAG_CLEAR;\r
5094}\r
5095\r
5096\r
5097M68KMAKE_OP(eor, 32, ., .)\r
5098{\r
5099 uint ea = M68KMAKE_GET_EA_AY_32;\r
5100 uint res = DX ^ m68ki_read_32(ea);\r
5101\r
5102 m68ki_write_32(ea, res);\r
5103\r
5104 FLAG_N = NFLAG_32(res);\r
5105 FLAG_Z = res;\r
5106 FLAG_C = CFLAG_CLEAR;\r
5107 FLAG_V = VFLAG_CLEAR;\r
5108}\r
5109\r
5110\r
5111M68KMAKE_OP(eori, 8, ., d)\r
5112{\r
5113 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());\r
5114\r
5115 FLAG_N = NFLAG_8(res);\r
5116 FLAG_Z = res;\r
5117 FLAG_C = CFLAG_CLEAR;\r
5118 FLAG_V = VFLAG_CLEAR;\r
5119}\r
5120\r
5121\r
5122M68KMAKE_OP(eori, 8, ., .)\r
5123{\r
5124 uint src = OPER_I_8();\r
5125 uint ea = M68KMAKE_GET_EA_AY_8;\r
5126 uint res = src ^ m68ki_read_8(ea);\r
5127\r
5128 m68ki_write_8(ea, res);\r
5129\r
5130 FLAG_N = NFLAG_8(res);\r
5131 FLAG_Z = res;\r
5132 FLAG_C = CFLAG_CLEAR;\r
5133 FLAG_V = VFLAG_CLEAR;\r
5134}\r
5135\r
5136\r
5137M68KMAKE_OP(eori, 16, ., d)\r
5138{\r
5139 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());\r
5140\r
5141 FLAG_N = NFLAG_16(res);\r
5142 FLAG_Z = res;\r
5143 FLAG_C = CFLAG_CLEAR;\r
5144 FLAG_V = VFLAG_CLEAR;\r
5145}\r
5146\r
5147\r
5148M68KMAKE_OP(eori, 16, ., .)\r
5149{\r
5150 uint src = OPER_I_16();\r
5151 uint ea = M68KMAKE_GET_EA_AY_16;\r
5152 uint res = src ^ m68ki_read_16(ea);\r
5153\r
5154 m68ki_write_16(ea, res);\r
5155\r
5156 FLAG_N = NFLAG_16(res);\r
5157 FLAG_Z = res;\r
5158 FLAG_C = CFLAG_CLEAR;\r
5159 FLAG_V = VFLAG_CLEAR;\r
5160}\r
5161\r
5162\r
5163M68KMAKE_OP(eori, 32, ., d)\r
5164{\r
5165 uint res = DY ^= OPER_I_32();\r
5166\r
5167 FLAG_N = NFLAG_32(res);\r
5168 FLAG_Z = res;\r
5169 FLAG_C = CFLAG_CLEAR;\r
5170 FLAG_V = VFLAG_CLEAR;\r
5171}\r
5172\r
5173\r
5174M68KMAKE_OP(eori, 32, ., .)\r
5175{\r
5176 uint src = OPER_I_32();\r
5177 uint ea = M68KMAKE_GET_EA_AY_32;\r
5178 uint res = src ^ m68ki_read_32(ea);\r
5179\r
5180 m68ki_write_32(ea, res);\r
5181\r
5182 FLAG_N = NFLAG_32(res);\r
5183 FLAG_Z = res;\r
5184 FLAG_C = CFLAG_CLEAR;\r
5185 FLAG_V = VFLAG_CLEAR;\r
5186}\r
5187\r
5188\r
5189M68KMAKE_OP(eori, 16, toc, .)\r
5190{\r
5191 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());\r
5192}\r
5193\r
5194\r
5195M68KMAKE_OP(eori, 16, tos, .)\r
5196{\r
5197 if(FLAG_S)\r
5198 {\r
5199 uint src = OPER_I_16();\r
5200 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5201 m68ki_set_sr(m68ki_get_sr() ^ src);\r
5202 return;\r
5203 }\r
5204 m68ki_exception_privilege_violation();\r
5205}\r
5206\r
5207\r
5208M68KMAKE_OP(exg, 32, dd, .)\r
5209{\r
5210 uint* reg_a = &DX;\r
5211 uint* reg_b = &DY;\r
5212 uint tmp = *reg_a;\r
5213 *reg_a = *reg_b;\r
5214 *reg_b = tmp;\r
5215}\r
5216\r
5217\r
5218M68KMAKE_OP(exg, 32, aa, .)\r
5219{\r
5220 uint* reg_a = &AX;\r
5221 uint* reg_b = &AY;\r
5222 uint tmp = *reg_a;\r
5223 *reg_a = *reg_b;\r
5224 *reg_b = tmp;\r
5225}\r
5226\r
5227\r
5228M68KMAKE_OP(exg, 32, da, .)\r
5229{\r
5230 uint* reg_a = &DX;\r
5231 uint* reg_b = &AY;\r
5232 uint tmp = *reg_a;\r
5233 *reg_a = *reg_b;\r
5234 *reg_b = tmp;\r
5235}\r
5236\r
5237\r
5238M68KMAKE_OP(ext, 16, ., .)\r
5239{\r
5240 uint* r_dst = &DY;\r
5241\r
5242 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);\r
5243\r
5244 FLAG_N = NFLAG_16(*r_dst);\r
5245 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
5246 FLAG_V = VFLAG_CLEAR;\r
5247 FLAG_C = CFLAG_CLEAR;\r
5248}\r
5249\r
5250\r
5251M68KMAKE_OP(ext, 32, ., .)\r
5252{\r
5253 uint* r_dst = &DY;\r
5254\r
5255 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);\r
5256\r
5257 FLAG_N = NFLAG_32(*r_dst);\r
5258 FLAG_Z = *r_dst;\r
5259 FLAG_V = VFLAG_CLEAR;\r
5260 FLAG_C = CFLAG_CLEAR;\r
5261}\r
5262\r
5263\r
5264M68KMAKE_OP(extb, 32, ., .)\r
5265{\r
5266 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5267 {\r
5268 uint* r_dst = &DY;\r
5269\r
5270 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);\r
5271\r
5272 FLAG_N = NFLAG_32(*r_dst);\r
5273 FLAG_Z = *r_dst;\r
5274 FLAG_V = VFLAG_CLEAR;\r
5275 FLAG_C = CFLAG_CLEAR;\r
5276 return;\r
5277 }\r
5278 m68ki_exception_illegal();\r
5279}\r
5280\r
5281\r
5282M68KMAKE_OP(illegal, 0, ., .)\r
5283{\r
5284 m68ki_exception_illegal();\r
5285}\r
5286\r
5287M68KMAKE_OP(jmp, 32, ., .)\r
5288{\r
5289 m68ki_jump(M68KMAKE_GET_EA_AY_32);\r
5290 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5291 if(REG_PC == REG_PPC)\r
5292 USE_ALL_CYCLES();\r
5293}\r
5294\r
5295\r
5296M68KMAKE_OP(jsr, 32, ., .)\r
5297{\r
5298 uint ea = M68KMAKE_GET_EA_AY_32;\r
5299 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
c6a4c892 5300 m68ki_push_32(REG_PC);\r
cc68a136 5301 m68ki_jump(ea);\r
5302}\r
5303\r
5304\r
5305M68KMAKE_OP(lea, 32, ., .)\r
5306{\r
5307 AX = M68KMAKE_GET_EA_AY_32;\r
5308}\r
5309\r
5310\r
5311M68KMAKE_OP(link, 16, ., a7)\r
5312{\r
5313 REG_A[7] -= 4;\r
5314 m68ki_write_32(REG_A[7], REG_A[7]);\r
5315 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5316}\r
5317\r
5318\r
5319M68KMAKE_OP(link, 16, ., .)\r
5320{\r
5321 uint* r_dst = &AY;\r
5322\r
5323 m68ki_push_32(*r_dst);\r
5324 *r_dst = REG_A[7];\r
5325 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5326}\r
5327\r
5328\r
5329M68KMAKE_OP(link, 32, ., a7)\r
5330{\r
5331 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5332 {\r
5333 REG_A[7] -= 4;\r
5334 m68ki_write_32(REG_A[7], REG_A[7]);\r
5335 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5336 return;\r
5337 }\r
5338 m68ki_exception_illegal();\r
5339}\r
5340\r
5341\r
5342M68KMAKE_OP(link, 32, ., .)\r
5343{\r
5344 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5345 {\r
5346 uint* r_dst = &AY;\r
5347\r
5348 m68ki_push_32(*r_dst);\r
5349 *r_dst = REG_A[7];\r
5350 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5351 return;\r
5352 }\r
5353 m68ki_exception_illegal();\r
5354}\r
5355\r
5356\r
5357M68KMAKE_OP(lsr, 8, s, .)\r
5358{\r
5359 uint* r_dst = &DY;\r
5360 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5361 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5362 uint res = src >> shift;\r
5363\r
5364 if(shift != 0)\r
5365 USE_CYCLES(shift<<CYC_SHIFT);\r
5366\r
5367 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5368\r
5369 FLAG_N = NFLAG_CLEAR;\r
5370 FLAG_Z = res;\r
5371 FLAG_X = FLAG_C = src << (9-shift);\r
5372 FLAG_V = VFLAG_CLEAR;\r
5373}\r
5374\r
5375\r
5376M68KMAKE_OP(lsr, 16, s, .)\r
5377{\r
5378 uint* r_dst = &DY;\r
5379 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5380 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5381 uint res = src >> shift;\r
5382\r
5383 if(shift != 0)\r
5384 USE_CYCLES(shift<<CYC_SHIFT);\r
5385\r
5386 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5387\r
5388 FLAG_N = NFLAG_CLEAR;\r
5389 FLAG_Z = res;\r
5390 FLAG_X = FLAG_C = src << (9-shift);\r
5391 FLAG_V = VFLAG_CLEAR;\r
5392}\r
5393\r
5394\r
5395M68KMAKE_OP(lsr, 32, s, .)\r
5396{\r
5397 uint* r_dst = &DY;\r
5398 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5399 uint src = *r_dst;\r
5400 uint res = src >> shift;\r
5401\r
5402 if(shift != 0)\r
5403 USE_CYCLES(shift<<CYC_SHIFT);\r
5404\r
5405 *r_dst = res;\r
5406\r
5407 FLAG_N = NFLAG_CLEAR;\r
5408 FLAG_Z = res;\r
5409 FLAG_X = FLAG_C = src << (9-shift);\r
5410 FLAG_V = VFLAG_CLEAR;\r
5411}\r
5412\r
5413\r
5414M68KMAKE_OP(lsr, 8, r, .)\r
5415{\r
5416 uint* r_dst = &DY;\r
5417 uint shift = DX & 0x3f;\r
5418 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5419 uint res = src >> shift;\r
5420\r
5421 if(shift != 0)\r
5422 {\r
5423 USE_CYCLES(shift<<CYC_SHIFT);\r
5424\r
5425 if(shift <= 8)\r
5426 {\r
5427 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5428 FLAG_X = FLAG_C = src << (9-shift);\r
5429 FLAG_N = NFLAG_CLEAR;\r
5430 FLAG_Z = res;\r
5431 FLAG_V = VFLAG_CLEAR;\r
5432 return;\r
5433 }\r
5434\r
5435 *r_dst &= 0xffffff00;\r
5436 FLAG_X = XFLAG_CLEAR;\r
5437 FLAG_C = CFLAG_CLEAR;\r
5438 FLAG_N = NFLAG_CLEAR;\r
5439 FLAG_Z = ZFLAG_SET;\r
5440 FLAG_V = VFLAG_CLEAR;\r
5441 return;\r
5442 }\r
5443\r
5444 FLAG_C = CFLAG_CLEAR;\r
5445 FLAG_N = NFLAG_8(src);\r
5446 FLAG_Z = src;\r
5447 FLAG_V = VFLAG_CLEAR;\r
5448}\r
5449\r
5450\r
5451M68KMAKE_OP(lsr, 16, r, .)\r
5452{\r
5453 uint* r_dst = &DY;\r
5454 uint shift = DX & 0x3f;\r
5455 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5456 uint res = src >> shift;\r
5457\r
5458 if(shift != 0)\r
5459 {\r
5460 USE_CYCLES(shift<<CYC_SHIFT);\r
5461\r
5462 if(shift <= 16)\r
5463 {\r
5464 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5465 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5466 FLAG_N = NFLAG_CLEAR;\r
5467 FLAG_Z = res;\r
5468 FLAG_V = VFLAG_CLEAR;\r
5469 return;\r
5470 }\r
5471\r
5472 *r_dst &= 0xffff0000;\r
5473 FLAG_X = XFLAG_CLEAR;\r
5474 FLAG_C = CFLAG_CLEAR;\r
5475 FLAG_N = NFLAG_CLEAR;\r
5476 FLAG_Z = ZFLAG_SET;\r
5477 FLAG_V = VFLAG_CLEAR;\r
5478 return;\r
5479 }\r
5480\r
5481 FLAG_C = CFLAG_CLEAR;\r
5482 FLAG_N = NFLAG_16(src);\r
5483 FLAG_Z = src;\r
5484 FLAG_V = VFLAG_CLEAR;\r
5485}\r
5486\r
5487\r
5488M68KMAKE_OP(lsr, 32, r, .)\r
5489{\r
5490 uint* r_dst = &DY;\r
5491 uint shift = DX & 0x3f;\r
5492 uint src = *r_dst;\r
5493 uint res = src >> shift;\r
5494\r
5495 if(shift != 0)\r
5496 {\r
5497 USE_CYCLES(shift<<CYC_SHIFT);\r
5498\r
5499 if(shift < 32)\r
5500 {\r
5501 *r_dst = res;\r
5502 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5503 FLAG_N = NFLAG_CLEAR;\r
5504 FLAG_Z = res;\r
5505 FLAG_V = VFLAG_CLEAR;\r
5506 return;\r
5507 }\r
5508\r
5509 *r_dst = 0;\r
5510 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);\r
5511 FLAG_N = NFLAG_CLEAR;\r
5512 FLAG_Z = ZFLAG_SET;\r
5513 FLAG_V = VFLAG_CLEAR;\r
5514 return;\r
5515 }\r
5516\r
5517 FLAG_C = CFLAG_CLEAR;\r
5518 FLAG_N = NFLAG_32(src);\r
5519 FLAG_Z = src;\r
5520 FLAG_V = VFLAG_CLEAR;\r
5521}\r
5522\r
5523\r
5524M68KMAKE_OP(lsr, 16, ., .)\r
5525{\r
5526 uint ea = M68KMAKE_GET_EA_AY_16;\r
5527 uint src = m68ki_read_16(ea);\r
5528 uint res = src >> 1;\r
5529\r
5530 m68ki_write_16(ea, res);\r
5531\r
5532 FLAG_N = NFLAG_CLEAR;\r
5533 FLAG_Z = res;\r
5534 FLAG_C = FLAG_X = src << 8;\r
5535 FLAG_V = VFLAG_CLEAR;\r
5536}\r
5537\r
5538\r
5539M68KMAKE_OP(lsl, 8, s, .)\r
5540{\r
5541 uint* r_dst = &DY;\r
5542 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5543 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5544 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5545\r
5546 if(shift != 0)\r
5547 USE_CYCLES(shift<<CYC_SHIFT);\r
5548\r
5549 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5550\r
5551 FLAG_N = NFLAG_8(res);\r
5552 FLAG_Z = res;\r
5553 FLAG_X = FLAG_C = src << shift;\r
5554 FLAG_V = VFLAG_CLEAR;\r
5555}\r
5556\r
5557\r
5558M68KMAKE_OP(lsl, 16, s, .)\r
5559{\r
5560 uint* r_dst = &DY;\r
5561 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5562 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5563 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5564\r
5565 if(shift != 0)\r
5566 USE_CYCLES(shift<<CYC_SHIFT);\r
5567\r
5568 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5569\r
5570 FLAG_N = NFLAG_16(res);\r
5571 FLAG_Z = res;\r
5572 FLAG_X = FLAG_C = src >> (8-shift);\r
5573 FLAG_V = VFLAG_CLEAR;\r
5574}\r
5575\r
5576\r
5577M68KMAKE_OP(lsl, 32, s, .)\r
5578{\r
5579 uint* r_dst = &DY;\r
5580 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5581 uint src = *r_dst;\r
5582 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5583\r
5584 if(shift != 0)\r
5585 USE_CYCLES(shift<<CYC_SHIFT);\r
5586\r
5587 *r_dst = res;\r
5588\r
5589 FLAG_N = NFLAG_32(res);\r
5590 FLAG_Z = res;\r
5591 FLAG_X = FLAG_C = src >> (24-shift);\r
5592 FLAG_V = VFLAG_CLEAR;\r
5593}\r
5594\r
5595\r
5596M68KMAKE_OP(lsl, 8, r, .)\r
5597{\r
5598 uint* r_dst = &DY;\r
5599 uint shift = DX & 0x3f;\r
5600 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5601 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5602\r
5603 if(shift != 0)\r
5604 {\r
5605 USE_CYCLES(shift<<CYC_SHIFT);\r
5606\r
5607 if(shift <= 8)\r
5608 {\r
5609 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5610 FLAG_X = FLAG_C = src << shift;\r
5611 FLAG_N = NFLAG_8(res);\r
5612 FLAG_Z = res;\r
5613 FLAG_V = VFLAG_CLEAR;\r
5614 return;\r
5615 }\r
5616\r
5617 *r_dst &= 0xffffff00;\r
5618 FLAG_X = XFLAG_CLEAR;\r
5619 FLAG_C = CFLAG_CLEAR;\r
5620 FLAG_N = NFLAG_CLEAR;\r
5621 FLAG_Z = ZFLAG_SET;\r
5622 FLAG_V = VFLAG_CLEAR;\r
5623 return;\r
5624 }\r
5625\r
5626 FLAG_C = CFLAG_CLEAR;\r
5627 FLAG_N = NFLAG_8(src);\r
5628 FLAG_Z = src;\r
5629 FLAG_V = VFLAG_CLEAR;\r
5630}\r
5631\r
5632\r
5633M68KMAKE_OP(lsl, 16, r, .)\r
5634{\r
5635 uint* r_dst = &DY;\r
5636 uint shift = DX & 0x3f;\r
5637 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5638 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5639\r
5640 if(shift != 0)\r
5641 {\r
5642 USE_CYCLES(shift<<CYC_SHIFT);\r
5643\r
5644 if(shift <= 16)\r
5645 {\r
5646 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5647 FLAG_X = FLAG_C = (src << shift) >> 8;\r
5648 FLAG_N = NFLAG_16(res);\r
5649 FLAG_Z = res;\r
5650 FLAG_V = VFLAG_CLEAR;\r
5651 return;\r
5652 }\r
5653\r
5654 *r_dst &= 0xffff0000;\r
5655 FLAG_X = XFLAG_CLEAR;\r
5656 FLAG_C = CFLAG_CLEAR;\r
5657 FLAG_N = NFLAG_CLEAR;\r
5658 FLAG_Z = ZFLAG_SET;\r
5659 FLAG_V = VFLAG_CLEAR;\r
5660 return;\r
5661 }\r
5662\r
5663 FLAG_C = CFLAG_CLEAR;\r
5664 FLAG_N = NFLAG_16(src);\r
5665 FLAG_Z = src;\r
5666 FLAG_V = VFLAG_CLEAR;\r
5667}\r
5668\r
5669\r
5670M68KMAKE_OP(lsl, 32, r, .)\r
5671{\r
5672 uint* r_dst = &DY;\r
5673 uint shift = DX & 0x3f;\r
5674 uint src = *r_dst;\r
5675 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5676\r
5677 if(shift != 0)\r
5678 {\r
5679 USE_CYCLES(shift<<CYC_SHIFT);\r
5680\r
5681 if(shift < 32)\r
5682 {\r
5683 *r_dst = res;\r
5684 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
5685 FLAG_N = NFLAG_32(res);\r
5686 FLAG_Z = res;\r
5687 FLAG_V = VFLAG_CLEAR;\r
5688 return;\r
5689 }\r
5690\r
5691 *r_dst = 0;\r
5692 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
5693 FLAG_N = NFLAG_CLEAR;\r
5694 FLAG_Z = ZFLAG_SET;\r
5695 FLAG_V = VFLAG_CLEAR;\r
5696 return;\r
5697 }\r
5698\r
5699 FLAG_C = CFLAG_CLEAR;\r
5700 FLAG_N = NFLAG_32(src);\r
5701 FLAG_Z = src;\r
5702 FLAG_V = VFLAG_CLEAR;\r
5703}\r
5704\r
5705\r
5706M68KMAKE_OP(lsl, 16, ., .)\r
5707{\r
5708 uint ea = M68KMAKE_GET_EA_AY_16;\r
5709 uint src = m68ki_read_16(ea);\r
5710 uint res = MASK_OUT_ABOVE_16(src << 1);\r
5711\r
5712 m68ki_write_16(ea, res);\r
5713\r
5714 FLAG_N = NFLAG_16(res);\r
5715 FLAG_Z = res;\r
5716 FLAG_X = FLAG_C = src >> 7;\r
5717 FLAG_V = VFLAG_CLEAR;\r
5718}\r
5719\r
5720\r
5721M68KMAKE_OP(move, 8, d, d)\r
5722{\r
5723 uint res = MASK_OUT_ABOVE_8(DY);\r
5724 uint* r_dst = &DX;\r
5725\r
5726 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5727\r
5728 FLAG_N = NFLAG_8(res);\r
5729 FLAG_Z = res;\r
5730 FLAG_V = VFLAG_CLEAR;\r
5731 FLAG_C = CFLAG_CLEAR;\r
5732}\r
5733\r
5734\r
5735M68KMAKE_OP(move, 8, d, .)\r
5736{\r
5737 uint res = M68KMAKE_GET_OPER_AY_8;\r
5738 uint* r_dst = &DX;\r
5739\r
5740 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5741\r
5742 FLAG_N = NFLAG_8(res);\r
5743 FLAG_Z = res;\r
5744 FLAG_V = VFLAG_CLEAR;\r
5745 FLAG_C = CFLAG_CLEAR;\r
5746}\r
5747\r
5748\r
5749M68KMAKE_OP(move, 8, ai, d)\r
5750{\r
5751 uint res = MASK_OUT_ABOVE_8(DY);\r
5752 uint ea = EA_AX_AI_8();\r
5753\r
5754 m68ki_write_8(ea, res);\r
5755\r
5756 FLAG_N = NFLAG_8(res);\r
5757 FLAG_Z = res;\r
5758 FLAG_V = VFLAG_CLEAR;\r
5759 FLAG_C = CFLAG_CLEAR;\r
5760}\r
5761\r
5762\r
5763M68KMAKE_OP(move, 8, ai, .)\r
5764{\r
5765 uint res = M68KMAKE_GET_OPER_AY_8;\r
5766 uint ea = EA_AX_AI_8();\r
5767\r
5768 m68ki_write_8(ea, res);\r
5769\r
5770 FLAG_N = NFLAG_8(res);\r
5771 FLAG_Z = res;\r
5772 FLAG_V = VFLAG_CLEAR;\r
5773 FLAG_C = CFLAG_CLEAR;\r
5774}\r
5775\r
5776\r
5777M68KMAKE_OP(move, 8, pi7, d)\r
5778{\r
5779 uint res = MASK_OUT_ABOVE_8(DY);\r
5780 uint ea = EA_A7_PI_8();\r
5781\r
5782 m68ki_write_8(ea, res);\r
5783\r
5784 FLAG_N = NFLAG_8(res);\r
5785 FLAG_Z = res;\r
5786 FLAG_V = VFLAG_CLEAR;\r
5787 FLAG_C = CFLAG_CLEAR;\r
5788}\r
5789\r
5790\r
5791M68KMAKE_OP(move, 8, pi, d)\r
5792{\r
5793 uint res = MASK_OUT_ABOVE_8(DY);\r
5794 uint ea = EA_AX_PI_8();\r
5795\r
5796 m68ki_write_8(ea, res);\r
5797\r
5798 FLAG_N = NFLAG_8(res);\r
5799 FLAG_Z = res;\r
5800 FLAG_V = VFLAG_CLEAR;\r
5801 FLAG_C = CFLAG_CLEAR;\r
5802}\r
5803\r
5804\r
5805M68KMAKE_OP(move, 8, pi7, .)\r
5806{\r
5807 uint res = M68KMAKE_GET_OPER_AY_8;\r
5808 uint ea = EA_A7_PI_8();\r
5809\r
5810 m68ki_write_8(ea, res);\r
5811\r
5812 FLAG_N = NFLAG_8(res);\r
5813 FLAG_Z = res;\r
5814 FLAG_V = VFLAG_CLEAR;\r
5815 FLAG_C = CFLAG_CLEAR;\r
5816}\r
5817\r
5818\r
5819M68KMAKE_OP(move, 8, pi, .)\r
5820{\r
5821 uint res = M68KMAKE_GET_OPER_AY_8;\r
5822 uint ea = EA_AX_PI_8();\r
5823\r
5824 m68ki_write_8(ea, res);\r
5825\r
5826 FLAG_N = NFLAG_8(res);\r
5827 FLAG_Z = res;\r
5828 FLAG_V = VFLAG_CLEAR;\r
5829 FLAG_C = CFLAG_CLEAR;\r
5830}\r
5831\r
5832\r
5833M68KMAKE_OP(move, 8, pd7, d)\r
5834{\r
5835 uint res = MASK_OUT_ABOVE_8(DY);\r
5836 uint ea = EA_A7_PD_8();\r
5837\r
5838 m68ki_write_8(ea, res);\r
5839\r
5840 FLAG_N = NFLAG_8(res);\r
5841 FLAG_Z = res;\r
5842 FLAG_V = VFLAG_CLEAR;\r
5843 FLAG_C = CFLAG_CLEAR;\r
5844}\r
5845\r
5846\r
5847M68KMAKE_OP(move, 8, pd, d)\r
5848{\r
5849 uint res = MASK_OUT_ABOVE_8(DY);\r
5850 uint ea = EA_AX_PD_8();\r
5851\r
5852 m68ki_write_8(ea, res);\r
5853\r
5854 FLAG_N = NFLAG_8(res);\r
5855 FLAG_Z = res;\r
5856 FLAG_V = VFLAG_CLEAR;\r
5857 FLAG_C = CFLAG_CLEAR;\r
5858}\r
5859\r
5860\r
5861M68KMAKE_OP(move, 8, pd7, .)\r
5862{\r
5863 uint res = M68KMAKE_GET_OPER_AY_8;\r
5864 uint ea = EA_A7_PD_8();\r
5865\r
5866 m68ki_write_8(ea, res);\r
5867\r
5868 FLAG_N = NFLAG_8(res);\r
5869 FLAG_Z = res;\r
5870 FLAG_V = VFLAG_CLEAR;\r
5871 FLAG_C = CFLAG_CLEAR;\r
5872}\r
5873\r
5874\r
5875M68KMAKE_OP(move, 8, pd, .)\r
5876{\r
5877 uint res = M68KMAKE_GET_OPER_AY_8;\r
5878 uint ea = EA_AX_PD_8();\r
5879\r
5880 m68ki_write_8(ea, res);\r
5881\r
5882 FLAG_N = NFLAG_8(res);\r
5883 FLAG_Z = res;\r
5884 FLAG_V = VFLAG_CLEAR;\r
5885 FLAG_C = CFLAG_CLEAR;\r
5886}\r
5887\r
5888\r
5889M68KMAKE_OP(move, 8, di, d)\r
5890{\r
5891 uint res = MASK_OUT_ABOVE_8(DY);\r
5892 uint ea = EA_AX_DI_8();\r
5893\r
5894 m68ki_write_8(ea, res);\r
5895\r
5896 FLAG_N = NFLAG_8(res);\r
5897 FLAG_Z = res;\r
5898 FLAG_V = VFLAG_CLEAR;\r
5899 FLAG_C = CFLAG_CLEAR;\r
5900}\r
5901\r
5902\r
5903M68KMAKE_OP(move, 8, di, .)\r
5904{\r
5905 uint res = M68KMAKE_GET_OPER_AY_8;\r
5906 uint ea = EA_AX_DI_8();\r
5907\r
5908 m68ki_write_8(ea, res);\r
5909\r
5910 FLAG_N = NFLAG_8(res);\r
5911 FLAG_Z = res;\r
5912 FLAG_V = VFLAG_CLEAR;\r
5913 FLAG_C = CFLAG_CLEAR;\r
5914}\r
5915\r
5916\r
5917M68KMAKE_OP(move, 8, ix, d)\r
5918{\r
5919 uint res = MASK_OUT_ABOVE_8(DY);\r
5920 uint ea = EA_AX_IX_8();\r
5921\r
5922 m68ki_write_8(ea, res);\r
5923\r
5924 FLAG_N = NFLAG_8(res);\r
5925 FLAG_Z = res;\r
5926 FLAG_V = VFLAG_CLEAR;\r
5927 FLAG_C = CFLAG_CLEAR;\r
5928}\r
5929\r
5930\r
5931M68KMAKE_OP(move, 8, ix, .)\r
5932{\r
5933 uint res = M68KMAKE_GET_OPER_AY_8;\r
5934 uint ea = EA_AX_IX_8();\r
5935\r
5936 m68ki_write_8(ea, res);\r
5937\r
5938 FLAG_N = NFLAG_8(res);\r
5939 FLAG_Z = res;\r
5940 FLAG_V = VFLAG_CLEAR;\r
5941 FLAG_C = CFLAG_CLEAR;\r
5942}\r
5943\r
5944\r
5945M68KMAKE_OP(move, 8, aw, d)\r
5946{\r
5947 uint res = MASK_OUT_ABOVE_8(DY);\r
5948 uint ea = EA_AW_8();\r
5949\r
5950 m68ki_write_8(ea, res);\r
5951\r
5952 FLAG_N = NFLAG_8(res);\r
5953 FLAG_Z = res;\r
5954 FLAG_V = VFLAG_CLEAR;\r
5955 FLAG_C = CFLAG_CLEAR;\r
5956}\r
5957\r
5958\r
5959M68KMAKE_OP(move, 8, aw, .)\r
5960{\r
5961 uint res = M68KMAKE_GET_OPER_AY_8;\r
5962 uint ea = EA_AW_8();\r
5963\r
5964 m68ki_write_8(ea, res);\r
5965\r
5966 FLAG_N = NFLAG_8(res);\r
5967 FLAG_Z = res;\r
5968 FLAG_V = VFLAG_CLEAR;\r
5969 FLAG_C = CFLAG_CLEAR;\r
5970}\r
5971\r
5972\r
5973M68KMAKE_OP(move, 8, al, d)\r
5974{\r
5975 uint res = MASK_OUT_ABOVE_8(DY);\r
5976 uint ea = EA_AL_8();\r
5977\r
5978 m68ki_write_8(ea, res);\r
5979\r
5980 FLAG_N = NFLAG_8(res);\r
5981 FLAG_Z = res;\r
5982 FLAG_V = VFLAG_CLEAR;\r
5983 FLAG_C = CFLAG_CLEAR;\r
5984}\r
5985\r
5986\r
5987M68KMAKE_OP(move, 8, al, .)\r
5988{\r
5989 uint res = M68KMAKE_GET_OPER_AY_8;\r
5990 uint ea = EA_AL_8();\r
5991\r
5992 m68ki_write_8(ea, res);\r
5993\r
5994 FLAG_N = NFLAG_8(res);\r
5995 FLAG_Z = res;\r
5996 FLAG_V = VFLAG_CLEAR;\r
5997 FLAG_C = CFLAG_CLEAR;\r
5998}\r
5999\r
6000\r
6001M68KMAKE_OP(move, 16, d, d)\r
6002{\r
6003 uint res = MASK_OUT_ABOVE_16(DY);\r
6004 uint* r_dst = &DX;\r
6005\r
6006 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6007\r
6008 FLAG_N = NFLAG_16(res);\r
6009 FLAG_Z = res;\r
6010 FLAG_V = VFLAG_CLEAR;\r
6011 FLAG_C = CFLAG_CLEAR;\r
6012}\r
6013\r
6014\r
6015M68KMAKE_OP(move, 16, d, a)\r
6016{\r
6017 uint res = MASK_OUT_ABOVE_16(AY);\r
6018 uint* r_dst = &DX;\r
6019\r
6020 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6021\r
6022 FLAG_N = NFLAG_16(res);\r
6023 FLAG_Z = res;\r
6024 FLAG_V = VFLAG_CLEAR;\r
6025 FLAG_C = CFLAG_CLEAR;\r
6026}\r
6027\r
6028\r
6029M68KMAKE_OP(move, 16, d, .)\r
6030{\r
6031 uint res = M68KMAKE_GET_OPER_AY_16;\r
6032 uint* r_dst = &DX;\r
6033\r
6034 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6035\r
6036 FLAG_N = NFLAG_16(res);\r
6037 FLAG_Z = res;\r
6038 FLAG_V = VFLAG_CLEAR;\r
6039 FLAG_C = CFLAG_CLEAR;\r
6040}\r
6041\r
6042\r
6043M68KMAKE_OP(move, 16, ai, d)\r
6044{\r
6045 uint res = MASK_OUT_ABOVE_16(DY);\r
6046 uint ea = EA_AX_AI_16();\r
6047\r
6048 m68ki_write_16(ea, res);\r
6049\r
6050 FLAG_N = NFLAG_16(res);\r
6051 FLAG_Z = res;\r
6052 FLAG_V = VFLAG_CLEAR;\r
6053 FLAG_C = CFLAG_CLEAR;\r
6054}\r
6055\r
6056\r
6057M68KMAKE_OP(move, 16, ai, a)\r
6058{\r
6059 uint res = MASK_OUT_ABOVE_16(AY);\r
6060 uint ea = EA_AX_AI_16();\r
6061\r
6062 m68ki_write_16(ea, res);\r
6063\r
6064 FLAG_N = NFLAG_16(res);\r
6065 FLAG_Z = res;\r
6066 FLAG_V = VFLAG_CLEAR;\r
6067 FLAG_C = CFLAG_CLEAR;\r
6068}\r
6069\r
6070\r
6071M68KMAKE_OP(move, 16, ai, .)\r
6072{\r
6073 uint res = M68KMAKE_GET_OPER_AY_16;\r
6074 uint ea = EA_AX_AI_16();\r
6075\r
6076 m68ki_write_16(ea, res);\r
6077\r
6078 FLAG_N = NFLAG_16(res);\r
6079 FLAG_Z = res;\r
6080 FLAG_V = VFLAG_CLEAR;\r
6081 FLAG_C = CFLAG_CLEAR;\r
6082}\r
6083\r
6084\r
6085M68KMAKE_OP(move, 16, pi, d)\r
6086{\r
6087 uint res = MASK_OUT_ABOVE_16(DY);\r
6088 uint ea = EA_AX_PI_16();\r
6089\r
6090 m68ki_write_16(ea, res);\r
6091\r
6092 FLAG_N = NFLAG_16(res);\r
6093 FLAG_Z = res;\r
6094 FLAG_V = VFLAG_CLEAR;\r
6095 FLAG_C = CFLAG_CLEAR;\r
6096}\r
6097\r
6098\r
6099M68KMAKE_OP(move, 16, pi, a)\r
6100{\r
6101 uint res = MASK_OUT_ABOVE_16(AY);\r
6102 uint ea = EA_AX_PI_16();\r
6103\r
6104 m68ki_write_16(ea, res);\r
6105\r
6106 FLAG_N = NFLAG_16(res);\r
6107 FLAG_Z = res;\r
6108 FLAG_V = VFLAG_CLEAR;\r
6109 FLAG_C = CFLAG_CLEAR;\r
6110}\r
6111\r
6112\r
6113M68KMAKE_OP(move, 16, pi, .)\r
6114{\r
6115 uint res = M68KMAKE_GET_OPER_AY_16;\r
6116 uint ea = EA_AX_PI_16();\r
6117\r
6118 m68ki_write_16(ea, res);\r
6119\r
6120 FLAG_N = NFLAG_16(res);\r
6121 FLAG_Z = res;\r
6122 FLAG_V = VFLAG_CLEAR;\r
6123 FLAG_C = CFLAG_CLEAR;\r
6124}\r
6125\r
6126\r
6127M68KMAKE_OP(move, 16, pd, d)\r
6128{\r
6129 uint res = MASK_OUT_ABOVE_16(DY);\r
6130 uint ea = EA_AX_PD_16();\r
6131\r
6132 m68ki_write_16(ea, res);\r
6133\r
6134 FLAG_N = NFLAG_16(res);\r
6135 FLAG_Z = res;\r
6136 FLAG_V = VFLAG_CLEAR;\r
6137 FLAG_C = CFLAG_CLEAR;\r
6138}\r
6139\r
6140\r
6141M68KMAKE_OP(move, 16, pd, a)\r
6142{\r
6143 uint res = MASK_OUT_ABOVE_16(AY);\r
6144 uint ea = EA_AX_PD_16();\r
6145\r
6146 m68ki_write_16(ea, res);\r
6147\r
6148 FLAG_N = NFLAG_16(res);\r
6149 FLAG_Z = res;\r
6150 FLAG_V = VFLAG_CLEAR;\r
6151 FLAG_C = CFLAG_CLEAR;\r
6152}\r
6153\r
6154\r
6155M68KMAKE_OP(move, 16, pd, .)\r
6156{\r
6157 uint res = M68KMAKE_GET_OPER_AY_16;\r
6158 uint ea = EA_AX_PD_16();\r
6159\r
6160 m68ki_write_16(ea, res);\r
6161\r
6162 FLAG_N = NFLAG_16(res);\r
6163 FLAG_Z = res;\r
6164 FLAG_V = VFLAG_CLEAR;\r
6165 FLAG_C = CFLAG_CLEAR;\r
6166}\r
6167\r
6168\r
6169M68KMAKE_OP(move, 16, di, d)\r
6170{\r
6171 uint res = MASK_OUT_ABOVE_16(DY);\r
6172 uint ea = EA_AX_DI_16();\r
6173\r
6174 m68ki_write_16(ea, res);\r
6175\r
6176 FLAG_N = NFLAG_16(res);\r
6177 FLAG_Z = res;\r
6178 FLAG_V = VFLAG_CLEAR;\r
6179 FLAG_C = CFLAG_CLEAR;\r
6180}\r
6181\r
6182\r
6183M68KMAKE_OP(move, 16, di, a)\r
6184{\r
6185 uint res = MASK_OUT_ABOVE_16(AY);\r
6186 uint ea = EA_AX_DI_16();\r
6187\r
6188 m68ki_write_16(ea, res);\r
6189\r
6190 FLAG_N = NFLAG_16(res);\r
6191 FLAG_Z = res;\r
6192 FLAG_V = VFLAG_CLEAR;\r
6193 FLAG_C = CFLAG_CLEAR;\r
6194}\r
6195\r
6196\r
6197M68KMAKE_OP(move, 16, di, .)\r
6198{\r
6199 uint res = M68KMAKE_GET_OPER_AY_16;\r
6200 uint ea = EA_AX_DI_16();\r
6201\r
6202 m68ki_write_16(ea, res);\r
6203\r
6204 FLAG_N = NFLAG_16(res);\r
6205 FLAG_Z = res;\r
6206 FLAG_V = VFLAG_CLEAR;\r
6207 FLAG_C = CFLAG_CLEAR;\r
6208}\r
6209\r
6210\r
6211M68KMAKE_OP(move, 16, ix, d)\r
6212{\r
6213 uint res = MASK_OUT_ABOVE_16(DY);\r
6214 uint ea = EA_AX_IX_16();\r
6215\r
6216 m68ki_write_16(ea, res);\r
6217\r
6218 FLAG_N = NFLAG_16(res);\r
6219 FLAG_Z = res;\r
6220 FLAG_V = VFLAG_CLEAR;\r
6221 FLAG_C = CFLAG_CLEAR;\r
6222}\r
6223\r
6224\r
6225M68KMAKE_OP(move, 16, ix, a)\r
6226{\r
6227 uint res = MASK_OUT_ABOVE_16(AY);\r
6228 uint ea = EA_AX_IX_16();\r
6229\r
6230 m68ki_write_16(ea, res);\r
6231\r
6232 FLAG_N = NFLAG_16(res);\r
6233 FLAG_Z = res;\r
6234 FLAG_V = VFLAG_CLEAR;\r
6235 FLAG_C = CFLAG_CLEAR;\r
6236}\r
6237\r
6238\r
6239M68KMAKE_OP(move, 16, ix, .)\r
6240{\r
6241 uint res = M68KMAKE_GET_OPER_AY_16;\r
6242 uint ea = EA_AX_IX_16();\r
6243\r
6244 m68ki_write_16(ea, res);\r
6245\r
6246 FLAG_N = NFLAG_16(res);\r
6247 FLAG_Z = res;\r
6248 FLAG_V = VFLAG_CLEAR;\r
6249 FLAG_C = CFLAG_CLEAR;\r
6250}\r
6251\r
6252\r
6253M68KMAKE_OP(move, 16, aw, d)\r
6254{\r
6255 uint res = MASK_OUT_ABOVE_16(DY);\r
6256 uint ea = EA_AW_16();\r
6257\r
6258 m68ki_write_16(ea, res);\r
6259\r
6260 FLAG_N = NFLAG_16(res);\r
6261 FLAG_Z = res;\r
6262 FLAG_V = VFLAG_CLEAR;\r
6263 FLAG_C = CFLAG_CLEAR;\r
6264}\r
6265\r
6266\r
6267M68KMAKE_OP(move, 16, aw, a)\r
6268{\r
6269 uint res = MASK_OUT_ABOVE_16(AY);\r
6270 uint ea = EA_AW_16();\r
6271\r
6272 m68ki_write_16(ea, res);\r
6273\r
6274 FLAG_N = NFLAG_16(res);\r
6275 FLAG_Z = res;\r
6276 FLAG_V = VFLAG_CLEAR;\r
6277 FLAG_C = CFLAG_CLEAR;\r
6278}\r
6279\r
6280\r
6281M68KMAKE_OP(move, 16, aw, .)\r
6282{\r
6283 uint res = M68KMAKE_GET_OPER_AY_16;\r
6284 uint ea = EA_AW_16();\r
6285\r
6286 m68ki_write_16(ea, res);\r
6287\r
6288 FLAG_N = NFLAG_16(res);\r
6289 FLAG_Z = res;\r
6290 FLAG_V = VFLAG_CLEAR;\r
6291 FLAG_C = CFLAG_CLEAR;\r
6292}\r
6293\r
6294\r
6295M68KMAKE_OP(move, 16, al, d)\r
6296{\r
6297 uint res = MASK_OUT_ABOVE_16(DY);\r
6298 uint ea = EA_AL_16();\r
6299\r
6300 m68ki_write_16(ea, res);\r
6301\r
6302 FLAG_N = NFLAG_16(res);\r
6303 FLAG_Z = res;\r
6304 FLAG_V = VFLAG_CLEAR;\r
6305 FLAG_C = CFLAG_CLEAR;\r
6306}\r
6307\r
6308\r
6309M68KMAKE_OP(move, 16, al, a)\r
6310{\r
6311 uint res = MASK_OUT_ABOVE_16(AY);\r
6312 uint ea = EA_AL_16();\r
6313\r
6314 m68ki_write_16(ea, res);\r
6315\r
6316 FLAG_N = NFLAG_16(res);\r
6317 FLAG_Z = res;\r
6318 FLAG_V = VFLAG_CLEAR;\r
6319 FLAG_C = CFLAG_CLEAR;\r
6320}\r
6321\r
6322\r
6323M68KMAKE_OP(move, 16, al, .)\r
6324{\r
6325 uint res = M68KMAKE_GET_OPER_AY_16;\r
6326 uint ea = EA_AL_16();\r
6327\r
6328 m68ki_write_16(ea, res);\r
6329\r
6330 FLAG_N = NFLAG_16(res);\r
6331 FLAG_Z = res;\r
6332 FLAG_V = VFLAG_CLEAR;\r
6333 FLAG_C = CFLAG_CLEAR;\r
6334}\r
6335\r
6336\r
6337M68KMAKE_OP(move, 32, d, d)\r
6338{\r
6339 uint res = DY;\r
6340 uint* r_dst = &DX;\r
6341\r
6342 *r_dst = res;\r
6343\r
6344 FLAG_N = NFLAG_32(res);\r
6345 FLAG_Z = res;\r
6346 FLAG_V = VFLAG_CLEAR;\r
6347 FLAG_C = CFLAG_CLEAR;\r
6348}\r
6349\r
6350\r
6351M68KMAKE_OP(move, 32, d, a)\r
6352{\r
6353 uint res = AY;\r
6354 uint* r_dst = &DX;\r
6355\r
6356 *r_dst = res;\r
6357\r
6358 FLAG_N = NFLAG_32(res);\r
6359 FLAG_Z = res;\r
6360 FLAG_V = VFLAG_CLEAR;\r
6361 FLAG_C = CFLAG_CLEAR;\r
6362}\r
6363\r
6364\r
6365M68KMAKE_OP(move, 32, d, .)\r
6366{\r
6367 uint res = M68KMAKE_GET_OPER_AY_32;\r
6368 uint* r_dst = &DX;\r
6369\r
6370 *r_dst = res;\r
6371\r
6372 FLAG_N = NFLAG_32(res);\r
6373 FLAG_Z = res;\r
6374 FLAG_V = VFLAG_CLEAR;\r
6375 FLAG_C = CFLAG_CLEAR;\r
6376}\r
6377\r
6378\r
6379M68KMAKE_OP(move, 32, ai, d)\r
6380{\r
6381 uint res = DY;\r
6382 uint ea = EA_AX_AI_32();\r
6383\r
6384 m68ki_write_32(ea, res);\r
6385\r
6386 FLAG_N = NFLAG_32(res);\r
6387 FLAG_Z = res;\r
6388 FLAG_V = VFLAG_CLEAR;\r
6389 FLAG_C = CFLAG_CLEAR;\r
6390}\r
6391\r
6392\r
6393M68KMAKE_OP(move, 32, ai, a)\r
6394{\r
6395 uint res = AY;\r
6396 uint ea = EA_AX_AI_32();\r
6397\r
6398 m68ki_write_32(ea, res);\r
6399\r
6400 FLAG_N = NFLAG_32(res);\r
6401 FLAG_Z = res;\r
6402 FLAG_V = VFLAG_CLEAR;\r
6403 FLAG_C = CFLAG_CLEAR;\r
6404}\r
6405\r
6406\r
6407M68KMAKE_OP(move, 32, ai, .)\r
6408{\r
6409 uint res = M68KMAKE_GET_OPER_AY_32;\r
6410 uint ea = EA_AX_AI_32();\r
6411\r
6412 m68ki_write_32(ea, res);\r
6413\r
6414 FLAG_N = NFLAG_32(res);\r
6415 FLAG_Z = res;\r
6416 FLAG_V = VFLAG_CLEAR;\r
6417 FLAG_C = CFLAG_CLEAR;\r
6418}\r
6419\r
6420\r
6421M68KMAKE_OP(move, 32, pi, d)\r
6422{\r
6423 uint res = DY;\r
6424 uint ea = EA_AX_PI_32();\r
6425\r
6426 m68ki_write_32(ea, res);\r
6427\r
6428 FLAG_N = NFLAG_32(res);\r
6429 FLAG_Z = res;\r
6430 FLAG_V = VFLAG_CLEAR;\r
6431 FLAG_C = CFLAG_CLEAR;\r
6432}\r
6433\r
6434\r
6435M68KMAKE_OP(move, 32, pi, a)\r
6436{\r
6437 uint res = AY;\r
6438 uint ea = EA_AX_PI_32();\r
6439\r
6440 m68ki_write_32(ea, res);\r
6441\r
6442 FLAG_N = NFLAG_32(res);\r
6443 FLAG_Z = res;\r
6444 FLAG_V = VFLAG_CLEAR;\r
6445 FLAG_C = CFLAG_CLEAR;\r
6446}\r
6447\r
6448\r
6449M68KMAKE_OP(move, 32, pi, .)\r
6450{\r
6451 uint res = M68KMAKE_GET_OPER_AY_32;\r
6452 uint ea = EA_AX_PI_32();\r
6453\r
6454 m68ki_write_32(ea, res);\r
6455\r
6456 FLAG_N = NFLAG_32(res);\r
6457 FLAG_Z = res;\r
6458 FLAG_V = VFLAG_CLEAR;\r
6459 FLAG_C = CFLAG_CLEAR;\r
6460}\r
6461\r
6462\r
6463M68KMAKE_OP(move, 32, pd, d)\r
6464{\r
6465 uint res = DY;\r
6466 uint ea = EA_AX_PD_32();\r
6467\r
c6a4c892 6468 m68ki_write_16(ea+2, res & 0xFFFF );\r
6469 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6470\r
6471 FLAG_N = NFLAG_32(res);\r
6472 FLAG_Z = res;\r
6473 FLAG_V = VFLAG_CLEAR;\r
6474 FLAG_C = CFLAG_CLEAR;\r
6475}\r
6476\r
6477\r
6478M68KMAKE_OP(move, 32, pd, a)\r
6479{\r
6480 uint res = AY;\r
6481 uint ea = EA_AX_PD_32();\r
6482\r
c6a4c892 6483 m68ki_write_16(ea+2, res & 0xFFFF );\r
6484 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6485\r
6486 FLAG_N = NFLAG_32(res);\r
6487 FLAG_Z = res;\r
6488 FLAG_V = VFLAG_CLEAR;\r
6489 FLAG_C = CFLAG_CLEAR;\r
6490}\r
6491\r
6492\r
6493M68KMAKE_OP(move, 32, pd, .)\r
6494{\r
6495 uint res = M68KMAKE_GET_OPER_AY_32;\r
6496 uint ea = EA_AX_PD_32();\r
6497\r
c6a4c892 6498 m68ki_write_16(ea+2, res & 0xFFFF );\r
6499 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6500\r
6501 FLAG_N = NFLAG_32(res);\r
6502 FLAG_Z = res;\r
6503 FLAG_V = VFLAG_CLEAR;\r
6504 FLAG_C = CFLAG_CLEAR;\r
6505}\r
6506\r
6507\r
6508M68KMAKE_OP(move, 32, di, d)\r
6509{\r
6510 uint res = DY;\r
6511 uint ea = EA_AX_DI_32();\r
6512\r
6513 m68ki_write_32(ea, res);\r
6514\r
6515 FLAG_N = NFLAG_32(res);\r
6516 FLAG_Z = res;\r
6517 FLAG_V = VFLAG_CLEAR;\r
6518 FLAG_C = CFLAG_CLEAR;\r
6519}\r
6520\r
6521\r
6522M68KMAKE_OP(move, 32, di, a)\r
6523{\r
6524 uint res = AY;\r
6525 uint ea = EA_AX_DI_32();\r
6526\r
6527 m68ki_write_32(ea, res);\r
6528\r
6529 FLAG_N = NFLAG_32(res);\r
6530 FLAG_Z = res;\r
6531 FLAG_V = VFLAG_CLEAR;\r
6532 FLAG_C = CFLAG_CLEAR;\r
6533}\r
6534\r
6535\r
6536M68KMAKE_OP(move, 32, di, .)\r
6537{\r
6538 uint res = M68KMAKE_GET_OPER_AY_32;\r
6539 uint ea = EA_AX_DI_32();\r
6540\r
6541 m68ki_write_32(ea, res);\r
6542\r
6543 FLAG_N = NFLAG_32(res);\r
6544 FLAG_Z = res;\r
6545 FLAG_V = VFLAG_CLEAR;\r
6546 FLAG_C = CFLAG_CLEAR;\r
6547}\r
6548\r
6549\r
6550M68KMAKE_OP(move, 32, ix, d)\r
6551{\r
6552 uint res = DY;\r
6553 uint ea = EA_AX_IX_32();\r
6554\r
6555 m68ki_write_32(ea, res);\r
6556\r
6557 FLAG_N = NFLAG_32(res);\r
6558 FLAG_Z = res;\r
6559 FLAG_V = VFLAG_CLEAR;\r
6560 FLAG_C = CFLAG_CLEAR;\r
6561}\r
6562\r
6563\r
6564M68KMAKE_OP(move, 32, ix, a)\r
6565{\r
6566 uint res = AY;\r
6567 uint ea = EA_AX_IX_32();\r
6568\r
6569 m68ki_write_32(ea, res);\r
6570\r
6571 FLAG_N = NFLAG_32(res);\r
6572 FLAG_Z = res;\r
6573 FLAG_V = VFLAG_CLEAR;\r
6574 FLAG_C = CFLAG_CLEAR;\r
6575}\r
6576\r
6577\r
6578M68KMAKE_OP(move, 32, ix, .)\r
6579{\r
6580 uint res = M68KMAKE_GET_OPER_AY_32;\r
6581 uint ea = EA_AX_IX_32();\r
6582\r
6583 m68ki_write_32(ea, res);\r
6584\r
6585 FLAG_N = NFLAG_32(res);\r
6586 FLAG_Z = res;\r
6587 FLAG_V = VFLAG_CLEAR;\r
6588 FLAG_C = CFLAG_CLEAR;\r
6589}\r
6590\r
6591\r
6592M68KMAKE_OP(move, 32, aw, d)\r
6593{\r
6594 uint res = DY;\r
6595 uint ea = EA_AW_32();\r
6596\r
6597 m68ki_write_32(ea, res);\r
6598\r
6599 FLAG_N = NFLAG_32(res);\r
6600 FLAG_Z = res;\r
6601 FLAG_V = VFLAG_CLEAR;\r
6602 FLAG_C = CFLAG_CLEAR;\r
6603}\r
6604\r
6605\r
6606M68KMAKE_OP(move, 32, aw, a)\r
6607{\r
6608 uint res = AY;\r
6609 uint ea = EA_AW_32();\r
6610\r
6611 m68ki_write_32(ea, res);\r
6612\r
6613 FLAG_N = NFLAG_32(res);\r
6614 FLAG_Z = res;\r
6615 FLAG_V = VFLAG_CLEAR;\r
6616 FLAG_C = CFLAG_CLEAR;\r
6617}\r
6618\r
6619\r
6620M68KMAKE_OP(move, 32, aw, .)\r
6621{\r
6622 uint res = M68KMAKE_GET_OPER_AY_32;\r
6623 uint ea = EA_AW_32();\r
6624\r
6625 m68ki_write_32(ea, res);\r
6626\r
6627 FLAG_N = NFLAG_32(res);\r
6628 FLAG_Z = res;\r
6629 FLAG_V = VFLAG_CLEAR;\r
6630 FLAG_C = CFLAG_CLEAR;\r
6631}\r
6632\r
6633\r
6634M68KMAKE_OP(move, 32, al, d)\r
6635{\r
6636 uint res = DY;\r
6637 uint ea = EA_AL_32();\r
6638\r
6639 m68ki_write_32(ea, res);\r
6640\r
6641 FLAG_N = NFLAG_32(res);\r
6642 FLAG_Z = res;\r
6643 FLAG_V = VFLAG_CLEAR;\r
6644 FLAG_C = CFLAG_CLEAR;\r
6645}\r
6646\r
6647\r
6648M68KMAKE_OP(move, 32, al, a)\r
6649{\r
6650 uint res = AY;\r
6651 uint ea = EA_AL_32();\r
6652\r
6653 m68ki_write_32(ea, res);\r
6654\r
6655 FLAG_N = NFLAG_32(res);\r
6656 FLAG_Z = res;\r
6657 FLAG_V = VFLAG_CLEAR;\r
6658 FLAG_C = CFLAG_CLEAR;\r
6659}\r
6660\r
6661\r
6662M68KMAKE_OP(move, 32, al, .)\r
6663{\r
6664 uint res = M68KMAKE_GET_OPER_AY_32;\r
6665 uint ea = EA_AL_32();\r
6666\r
6667 m68ki_write_32(ea, res);\r
6668\r
6669 FLAG_N = NFLAG_32(res);\r
6670 FLAG_Z = res;\r
6671 FLAG_V = VFLAG_CLEAR;\r
6672 FLAG_C = CFLAG_CLEAR;\r
6673}\r
6674\r
6675\r
6676M68KMAKE_OP(movea, 16, ., d)\r
6677{\r
6678 AX = MAKE_INT_16(DY);\r
6679}\r
6680\r
6681\r
6682M68KMAKE_OP(movea, 16, ., a)\r
6683{\r
6684 AX = MAKE_INT_16(AY);\r
6685}\r
6686\r
6687\r
6688M68KMAKE_OP(movea, 16, ., .)\r
6689{\r
6690 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
6691}\r
6692\r
6693\r
6694M68KMAKE_OP(movea, 32, ., d)\r
6695{\r
6696 AX = DY;\r
6697}\r
6698\r
6699\r
6700M68KMAKE_OP(movea, 32, ., a)\r
6701{\r
6702 AX = AY;\r
6703}\r
6704\r
6705\r
6706M68KMAKE_OP(movea, 32, ., .)\r
6707{\r
6708 AX = M68KMAKE_GET_OPER_AY_32;\r
6709}\r
6710\r
6711\r
6712M68KMAKE_OP(move, 16, frc, d)\r
6713{\r
6714 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6715 {\r
6716 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();\r
6717 return;\r
6718 }\r
6719 m68ki_exception_illegal();\r
6720}\r
6721\r
6722\r
6723M68KMAKE_OP(move, 16, frc, .)\r
6724{\r
6725 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6726 {\r
6727 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());\r
6728 return;\r
6729 }\r
6730 m68ki_exception_illegal();\r
6731}\r
6732\r
6733\r
6734M68KMAKE_OP(move, 16, toc, d)\r
6735{\r
6736 m68ki_set_ccr(DY);\r
6737}\r
6738\r
6739\r
6740M68KMAKE_OP(move, 16, toc, .)\r
6741{\r
6742 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);\r
6743}\r
6744\r
6745\r
6746M68KMAKE_OP(move, 16, frs, d)\r
6747{\r
6748 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6749 {\r
6750 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();\r
6751 return;\r
6752 }\r
6753 m68ki_exception_privilege_violation();\r
6754}\r
6755\r
6756\r
6757M68KMAKE_OP(move, 16, frs, .)\r
6758{\r
6759 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6760 {\r
6761 uint ea = M68KMAKE_GET_EA_AY_16;\r
6762 m68ki_write_16(ea, m68ki_get_sr());\r
6763 return;\r
6764 }\r
6765 m68ki_exception_privilege_violation();\r
6766}\r
6767\r
6768\r
6769M68KMAKE_OP(move, 16, tos, d)\r
6770{\r
6771 if(FLAG_S)\r
6772 {\r
6773 m68ki_set_sr(DY);\r
6774 return;\r
6775 }\r
6776 m68ki_exception_privilege_violation();\r
6777}\r
6778\r
6779\r
6780M68KMAKE_OP(move, 16, tos, .)\r
6781{\r
6782 if(FLAG_S)\r
6783 {\r
6784 uint new_sr = M68KMAKE_GET_OPER_AY_16;\r
6785 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6786 m68ki_set_sr(new_sr);\r
6787 return;\r
6788 }\r
6789 m68ki_exception_privilege_violation();\r
6790}\r
6791\r
6792\r
6793M68KMAKE_OP(move, 32, fru, .)\r
6794{\r
6795 if(FLAG_S)\r
6796 {\r
6797 AY = REG_USP;\r
6798 return;\r
6799 }\r
6800 m68ki_exception_privilege_violation();\r
6801}\r
6802\r
6803\r
6804M68KMAKE_OP(move, 32, tou, .)\r
6805{\r
6806 if(FLAG_S)\r
6807 {\r
6808 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6809 REG_USP = AY;\r
6810 return;\r
6811 }\r
6812 m68ki_exception_privilege_violation();\r
6813}\r
6814\r
6815\r
6816M68KMAKE_OP(movec, 32, cr, .)\r
6817{\r
6818 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6819 {\r
6820 if(FLAG_S)\r
6821 {\r
6822 uint word2 = OPER_I_16();\r
6823\r
6824 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6825 switch (word2 & 0xfff)\r
6826 {\r
6827 case 0x000: /* SFC */\r
6828 REG_DA[(word2 >> 12) & 15] = REG_SFC;\r
6829 return;\r
6830 case 0x001: /* DFC */\r
6831 REG_DA[(word2 >> 12) & 15] = REG_DFC;\r
6832 return;\r
6833 case 0x002: /* CACR */\r
6834 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6835 {\r
6836 REG_DA[(word2 >> 12) & 15] = REG_CACR;\r
6837 return;\r
6838 }\r
6839 return;\r
6840 case 0x800: /* USP */\r
6841 REG_DA[(word2 >> 12) & 15] = REG_USP;\r
6842 return;\r
6843 case 0x801: /* VBR */\r
6844 REG_DA[(word2 >> 12) & 15] = REG_VBR;\r
6845 return;\r
6846 case 0x802: /* CAAR */\r
6847 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6848 {\r
6849 REG_DA[(word2 >> 12) & 15] = REG_CAAR;\r
6850 return;\r
6851 }\r
6852 m68ki_exception_illegal();\r
6853 break;\r
6854 case 0x803: /* MSP */\r
6855 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6856 {\r
6857 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;\r
6858 return;\r
6859 }\r
6860 m68ki_exception_illegal();\r
6861 return;\r
6862 case 0x804: /* ISP */\r
6863 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6864 {\r
6865 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;\r
6866 return;\r
6867 }\r
6868 m68ki_exception_illegal();\r
6869 return;\r
6870 case 0x003: /* TC */\r
6871 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6872 {\r
6873 /* TODO */\r
6874 return;\r
6875 }\r
6876 m68ki_exception_illegal();\r
6877 return;\r
6878 case 0x004: /* ITT0 */\r
6879 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6880 {\r
6881 /* TODO */\r
6882 return;\r
6883 }\r
6884 m68ki_exception_illegal();\r
6885 return;\r
6886 case 0x005: /* ITT1 */\r
6887 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6888 {\r
6889 /* TODO */\r
6890 return;\r
6891 }\r
6892 m68ki_exception_illegal();\r
6893 return;\r
6894 case 0x006: /* DTT0 */\r
6895 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6896 {\r
6897 /* TODO */\r
6898 return;\r
6899 }\r
6900 m68ki_exception_illegal();\r
6901 return;\r
6902 case 0x007: /* DTT1 */\r
6903 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6904 {\r
6905 /* TODO */\r
6906 return;\r
6907 }\r
6908 m68ki_exception_illegal();\r
6909 return;\r
6910 case 0x805: /* MMUSR */\r
6911 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6912 {\r
6913 /* TODO */\r
6914 return;\r
6915 }\r
6916 m68ki_exception_illegal();\r
6917 return;\r
6918 case 0x806: /* URP */\r
6919 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6920 {\r
6921 /* TODO */\r
6922 return;\r
6923 }\r
6924 m68ki_exception_illegal();\r
6925 return;\r
6926 case 0x807: /* SRP */\r
6927 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6928 {\r
6929 /* TODO */\r
6930 return;\r
6931 }\r
6932 m68ki_exception_illegal();\r
6933 return;\r
6934 default:\r
6935 m68ki_exception_illegal();\r
6936 return;\r
6937 }\r
6938 }\r
6939 m68ki_exception_privilege_violation();\r
6940 return;\r
6941 }\r
6942 m68ki_exception_illegal();\r
6943}\r
6944\r
6945\r
6946M68KMAKE_OP(movec, 32, rc, .)\r
6947{\r
6948 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6949 {\r
6950 if(FLAG_S)\r
6951 {\r
6952 uint word2 = OPER_I_16();\r
6953\r
6954 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6955 switch (word2 & 0xfff)\r
6956 {\r
6957 case 0x000: /* SFC */\r
6958 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;\r
6959 return;\r
6960 case 0x001: /* DFC */\r
6961 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;\r
6962 return;\r
6963 case 0x002: /* CACR */\r
6964 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6965 {\r
c6a4c892 6966 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6967 {\r
6968 REG_CACR = REG_DA[(word2 >> 12) & 15];\r
6969 }\r
6970 else\r
6971 {\r
6972 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */\r
6973 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;\r
6974 }\r
cc68a136 6975 return;\r
6976 }\r
6977 m68ki_exception_illegal();\r
6978 return;\r
6979 case 0x800: /* USP */\r
6980 REG_USP = REG_DA[(word2 >> 12) & 15];\r
6981 return;\r
6982 case 0x801: /* VBR */\r
6983 REG_VBR = REG_DA[(word2 >> 12) & 15];\r
6984 return;\r
6985 case 0x802: /* CAAR */\r
6986 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6987 {\r
6988 REG_CAAR = REG_DA[(word2 >> 12) & 15];\r
6989 return;\r
6990 }\r
6991 m68ki_exception_illegal();\r
6992 return;\r
6993 case 0x803: /* MSP */\r
6994 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6995 {\r
6996 /* we are in supervisor mode so just check for M flag */\r
6997 if(!FLAG_M)\r
6998 {\r
6999 REG_MSP = REG_DA[(word2 >> 12) & 15];\r
7000 return;\r
7001 }\r
7002 REG_SP = REG_DA[(word2 >> 12) & 15];\r
7003 return;\r
7004 }\r
7005 m68ki_exception_illegal();\r
7006 return;\r
7007 case 0x804: /* ISP */\r
7008 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7009 {\r
7010 if(!FLAG_M)\r
7011 {\r
7012 REG_SP = REG_DA[(word2 >> 12) & 15];\r
7013 return;\r
7014 }\r
7015 REG_ISP = REG_DA[(word2 >> 12) & 15];\r
7016 return;\r
7017 }\r
7018 m68ki_exception_illegal();\r
7019 return;\r
7020 case 0x003: /* TC */\r
7021 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7022 {\r
7023 /* TODO */\r
7024 return;\r
7025 }\r
7026 m68ki_exception_illegal();\r
7027 return;\r
7028 case 0x004: /* ITT0 */\r
7029 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7030 {\r
7031 /* TODO */\r
7032 return;\r
7033 }\r
7034 m68ki_exception_illegal();\r
7035 return;\r
7036 case 0x005: /* ITT1 */\r
7037 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7038 {\r
7039 /* TODO */\r
7040 return;\r
7041 }\r
7042 m68ki_exception_illegal();\r
7043 return;\r
7044 case 0x006: /* DTT0 */\r
7045 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7046 {\r
7047 /* TODO */\r
7048 return;\r
7049 }\r
7050 m68ki_exception_illegal();\r
7051 return;\r
7052 case 0x007: /* DTT1 */\r
7053 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7054 {\r
7055 /* TODO */\r
7056 return;\r
7057 }\r
7058 m68ki_exception_illegal();\r
7059 return;\r
7060 case 0x805: /* MMUSR */\r
7061 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7062 {\r
7063 /* TODO */\r
7064 return;\r
7065 }\r
7066 m68ki_exception_illegal();\r
7067 return;\r
7068 case 0x806: /* URP */\r
7069 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7070 {\r
7071 /* TODO */\r
7072 return;\r
7073 }\r
7074 m68ki_exception_illegal();\r
7075 return;\r
7076 case 0x807: /* SRP */\r
7077 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7078 {\r
7079 /* TODO */\r
7080 return;\r
7081 }\r
7082 m68ki_exception_illegal();\r
7083 return;\r
7084 default:\r
7085 m68ki_exception_illegal();\r
7086 return;\r
7087 }\r
7088 }\r
7089 m68ki_exception_privilege_violation();\r
7090 return;\r
7091 }\r
7092 m68ki_exception_illegal();\r
7093}\r
7094\r
7095\r
7096M68KMAKE_OP(movem, 16, re, pd)\r
7097{\r
7098 uint i = 0;\r
7099 uint register_list = OPER_I_16();\r
7100 uint ea = AY;\r
7101 uint count = 0;\r
7102\r
7103 for(; i < 16; i++)\r
7104 if(register_list & (1 << i))\r
7105 {\r
7106 ea -= 2;\r
7107 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));\r
7108 count++;\r
7109 }\r
7110 AY = ea;\r
7111\r
7112 USE_CYCLES(count<<CYC_MOVEM_W);\r
7113}\r
7114\r
7115\r
7116M68KMAKE_OP(movem, 16, re, .)\r
7117{\r
7118 uint i = 0;\r
7119 uint register_list = OPER_I_16();\r
7120 uint ea = M68KMAKE_GET_EA_AY_16;\r
7121 uint count = 0;\r
7122\r
7123 for(; i < 16; i++)\r
7124 if(register_list & (1 << i))\r
7125 {\r
7126 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));\r
7127 ea += 2;\r
7128 count++;\r
7129 }\r
7130\r
7131 USE_CYCLES(count<<CYC_MOVEM_W);\r
7132}\r
7133\r
7134\r
7135M68KMAKE_OP(movem, 32, re, pd)\r
7136{\r
7137 uint i = 0;\r
7138 uint register_list = OPER_I_16();\r
7139 uint ea = AY;\r
7140 uint count = 0;\r
7141\r
7142 for(; i < 16; i++)\r
7143 if(register_list & (1 << i))\r
7144 {\r
7145 ea -= 4;\r
e28a980f 7146#if 0\r
a5ccbfba 7147 m68ki_write_32(ea, REG_DA[15-i] ); // notaz Cyclone hack\r
e28a980f 7148#else\r
7149 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );\r
7150 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );\r
7151#endif\r
cc68a136 7152 count++;\r
7153 }\r
7154 AY = ea;\r
7155\r
7156 USE_CYCLES(count<<CYC_MOVEM_L);\r
7157}\r
7158\r
7159\r
7160M68KMAKE_OP(movem, 32, re, .)\r
7161{\r
7162 uint i = 0;\r
7163 uint register_list = OPER_I_16();\r
7164 uint ea = M68KMAKE_GET_EA_AY_32;\r
7165 uint count = 0;\r
7166\r
7167 for(; i < 16; i++)\r
7168 if(register_list & (1 << i))\r
7169 {\r
7170 m68ki_write_32(ea, REG_DA[i]);\r
7171 ea += 4;\r
7172 count++;\r
7173 }\r
7174\r
7175 USE_CYCLES(count<<CYC_MOVEM_L);\r
7176}\r
7177\r
7178\r
7179M68KMAKE_OP(movem, 16, er, pi)\r
7180{\r
7181 uint i = 0;\r
7182 uint register_list = OPER_I_16();\r
7183 uint ea = AY;\r
7184 uint count = 0;\r
7185\r
7186 for(; i < 16; i++)\r
7187 if(register_list & (1 << i))\r
7188 {\r
7189 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7190 ea += 2;\r
7191 count++;\r
7192 }\r
7193 AY = ea;\r
7194\r
7195 USE_CYCLES(count<<CYC_MOVEM_W);\r
7196}\r
7197\r
7198\r
7199M68KMAKE_OP(movem, 16, er, pcdi)\r
7200{\r
7201 uint i = 0;\r
7202 uint register_list = OPER_I_16();\r
7203 uint ea = EA_PCDI_16();\r
7204 uint count = 0;\r
7205\r
7206 for(; i < 16; i++)\r
7207 if(register_list & (1 << i))\r
7208 {\r
7209 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7210 ea += 2;\r
7211 count++;\r
7212 }\r
7213\r
7214 USE_CYCLES(count<<CYC_MOVEM_W);\r
7215}\r
7216\r
7217\r
7218M68KMAKE_OP(movem, 16, er, pcix)\r
7219{\r
7220 uint i = 0;\r
7221 uint register_list = OPER_I_16();\r
7222 uint ea = EA_PCIX_16();\r
7223 uint count = 0;\r
7224\r
7225 for(; i < 16; i++)\r
7226 if(register_list & (1 << i))\r
7227 {\r
7228 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7229 ea += 2;\r
7230 count++;\r
7231 }\r
7232\r
7233 USE_CYCLES(count<<CYC_MOVEM_W);\r
7234}\r
7235\r
7236\r
7237M68KMAKE_OP(movem, 16, er, .)\r
7238{\r
7239 uint i = 0;\r
7240 uint register_list = OPER_I_16();\r
7241 uint ea = M68KMAKE_GET_EA_AY_16;\r
7242 uint count = 0;\r
7243\r
7244 for(; i < 16; i++)\r
7245 if(register_list & (1 << i))\r
7246 {\r
7247 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7248 ea += 2;\r
7249 count++;\r
7250 }\r
7251\r
7252 USE_CYCLES(count<<CYC_MOVEM_W);\r
7253}\r
7254\r
7255\r
7256M68KMAKE_OP(movem, 32, er, pi)\r
7257{\r
7258 uint i = 0;\r
7259 uint register_list = OPER_I_16();\r
7260 uint ea = AY;\r
7261 uint count = 0;\r
7262\r
7263 for(; i < 16; i++)\r
7264 if(register_list & (1 << i))\r
7265 {\r
7266 REG_DA[i] = m68ki_read_32(ea);\r
7267 ea += 4;\r
7268 count++;\r
7269 }\r
7270 AY = ea;\r
7271\r
7272 USE_CYCLES(count<<CYC_MOVEM_L);\r
7273}\r
7274\r
7275\r
7276M68KMAKE_OP(movem, 32, er, pcdi)\r
7277{\r
7278 uint i = 0;\r
7279 uint register_list = OPER_I_16();\r
7280 uint ea = EA_PCDI_32();\r
7281 uint count = 0;\r
7282\r
7283 for(; i < 16; i++)\r
7284 if(register_list & (1 << i))\r
7285 {\r
7286 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7287 ea += 4;\r
7288 count++;\r
7289 }\r
7290\r
7291 USE_CYCLES(count<<CYC_MOVEM_L);\r
7292}\r
7293\r
7294\r
7295M68KMAKE_OP(movem, 32, er, pcix)\r
7296{\r
7297 uint i = 0;\r
7298 uint register_list = OPER_I_16();\r
7299 uint ea = EA_PCIX_32();\r
7300 uint count = 0;\r
7301\r
7302 for(; i < 16; i++)\r
7303 if(register_list & (1 << i))\r
7304 {\r
7305 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7306 ea += 4;\r
7307 count++;\r
7308 }\r
7309\r
7310 USE_CYCLES(count<<CYC_MOVEM_L);\r
7311}\r
7312\r
7313\r
7314M68KMAKE_OP(movem, 32, er, .)\r
7315{\r
7316 uint i = 0;\r
7317 uint register_list = OPER_I_16();\r
7318 uint ea = M68KMAKE_GET_EA_AY_32;\r
7319 uint count = 0;\r
7320\r
7321 for(; i < 16; i++)\r
7322 if(register_list & (1 << i))\r
7323 {\r
7324 REG_DA[i] = m68ki_read_32(ea);\r
7325 ea += 4;\r
7326 count++;\r
7327 }\r
7328\r
7329 USE_CYCLES(count<<CYC_MOVEM_L);\r
7330}\r
7331\r
7332\r
7333M68KMAKE_OP(movep, 16, re, .)\r
7334{\r
7335 uint ea = EA_AY_DI_16();\r
7336 uint src = DX;\r
7337\r
7338 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));\r
7339 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7340}\r
7341\r
7342\r
7343M68KMAKE_OP(movep, 32, re, .)\r
7344{\r
7345 uint ea = EA_AY_DI_32();\r
7346 uint src = DX;\r
7347\r
7348 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));\r
7349 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));\r
7350 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));\r
7351 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7352}\r
7353\r
7354\r
7355M68KMAKE_OP(movep, 16, er, .)\r
7356{\r
7357 uint ea = EA_AY_DI_16();\r
7358 uint* r_dst = &DX;\r
7359\r
7360 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));\r
7361}\r
7362\r
7363\r
7364M68KMAKE_OP(movep, 32, er, .)\r
7365{\r
7366 uint ea = EA_AY_DI_32();\r
7367\r
7368 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)\r
7369 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);\r
7370}\r
7371\r
7372\r
7373M68KMAKE_OP(moves, 8, ., .)\r
7374{\r
7375 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7376 {\r
7377 if(FLAG_S)\r
7378 {\r
7379 uint word2 = OPER_I_16();\r
7380 uint ea = M68KMAKE_GET_EA_AY_8;\r
7381\r
7382 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7383 if(BIT_B(word2)) /* Register to memory */\r
7384 {\r
7385 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));\r
7386 return;\r
7387 }\r
7388 if(BIT_F(word2)) /* Memory to address register */\r
7389 {\r
7390 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));\r
7391 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7392 USE_CYCLES(2);\r
7393 return;\r
7394 }\r
7395 /* Memory to data register */\r
7396 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);\r
7397 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7398 USE_CYCLES(2);\r
7399 return;\r
7400 }\r
7401 m68ki_exception_privilege_violation();\r
7402 return;\r
7403 }\r
7404 m68ki_exception_illegal();\r
7405}\r
7406\r
7407\r
7408M68KMAKE_OP(moves, 16, ., .)\r
7409{\r
7410 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7411 {\r
7412 if(FLAG_S)\r
7413 {\r
7414 uint word2 = OPER_I_16();\r
7415 uint ea = M68KMAKE_GET_EA_AY_16;\r
7416\r
7417 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7418 if(BIT_B(word2)) /* Register to memory */\r
7419 {\r
7420 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));\r
7421 return;\r
7422 }\r
7423 if(BIT_F(word2)) /* Memory to address register */\r
7424 {\r
7425 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));\r
7426 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7427 USE_CYCLES(2);\r
7428 return;\r
7429 }\r
7430 /* Memory to data register */\r
7431 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);\r
7432 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7433 USE_CYCLES(2);\r
7434 return;\r
7435 }\r
7436 m68ki_exception_privilege_violation();\r
7437 return;\r
7438 }\r
7439 m68ki_exception_illegal();\r
7440}\r
7441\r
7442\r
7443M68KMAKE_OP(moves, 32, ., .)\r
7444{\r
7445 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7446 {\r
7447 if(FLAG_S)\r
7448 {\r
7449 uint word2 = OPER_I_16();\r
7450 uint ea = M68KMAKE_GET_EA_AY_32;\r
7451\r
7452 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7453 if(BIT_B(word2)) /* Register to memory */\r
7454 {\r
7455 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);\r
7456 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7457 USE_CYCLES(2);\r
7458 return;\r
7459 }\r
7460 /* Memory to register */\r
7461 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);\r
7462 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7463 USE_CYCLES(2);\r
7464 return;\r
7465 }\r
7466 m68ki_exception_privilege_violation();\r
7467 return;\r
7468 }\r
7469 m68ki_exception_illegal();\r
7470}\r
7471\r
7472\r
7473M68KMAKE_OP(moveq, 32, ., .)\r
7474{\r
7475 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));\r
7476\r
7477 FLAG_N = NFLAG_32(res);\r
7478 FLAG_Z = res;\r
7479 FLAG_V = VFLAG_CLEAR;\r
7480 FLAG_C = CFLAG_CLEAR;\r
7481}\r
7482\r
7483\r
7484M68KMAKE_OP(move16, 32, ., .)\r
7485{\r
7486 UINT16 w2 = OPER_I_16();\r
7487 int ax = REG_IR & 7;\r
7488 int ay = (w2 >> 12) & 7;\r
7489\r
7490 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));\r
7491 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));\r
7492 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));\r
7493 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));\r
7494\r
7495 REG_A[ax] += 16;\r
7496 REG_A[ay] += 16;\r
7497}\r
7498\r
7499\r
7500M68KMAKE_OP(muls, 16, ., d)\r
7501{\r
7502 uint* r_dst = &DX;\r
7503 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7504\r
7505 *r_dst = res;\r
7506\r
7507 FLAG_Z = res;\r
7508 FLAG_N = NFLAG_32(res);\r
7509 FLAG_V = VFLAG_CLEAR;\r
7510 FLAG_C = CFLAG_CLEAR;\r
7511}\r
7512\r
7513\r
7514M68KMAKE_OP(muls, 16, ., .)\r
7515{\r
7516 uint* r_dst = &DX;\r
7517 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7518\r
7519 *r_dst = res;\r
7520\r
7521 FLAG_Z = res;\r
7522 FLAG_N = NFLAG_32(res);\r
7523 FLAG_V = VFLAG_CLEAR;\r
7524 FLAG_C = CFLAG_CLEAR;\r
7525}\r
7526\r
7527\r
7528M68KMAKE_OP(mulu, 16, ., d)\r
7529{\r
7530 uint* r_dst = &DX;\r
7531 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);\r
7532\r
7533 *r_dst = res;\r
7534\r
7535 FLAG_Z = res;\r
7536 FLAG_N = NFLAG_32(res);\r
7537 FLAG_V = VFLAG_CLEAR;\r
7538 FLAG_C = CFLAG_CLEAR;\r
7539}\r
7540\r
7541\r
7542M68KMAKE_OP(mulu, 16, ., .)\r
7543{\r
7544 uint* r_dst = &DX;\r
7545 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);\r
7546\r
7547 *r_dst = res;\r
7548\r
7549 FLAG_Z = res;\r
7550 FLAG_N = NFLAG_32(res);\r
7551 FLAG_V = VFLAG_CLEAR;\r
7552 FLAG_C = CFLAG_CLEAR;\r
7553}\r
7554\r
7555\r
7556M68KMAKE_OP(mull, 32, ., d)\r
7557{\r
7558#if M68K_USE_64_BIT\r
7559\r
7560 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7561 {\r
7562 uint word2 = OPER_I_16();\r
7563 uint64 src = DY;\r
7564 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7565 uint64 res;\r
7566\r
7567 FLAG_C = CFLAG_CLEAR;\r
7568\r
7569 if(BIT_B(word2)) /* signed */\r
7570 {\r
7571 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7572 if(!BIT_A(word2))\r
7573 {\r
7574 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7575 FLAG_N = NFLAG_32(res);\r
7576 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7577 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7578 return;\r
7579 }\r
7580 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7581 FLAG_N = NFLAG_64(res);\r
7582 FLAG_V = VFLAG_CLEAR;\r
7583 REG_D[word2 & 7] = (res >> 32);\r
7584 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7585 return;\r
7586 }\r
7587\r
7588 res = src * dst;\r
7589 if(!BIT_A(word2))\r
7590 {\r
7591 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7592 FLAG_N = NFLAG_32(res);\r
7593 FLAG_V = (res > 0xffffffff)<<7;\r
7594 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7595 return;\r
7596 }\r
7597 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7598 FLAG_N = NFLAG_64(res);\r
7599 FLAG_V = VFLAG_CLEAR;\r
7600 REG_D[word2 & 7] = (res >> 32);\r
7601 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7602 return;\r
7603 }\r
7604 m68ki_exception_illegal();\r
7605\r
7606#else\r
7607\r
7608 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7609 {\r
7610 uint word2 = OPER_I_16();\r
7611 uint src = DY;\r
7612 uint dst = REG_D[(word2 >> 12) & 7];\r
7613 uint neg = GET_MSB_32(src ^ dst);\r
7614 uint src1;\r
7615 uint src2;\r
7616 uint dst1;\r
7617 uint dst2;\r
7618 uint r1;\r
7619 uint r2;\r
7620 uint r3;\r
7621 uint r4;\r
7622 uint lo;\r
7623 uint hi;\r
7624\r
7625 FLAG_C = CFLAG_CLEAR;\r
7626\r
7627 if(BIT_B(word2)) /* signed */\r
7628 {\r
7629 if(GET_MSB_32(src))\r
7630 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7631 if(GET_MSB_32(dst))\r
7632 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7633 }\r
7634\r
7635 src1 = MASK_OUT_ABOVE_16(src);\r
7636 src2 = src>>16;\r
7637 dst1 = MASK_OUT_ABOVE_16(dst);\r
7638 dst2 = dst>>16;\r
7639\r
7640\r
7641 r1 = src1 * dst1;\r
7642 r2 = src1 * dst2;\r
7643 r3 = src2 * dst1;\r
7644 r4 = src2 * dst2;\r
7645\r
7646 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7647 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7648\r
7649 if(BIT_B(word2) && neg)\r
7650 {\r
7651 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7652 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7653 }\r
7654\r
7655 if(BIT_A(word2))\r
7656 {\r
7657 REG_D[word2 & 7] = hi;\r
7658 REG_D[(word2 >> 12) & 7] = lo;\r
7659 FLAG_N = NFLAG_32(hi);\r
7660 FLAG_Z = hi | lo;\r
7661 FLAG_V = VFLAG_CLEAR;\r
7662 return;\r
7663 }\r
7664\r
7665 REG_D[(word2 >> 12) & 7] = lo;\r
7666 FLAG_N = NFLAG_32(lo);\r
7667 FLAG_Z = lo;\r
7668 if(BIT_B(word2))\r
7669 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7670 else\r
7671 FLAG_V = (hi != 0) << 7;\r
7672 return;\r
7673 }\r
7674 m68ki_exception_illegal();\r
7675\r
7676#endif\r
7677}\r
7678\r
7679\r
7680M68KMAKE_OP(mull, 32, ., .)\r
7681{\r
7682#if M68K_USE_64_BIT\r
7683\r
7684 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7685 {\r
7686 uint word2 = OPER_I_16();\r
7687 uint64 src = M68KMAKE_GET_OPER_AY_32;\r
7688 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7689 uint64 res;\r
7690\r
7691 FLAG_C = CFLAG_CLEAR;\r
7692\r
7693 if(BIT_B(word2)) /* signed */\r
7694 {\r
7695 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7696 if(!BIT_A(word2))\r
7697 {\r
7698 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7699 FLAG_N = NFLAG_32(res);\r
7700 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7701 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7702 return;\r
7703 }\r
7704 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7705 FLAG_N = NFLAG_64(res);\r
7706 FLAG_V = VFLAG_CLEAR;\r
7707 REG_D[word2 & 7] = (res >> 32);\r
7708 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7709 return;\r
7710 }\r
7711\r
7712 res = src * dst;\r
7713 if(!BIT_A(word2))\r
7714 {\r
7715 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7716 FLAG_N = NFLAG_32(res);\r
7717 FLAG_V = (res > 0xffffffff)<<7;\r
7718 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7719 return;\r
7720 }\r
7721 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7722 FLAG_N = NFLAG_64(res);\r
7723 FLAG_V = VFLAG_CLEAR;\r
7724 REG_D[word2 & 7] = (res >> 32);\r
7725 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7726 return;\r
7727 }\r
7728 m68ki_exception_illegal();\r
7729\r
7730#else\r
7731\r
7732 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7733 {\r
7734 uint word2 = OPER_I_16();\r
7735 uint src = M68KMAKE_GET_OPER_AY_32;\r
7736 uint dst = REG_D[(word2 >> 12) & 7];\r
7737 uint neg = GET_MSB_32(src ^ dst);\r
7738 uint src1;\r
7739 uint src2;\r
7740 uint dst1;\r
7741 uint dst2;\r
7742 uint r1;\r
7743 uint r2;\r
7744 uint r3;\r
7745 uint r4;\r
7746 uint lo;\r
7747 uint hi;\r
7748\r
7749 FLAG_C = CFLAG_CLEAR;\r
7750\r
7751 if(BIT_B(word2)) /* signed */\r
7752 {\r
7753 if(GET_MSB_32(src))\r
7754 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7755 if(GET_MSB_32(dst))\r
7756 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7757 }\r
7758\r
7759 src1 = MASK_OUT_ABOVE_16(src);\r
7760 src2 = src>>16;\r
7761 dst1 = MASK_OUT_ABOVE_16(dst);\r
7762 dst2 = dst>>16;\r
7763\r
7764\r
7765 r1 = src1 * dst1;\r
7766 r2 = src1 * dst2;\r
7767 r3 = src2 * dst1;\r
7768 r4 = src2 * dst2;\r
7769\r
7770 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7771 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7772\r
7773 if(BIT_B(word2) && neg)\r
7774 {\r
7775 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7776 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7777 }\r
7778\r
7779 if(BIT_A(word2))\r
7780 {\r
7781 REG_D[word2 & 7] = hi;\r
7782 REG_D[(word2 >> 12) & 7] = lo;\r
7783 FLAG_N = NFLAG_32(hi);\r
7784 FLAG_Z = hi | lo;\r
7785 FLAG_V = VFLAG_CLEAR;\r
7786 return;\r
7787 }\r
7788\r
7789 REG_D[(word2 >> 12) & 7] = lo;\r
7790 FLAG_N = NFLAG_32(lo);\r
7791 FLAG_Z = lo;\r
7792 if(BIT_B(word2))\r
7793 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7794 else\r
7795 FLAG_V = (hi != 0) << 7;\r
7796 return;\r
7797 }\r
7798 m68ki_exception_illegal();\r
7799\r
7800#endif\r
7801}\r
7802\r
7803\r
7804M68KMAKE_OP(nbcd, 8, ., d)\r
7805{\r
7806 uint* r_dst = &DY;\r
c6e1e977 7807 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
7808 uint res = -dst - XFLAG_AS_1();\r
cc68a136 7809\r
c6e1e977 7810 if(res != 0)\r
cc68a136 7811 {\r
c6e1e977 7812 FLAG_V = res; /* Undefined V behavior */\r
cc68a136 7813\r
c6e1e977 7814 if(((res|dst) & 0x0f) == 0)\r
7815 res = (res & 0xf0) + 6;\r
cc68a136 7816\r
c6e1e977 7817 res = MASK_OUT_ABOVE_8(res + 0x9a);\r
cc68a136 7818\r
c6e1e977 7819 FLAG_V &= ~res; /* Undefined V behavior part II */\r
cc68a136 7820\r
7821 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7822\r
7823 FLAG_Z |= res;\r
7824 FLAG_C = CFLAG_SET;\r
7825 FLAG_X = XFLAG_SET;\r
7826 }\r
7827 else\r
7828 {\r
7829 FLAG_V = VFLAG_CLEAR;\r
7830 FLAG_C = CFLAG_CLEAR;\r
7831 FLAG_X = XFLAG_CLEAR;\r
7832 }\r
7833 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7834}\r
7835\r
7836\r
7837M68KMAKE_OP(nbcd, 8, ., .)\r
7838{\r
7839 uint ea = M68KMAKE_GET_EA_AY_8;\r
7840 uint dst = m68ki_read_8(ea);\r
c6e1e977 7841 uint res = -dst - XFLAG_AS_1();\r
cc68a136 7842\r
c6e1e977 7843 if(res != 0)\r
cc68a136 7844 {\r
c6e1e977 7845 FLAG_V = res; /* Undefined V behavior */\r
cc68a136 7846\r
c6e1e977 7847 if(((res|dst) & 0x0f) == 0)\r
7848 res = (res & 0xf0) + 6;\r
cc68a136 7849\r
c6e1e977 7850 res = MASK_OUT_ABOVE_8(res + 0x9a);\r
cc68a136 7851\r
c6e1e977 7852 FLAG_V &= ~res; /* Undefined V behavior part II */\r
cc68a136 7853\r
7854 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));\r
7855\r
7856 FLAG_Z |= res;\r
7857 FLAG_C = CFLAG_SET;\r
7858 FLAG_X = XFLAG_SET;\r
7859 }\r
7860 else\r
7861 {\r
7862 FLAG_V = VFLAG_CLEAR;\r
7863 FLAG_C = CFLAG_CLEAR;\r
7864 FLAG_X = XFLAG_CLEAR;\r
7865 }\r
7866 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7867}\r
7868\r
7869\r
7870M68KMAKE_OP(neg, 8, ., d)\r
7871{\r
7872 uint* r_dst = &DY;\r
7873 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);\r
7874\r
7875 FLAG_N = NFLAG_8(res);\r
7876 FLAG_C = FLAG_X = CFLAG_8(res);\r
7877 FLAG_V = *r_dst & res;\r
7878 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7879\r
7880 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
7881}\r
7882\r
7883\r
7884M68KMAKE_OP(neg, 8, ., .)\r
7885{\r
7886 uint ea = M68KMAKE_GET_EA_AY_8;\r
7887 uint src = m68ki_read_8(ea);\r
7888 uint res = 0 - src;\r
7889\r
7890 FLAG_N = NFLAG_8(res);\r
7891 FLAG_C = FLAG_X = CFLAG_8(res);\r
7892 FLAG_V = src & res;\r
7893 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7894\r
7895 m68ki_write_8(ea, FLAG_Z);\r
7896}\r
7897\r
7898\r
7899M68KMAKE_OP(neg, 16, ., d)\r
7900{\r
7901 uint* r_dst = &DY;\r
7902 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);\r
7903\r
7904 FLAG_N = NFLAG_16(res);\r
7905 FLAG_C = FLAG_X = CFLAG_16(res);\r
7906 FLAG_V = (*r_dst & res)>>8;\r
7907 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
7908\r
7909 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
7910}\r
7911\r
7912\r
7913M68KMAKE_OP(neg, 16, ., .)\r
7914{\r
7915 uint ea = M68KMAKE_GET_EA_AY_16;\r
7916 uint src = m68ki_read_16(ea);\r
7917 uint res = 0 - src;\r
7918\r
7919 FLAG_N = NFLAG_16(res);\r
7920 FLAG_C = FLAG_X = CFLAG_16(res);\r
7921 FLAG_V = (src & res)>>8;\r
7922 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
7923\r
7924 m68ki_write_16(ea, FLAG_Z);\r
7925}\r
7926\r
7927\r
7928M68KMAKE_OP(neg, 32, ., d)\r
7929{\r
7930 uint* r_dst = &DY;\r
7931 uint res = 0 - *r_dst;\r
7932\r
7933 FLAG_N = NFLAG_32(res);\r
7934 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);\r
7935 FLAG_V = (*r_dst & res)>>24;\r
7936 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7937\r
7938 *r_dst = FLAG_Z;\r
7939}\r
7940\r
7941\r
7942M68KMAKE_OP(neg, 32, ., .)\r
7943{\r
7944 uint ea = M68KMAKE_GET_EA_AY_32;\r
7945 uint src = m68ki_read_32(ea);\r
7946 uint res = 0 - src;\r
7947\r
7948 FLAG_N = NFLAG_32(res);\r
7949 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);\r
7950 FLAG_V = (src & res)>>24;\r
7951 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7952\r
7953 m68ki_write_32(ea, FLAG_Z);\r
7954}\r
7955\r
7956\r
7957M68KMAKE_OP(negx, 8, ., d)\r
7958{\r
7959 uint* r_dst = &DY;\r
7960 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();\r
7961\r
7962 FLAG_N = NFLAG_8(res);\r
7963 FLAG_X = FLAG_C = CFLAG_8(res);\r
7964 FLAG_V = *r_dst & res;\r
7965\r
7966 res = MASK_OUT_ABOVE_8(res);\r
7967 FLAG_Z |= res;\r
7968\r
7969 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7970}\r
7971\r
7972\r
7973M68KMAKE_OP(negx, 8, ., .)\r
7974{\r
7975 uint ea = M68KMAKE_GET_EA_AY_8;\r
7976 uint src = m68ki_read_8(ea);\r
7977 uint res = 0 - src - XFLAG_AS_1();\r
7978\r
7979 FLAG_N = NFLAG_8(res);\r
7980 FLAG_X = FLAG_C = CFLAG_8(res);\r
7981 FLAG_V = src & res;\r
7982\r
7983 res = MASK_OUT_ABOVE_8(res);\r
7984 FLAG_Z |= res;\r
7985\r
7986 m68ki_write_8(ea, res);\r
7987}\r
7988\r
7989\r
7990M68KMAKE_OP(negx, 16, ., d)\r
7991{\r
7992 uint* r_dst = &DY;\r
7993 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();\r
7994\r
7995 FLAG_N = NFLAG_16(res);\r
7996 FLAG_X = FLAG_C = CFLAG_16(res);\r
7997 FLAG_V = (*r_dst & res)>>8;\r
7998\r
7999 res = MASK_OUT_ABOVE_16(res);\r
8000 FLAG_Z |= res;\r
8001\r
8002 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8003}\r
8004\r
8005\r
8006M68KMAKE_OP(negx, 16, ., .)\r
8007{\r
8008 uint ea = M68KMAKE_GET_EA_AY_16;\r
8009 uint src = m68ki_read_16(ea);\r
8010 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();\r
8011\r
8012 FLAG_N = NFLAG_16(res);\r
8013 FLAG_X = FLAG_C = CFLAG_16(res);\r
8014 FLAG_V = (src & res)>>8;\r
8015\r
8016 res = MASK_OUT_ABOVE_16(res);\r
8017 FLAG_Z |= res;\r
8018\r
8019 m68ki_write_16(ea, res);\r
8020}\r
8021\r
8022\r
8023M68KMAKE_OP(negx, 32, ., d)\r
8024{\r
8025 uint* r_dst = &DY;\r
8026 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();\r
8027\r
8028 FLAG_N = NFLAG_32(res);\r
8029 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);\r
8030 FLAG_V = (*r_dst & res)>>24;\r
8031\r
8032 res = MASK_OUT_ABOVE_32(res);\r
8033 FLAG_Z |= res;\r
8034\r
8035 *r_dst = res;\r
8036}\r
8037\r
8038\r
8039M68KMAKE_OP(negx, 32, ., .)\r
8040{\r
8041 uint ea = M68KMAKE_GET_EA_AY_32;\r
8042 uint src = m68ki_read_32(ea);\r
8043 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();\r
8044\r
8045 FLAG_N = NFLAG_32(res);\r
8046 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);\r
8047 FLAG_V = (src & res)>>24;\r
8048\r
8049 res = MASK_OUT_ABOVE_32(res);\r
8050 FLAG_Z |= res;\r
8051\r
8052 m68ki_write_32(ea, res);\r
8053}\r
8054\r
8055\r
8056M68KMAKE_OP(nop, 0, ., .)\r
8057{\r
8058 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8059}\r
8060\r
8061\r
8062M68KMAKE_OP(not, 8, ., d)\r
8063{\r
8064 uint* r_dst = &DY;\r
8065 uint res = MASK_OUT_ABOVE_8(~*r_dst);\r
8066\r
8067 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8068\r
8069 FLAG_N = NFLAG_8(res);\r
8070 FLAG_Z = res;\r
8071 FLAG_C = CFLAG_CLEAR;\r
8072 FLAG_V = VFLAG_CLEAR;\r
8073}\r
8074\r
8075\r
8076M68KMAKE_OP(not, 8, ., .)\r
8077{\r
8078 uint ea = M68KMAKE_GET_EA_AY_8;\r
8079 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));\r
8080\r
8081 m68ki_write_8(ea, res);\r
8082\r
8083 FLAG_N = NFLAG_8(res);\r
8084 FLAG_Z = res;\r
8085 FLAG_C = CFLAG_CLEAR;\r
8086 FLAG_V = VFLAG_CLEAR;\r
8087}\r
8088\r
8089\r
8090M68KMAKE_OP(not, 16, ., d)\r
8091{\r
8092 uint* r_dst = &DY;\r
8093 uint res = MASK_OUT_ABOVE_16(~*r_dst);\r
8094\r
8095 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8096\r
8097 FLAG_N = NFLAG_16(res);\r
8098 FLAG_Z = res;\r
8099 FLAG_C = CFLAG_CLEAR;\r
8100 FLAG_V = VFLAG_CLEAR;\r
8101}\r
8102\r
8103\r
8104M68KMAKE_OP(not, 16, ., .)\r
8105{\r
8106 uint ea = M68KMAKE_GET_EA_AY_16;\r
8107 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));\r
8108\r
8109 m68ki_write_16(ea, res);\r
8110\r
8111 FLAG_N = NFLAG_16(res);\r
8112 FLAG_Z = res;\r
8113 FLAG_C = CFLAG_CLEAR;\r
8114 FLAG_V = VFLAG_CLEAR;\r
8115}\r
8116\r
8117\r
8118M68KMAKE_OP(not, 32, ., d)\r
8119{\r
8120 uint* r_dst = &DY;\r
8121 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);\r
8122\r
8123 FLAG_N = NFLAG_32(res);\r
8124 FLAG_Z = res;\r
8125 FLAG_C = CFLAG_CLEAR;\r
8126 FLAG_V = VFLAG_CLEAR;\r
8127}\r
8128\r
8129\r
8130M68KMAKE_OP(not, 32, ., .)\r
8131{\r
8132 uint ea = M68KMAKE_GET_EA_AY_32;\r
8133 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));\r
8134\r
8135 m68ki_write_32(ea, res);\r
8136\r
8137 FLAG_N = NFLAG_32(res);\r
8138 FLAG_Z = res;\r
8139 FLAG_C = CFLAG_CLEAR;\r
8140 FLAG_V = VFLAG_CLEAR;\r
8141}\r
8142\r
8143\r
8144M68KMAKE_OP(or, 8, er, d)\r
8145{\r
8146 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));\r
8147\r
8148 FLAG_N = NFLAG_8(res);\r
8149 FLAG_Z = res;\r
8150 FLAG_C = CFLAG_CLEAR;\r
8151 FLAG_V = VFLAG_CLEAR;\r
8152}\r
8153\r
8154\r
8155M68KMAKE_OP(or, 8, er, .)\r
8156{\r
8157 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));\r
8158\r
8159 FLAG_N = NFLAG_8(res);\r
8160 FLAG_Z = res;\r
8161 FLAG_C = CFLAG_CLEAR;\r
8162 FLAG_V = VFLAG_CLEAR;\r
8163}\r
8164\r
8165\r
8166M68KMAKE_OP(or, 16, er, d)\r
8167{\r
8168 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));\r
8169\r
8170 FLAG_N = NFLAG_16(res);\r
8171 FLAG_Z = res;\r
8172 FLAG_C = CFLAG_CLEAR;\r
8173 FLAG_V = VFLAG_CLEAR;\r
8174}\r
8175\r
8176\r
8177M68KMAKE_OP(or, 16, er, .)\r
8178{\r
8179 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));\r
8180\r
8181 FLAG_N = NFLAG_16(res);\r
8182 FLAG_Z = res;\r
8183 FLAG_C = CFLAG_CLEAR;\r
8184 FLAG_V = VFLAG_CLEAR;\r
8185}\r
8186\r
8187\r
8188M68KMAKE_OP(or, 32, er, d)\r
8189{\r
8190 uint res = DX |= DY;\r
8191\r
8192 FLAG_N = NFLAG_32(res);\r
8193 FLAG_Z = res;\r
8194 FLAG_C = CFLAG_CLEAR;\r
8195 FLAG_V = VFLAG_CLEAR;\r
8196}\r
8197\r
8198\r
8199M68KMAKE_OP(or, 32, er, .)\r
8200{\r
8201 uint res = DX |= M68KMAKE_GET_OPER_AY_32;\r
8202\r
8203 FLAG_N = NFLAG_32(res);\r
8204 FLAG_Z = res;\r
8205 FLAG_C = CFLAG_CLEAR;\r
8206 FLAG_V = VFLAG_CLEAR;\r
8207}\r
8208\r
8209\r
8210M68KMAKE_OP(or, 8, re, .)\r
8211{\r
8212 uint ea = M68KMAKE_GET_EA_AY_8;\r
8213 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));\r
8214\r
8215 m68ki_write_8(ea, res);\r
8216\r
8217 FLAG_N = NFLAG_8(res);\r
8218 FLAG_Z = res;\r
8219 FLAG_C = CFLAG_CLEAR;\r
8220 FLAG_V = VFLAG_CLEAR;\r
8221}\r
8222\r
8223\r
8224M68KMAKE_OP(or, 16, re, .)\r
8225{\r
8226 uint ea = M68KMAKE_GET_EA_AY_16;\r
8227 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));\r
8228\r
8229 m68ki_write_16(ea, res);\r
8230\r
8231 FLAG_N = NFLAG_16(res);\r
8232 FLAG_Z = res;\r
8233 FLAG_C = CFLAG_CLEAR;\r
8234 FLAG_V = VFLAG_CLEAR;\r
8235}\r
8236\r
8237\r
8238M68KMAKE_OP(or, 32, re, .)\r
8239{\r
8240 uint ea = M68KMAKE_GET_EA_AY_32;\r
8241 uint res = DX | m68ki_read_32(ea);\r
8242\r
8243 m68ki_write_32(ea, res);\r
8244\r
8245 FLAG_N = NFLAG_32(res);\r
8246 FLAG_Z = res;\r
8247 FLAG_C = CFLAG_CLEAR;\r
8248 FLAG_V = VFLAG_CLEAR;\r
8249}\r
8250\r
8251\r
8252M68KMAKE_OP(ori, 8, ., d)\r
8253{\r
8254 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));\r
8255\r
8256 FLAG_N = NFLAG_8(res);\r
8257 FLAG_Z = res;\r
8258 FLAG_C = CFLAG_CLEAR;\r
8259 FLAG_V = VFLAG_CLEAR;\r
8260}\r
8261\r
8262\r
8263M68KMAKE_OP(ori, 8, ., .)\r
8264{\r
8265 uint src = OPER_I_8();\r
8266 uint ea = M68KMAKE_GET_EA_AY_8;\r
8267 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));\r
8268\r
8269 m68ki_write_8(ea, res);\r
8270\r
8271 FLAG_N = NFLAG_8(res);\r
8272 FLAG_Z = res;\r
8273 FLAG_C = CFLAG_CLEAR;\r
8274 FLAG_V = VFLAG_CLEAR;\r
8275}\r
8276\r
8277\r
8278M68KMAKE_OP(ori, 16, ., d)\r
8279{\r
8280 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());\r
8281\r
8282 FLAG_N = NFLAG_16(res);\r
8283 FLAG_Z = res;\r
8284 FLAG_C = CFLAG_CLEAR;\r
8285 FLAG_V = VFLAG_CLEAR;\r
8286}\r
8287\r
8288\r
8289M68KMAKE_OP(ori, 16, ., .)\r
8290{\r
8291 uint src = OPER_I_16();\r
8292 uint ea = M68KMAKE_GET_EA_AY_16;\r
8293 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));\r
8294\r
8295 m68ki_write_16(ea, res);\r
8296\r
8297 FLAG_N = NFLAG_16(res);\r
8298 FLAG_Z = res;\r
8299 FLAG_C = CFLAG_CLEAR;\r
8300 FLAG_V = VFLAG_CLEAR;\r
8301}\r
8302\r
8303\r
8304M68KMAKE_OP(ori, 32, ., d)\r
8305{\r
8306 uint res = DY |= OPER_I_32();\r
8307\r
8308 FLAG_N = NFLAG_32(res);\r
8309 FLAG_Z = res;\r
8310 FLAG_C = CFLAG_CLEAR;\r
8311 FLAG_V = VFLAG_CLEAR;\r
8312}\r
8313\r
8314\r
8315M68KMAKE_OP(ori, 32, ., .)\r
8316{\r
8317 uint src = OPER_I_32();\r
8318 uint ea = M68KMAKE_GET_EA_AY_32;\r
8319 uint res = src | m68ki_read_32(ea);\r
8320\r
8321 m68ki_write_32(ea, res);\r
8322\r
8323 FLAG_N = NFLAG_32(res);\r
8324 FLAG_Z = res;\r
8325 FLAG_C = CFLAG_CLEAR;\r
8326 FLAG_V = VFLAG_CLEAR;\r
8327}\r
8328\r
8329\r
8330M68KMAKE_OP(ori, 16, toc, .)\r
8331{\r
8332 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());\r
8333}\r
8334\r
8335\r
8336M68KMAKE_OP(ori, 16, tos, .)\r
8337{\r
8338 if(FLAG_S)\r
8339 {\r
8340 uint src = OPER_I_16();\r
8341 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8342 m68ki_set_sr(m68ki_get_sr() | src);\r
8343 return;\r
8344 }\r
8345 m68ki_exception_privilege_violation();\r
8346}\r
8347\r
8348\r
8349M68KMAKE_OP(pack, 16, rr, .)\r
8350{\r
8351 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8352 {\r
8353 /* Note: DX and DY are reversed in Motorola's docs */\r
8354 uint src = DY + OPER_I_16();\r
8355 uint* r_dst = &DX;\r
8356\r
8357 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);\r
8358 return;\r
8359 }\r
8360 m68ki_exception_illegal();\r
8361}\r
8362\r
8363\r
8364M68KMAKE_OP(pack, 16, mm, ax7)\r
8365{\r
8366 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8367 {\r
8368 /* Note: AX and AY are reversed in Motorola's docs */\r
8369 uint ea_src = EA_AY_PD_8();\r
8370 uint src = m68ki_read_8(ea_src);\r
8371 ea_src = EA_AY_PD_8();\r
8372 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8373\r
8374 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8375 return;\r
8376 }\r
8377 m68ki_exception_illegal();\r
8378}\r
8379\r
8380\r
8381M68KMAKE_OP(pack, 16, mm, ay7)\r
8382{\r
8383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8384 {\r
8385 /* Note: AX and AY are reversed in Motorola's docs */\r
8386 uint ea_src = EA_A7_PD_8();\r
8387 uint src = m68ki_read_8(ea_src);\r
8388 ea_src = EA_A7_PD_8();\r
8389 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8390\r
8391 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8392 return;\r
8393 }\r
8394 m68ki_exception_illegal();\r
8395}\r
8396\r
8397\r
8398M68KMAKE_OP(pack, 16, mm, axy7)\r
8399{\r
8400 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8401 {\r
8402 uint ea_src = EA_A7_PD_8();\r
8403 uint src = m68ki_read_8(ea_src);\r
8404 ea_src = EA_A7_PD_8();\r
8405 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8406\r
8407 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8408 return;\r
8409 }\r
8410 m68ki_exception_illegal();\r
8411}\r
8412\r
8413\r
8414M68KMAKE_OP(pack, 16, mm, .)\r
8415{\r
8416 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8417 {\r
8418 /* Note: AX and AY are reversed in Motorola's docs */\r
8419 uint ea_src = EA_AY_PD_8();\r
8420 uint src = m68ki_read_8(ea_src);\r
8421 ea_src = EA_AY_PD_8();\r
8422 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8423\r
8424 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8425 return;\r
8426 }\r
8427 m68ki_exception_illegal();\r
8428}\r
8429\r
8430\r
8431M68KMAKE_OP(pea, 32, ., .)\r
8432{\r
8433 uint ea = M68KMAKE_GET_EA_AY_32;\r
8434\r
8435 m68ki_push_32(ea);\r
8436}\r
8437\r
8438\r
8439M68KMAKE_OP(pflush, 32, ., .)\r
8440{\r
8441 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
8442 {\r
8443 // Nothing to do, unless address translation cache is emulated\r
8444 return;\r
8445 }\r
8446 m68ki_exception_illegal();\r
8447}\r
8448\r
8449\r
8450M68KMAKE_OP(reset, 0, ., .)\r
8451{\r
8452 if(FLAG_S)\r
8453 {\r
8454 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */\r
8455 USE_CYCLES(CYC_RESET);\r
8456 return;\r
8457 }\r
8458 m68ki_exception_privilege_violation();\r
8459}\r
8460\r
8461\r
8462M68KMAKE_OP(ror, 8, s, .)\r
8463{\r
8464 uint* r_dst = &DY;\r
8465 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8466 uint shift = orig_shift & 7;\r
8467 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8468 uint res = ROR_8(src, shift);\r
8469\r
8470 if(orig_shift != 0)\r
8471 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8472\r
8473 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8474\r
8475 FLAG_N = NFLAG_8(res);\r
8476 FLAG_Z = res;\r
8477 FLAG_C = src << (9-orig_shift);\r
8478 FLAG_V = VFLAG_CLEAR;\r
8479}\r
8480\r
8481\r
8482M68KMAKE_OP(ror, 16, s, .)\r
8483{\r
8484 uint* r_dst = &DY;\r
8485 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8486 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8487 uint res = ROR_16(src, shift);\r
8488\r
8489 if(shift != 0)\r
8490 USE_CYCLES(shift<<CYC_SHIFT);\r
8491\r
8492 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8493\r
8494 FLAG_N = NFLAG_16(res);\r
8495 FLAG_Z = res;\r
8496 FLAG_C = src << (9-shift);\r
8497 FLAG_V = VFLAG_CLEAR;\r
8498}\r
8499\r
8500\r
8501M68KMAKE_OP(ror, 32, s, .)\r
8502{\r
8503 uint* r_dst = &DY;\r
8504 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8505 uint64 src = *r_dst;\r
8506 uint res = ROR_32(src, shift);\r
8507\r
8508 if(shift != 0)\r
8509 USE_CYCLES(shift<<CYC_SHIFT);\r
8510\r
8511 *r_dst = res;\r
8512\r
8513 FLAG_N = NFLAG_32(res);\r
8514 FLAG_Z = res;\r
8515 FLAG_C = src << (9-shift);\r
8516 FLAG_V = VFLAG_CLEAR;\r
8517}\r
8518\r
8519\r
8520M68KMAKE_OP(ror, 8, r, .)\r
8521{\r
8522 uint* r_dst = &DY;\r
8523 uint orig_shift = DX & 0x3f;\r
8524 uint shift = orig_shift & 7;\r
8525 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8526 uint res = ROR_8(src, shift);\r
8527\r
8528 if(orig_shift != 0)\r
8529 {\r
8530 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8531\r
8532 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8533 FLAG_C = src << (8-((shift-1)&7));\r
8534 FLAG_N = NFLAG_8(res);\r
8535 FLAG_Z = res;\r
8536 FLAG_V = VFLAG_CLEAR;\r
8537 return;\r
8538 }\r
8539\r
8540 FLAG_C = CFLAG_CLEAR;\r
8541 FLAG_N = NFLAG_8(src);\r
8542 FLAG_Z = src;\r
8543 FLAG_V = VFLAG_CLEAR;\r
8544}\r
8545\r
8546\r
8547M68KMAKE_OP(ror, 16, r, .)\r
8548{\r
8549 uint* r_dst = &DY;\r
8550 uint orig_shift = DX & 0x3f;\r
8551 uint shift = orig_shift & 15;\r
8552 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8553 uint res = ROR_16(src, shift);\r
8554\r
8555 if(orig_shift != 0)\r
8556 {\r
8557 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8558\r
8559 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8560 FLAG_C = (src >> ((shift - 1) & 15)) << 8;\r
8561 FLAG_N = NFLAG_16(res);\r
8562 FLAG_Z = res;\r
8563 FLAG_V = VFLAG_CLEAR;\r
8564 return;\r
8565 }\r
8566\r
8567 FLAG_C = CFLAG_CLEAR;\r
8568 FLAG_N = NFLAG_16(src);\r
8569 FLAG_Z = src;\r
8570 FLAG_V = VFLAG_CLEAR;\r
8571}\r
8572\r
8573\r
8574M68KMAKE_OP(ror, 32, r, .)\r
8575{\r
8576 uint* r_dst = &DY;\r
8577 uint orig_shift = DX & 0x3f;\r
8578 uint shift = orig_shift & 31;\r
8579 uint64 src = *r_dst;\r
8580 uint res = ROR_32(src, shift);\r
8581\r
8582 if(orig_shift != 0)\r
8583 {\r
8584 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8585\r
8586 *r_dst = res;\r
8587 FLAG_C = (src >> ((shift - 1) & 31)) << 8;\r
8588 FLAG_N = NFLAG_32(res);\r
8589 FLAG_Z = res;\r
8590 FLAG_V = VFLAG_CLEAR;\r
8591 return;\r
8592 }\r
8593\r
8594 FLAG_C = CFLAG_CLEAR;\r
8595 FLAG_N = NFLAG_32(src);\r
8596 FLAG_Z = src;\r
8597 FLAG_V = VFLAG_CLEAR;\r
8598}\r
8599\r
8600\r
8601M68KMAKE_OP(ror, 16, ., .)\r
8602{\r
8603 uint ea = M68KMAKE_GET_EA_AY_16;\r
8604 uint src = m68ki_read_16(ea);\r
8605 uint res = ROR_16(src, 1);\r
8606\r
8607 m68ki_write_16(ea, res);\r
8608\r
8609 FLAG_N = NFLAG_16(res);\r
8610 FLAG_Z = res;\r
8611 FLAG_C = src << 8;\r
8612 FLAG_V = VFLAG_CLEAR;\r
8613}\r
8614\r
8615\r
8616M68KMAKE_OP(rol, 8, s, .)\r
8617{\r
8618 uint* r_dst = &DY;\r
8619 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8620 uint shift = orig_shift & 7;\r
8621 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8622 uint res = ROL_8(src, shift);\r
8623\r
8624 if(orig_shift != 0)\r
8625 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8626\r
8627 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8628\r
8629 FLAG_N = NFLAG_8(res);\r
8630 FLAG_Z = res;\r
8631 FLAG_C = src << orig_shift;\r
8632 FLAG_V = VFLAG_CLEAR;\r
8633}\r
8634\r
8635\r
8636M68KMAKE_OP(rol, 16, s, .)\r
8637{\r
8638 uint* r_dst = &DY;\r
8639 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8640 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8641 uint res = ROL_16(src, shift);\r
8642\r
8643 if(shift != 0)\r
8644 USE_CYCLES(shift<<CYC_SHIFT);\r
8645\r
8646 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8647\r
8648 FLAG_N = NFLAG_16(res);\r
8649 FLAG_Z = res;\r
8650 FLAG_C = src >> (8-shift);\r
8651 FLAG_V = VFLAG_CLEAR;\r
8652}\r
8653\r
8654\r
8655M68KMAKE_OP(rol, 32, s, .)\r
8656{\r
8657 uint* r_dst = &DY;\r
8658 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8659 uint64 src = *r_dst;\r
8660 uint res = ROL_32(src, shift);\r
8661\r
8662 if(shift != 0)\r
8663 USE_CYCLES(shift<<CYC_SHIFT);\r
8664\r
8665 *r_dst = res;\r
8666\r
8667 FLAG_N = NFLAG_32(res);\r
8668 FLAG_Z = res;\r
8669 FLAG_C = src >> (24-shift);\r
8670 FLAG_V = VFLAG_CLEAR;\r
8671}\r
8672\r
8673\r
8674M68KMAKE_OP(rol, 8, r, .)\r
8675{\r
8676 uint* r_dst = &DY;\r
8677 uint orig_shift = DX & 0x3f;\r
8678 uint shift = orig_shift & 7;\r
8679 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8680 uint res = ROL_8(src, shift);\r
8681\r
8682 if(orig_shift != 0)\r
8683 {\r
8684 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8685\r
8686 if(shift != 0)\r
8687 {\r
8688 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8689 FLAG_C = src << shift;\r
8690 FLAG_N = NFLAG_8(res);\r
8691 FLAG_Z = res;\r
8692 FLAG_V = VFLAG_CLEAR;\r
8693 return;\r
8694 }\r
8695 FLAG_C = (src & 1)<<8;\r
8696 FLAG_N = NFLAG_8(src);\r
8697 FLAG_Z = src;\r
8698 FLAG_V = VFLAG_CLEAR;\r
8699 return;\r
8700 }\r
8701\r
8702 FLAG_C = CFLAG_CLEAR;\r
8703 FLAG_N = NFLAG_8(src);\r
8704 FLAG_Z = src;\r
8705 FLAG_V = VFLAG_CLEAR;\r
8706}\r
8707\r
8708\r
8709M68KMAKE_OP(rol, 16, r, .)\r
8710{\r
8711 uint* r_dst = &DY;\r
8712 uint orig_shift = DX & 0x3f;\r
8713 uint shift = orig_shift & 15;\r
8714 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8715 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));\r
8716\r
8717 if(orig_shift != 0)\r
8718 {\r
8719 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8720\r
8721 if(shift != 0)\r
8722 {\r
8723 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8724 FLAG_C = (src << shift) >> 8;\r
8725 FLAG_N = NFLAG_16(res);\r
8726 FLAG_Z = res;\r
8727 FLAG_V = VFLAG_CLEAR;\r
8728 return;\r
8729 }\r
8730 FLAG_C = (src & 1)<<8;\r
8731 FLAG_N = NFLAG_16(src);\r
8732 FLAG_Z = src;\r
8733 FLAG_V = VFLAG_CLEAR;\r
8734 return;\r
8735 }\r
8736\r
8737 FLAG_C = CFLAG_CLEAR;\r
8738 FLAG_N = NFLAG_16(src);\r
8739 FLAG_Z = src;\r
8740 FLAG_V = VFLAG_CLEAR;\r
8741}\r
8742\r
8743\r
8744M68KMAKE_OP(rol, 32, r, .)\r
8745{\r
8746 uint* r_dst = &DY;\r
8747 uint orig_shift = DX & 0x3f;\r
8748 uint shift = orig_shift & 31;\r
8749 uint64 src = *r_dst;\r
8750 uint res = ROL_32(src, shift);\r
8751\r
8752 if(orig_shift != 0)\r
8753 {\r
8754 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8755\r
8756 *r_dst = res;\r
8757\r
c6a4c892 8758 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;\r
cc68a136 8759 FLAG_N = NFLAG_32(res);\r
8760 FLAG_Z = res;\r
8761 FLAG_V = VFLAG_CLEAR;\r
8762 return;\r
8763 }\r
8764\r
8765 FLAG_C = CFLAG_CLEAR;\r
8766 FLAG_N = NFLAG_32(src);\r
8767 FLAG_Z = src;\r
8768 FLAG_V = VFLAG_CLEAR;\r
8769}\r
8770\r
8771\r
8772M68KMAKE_OP(rol, 16, ., .)\r
8773{\r
8774 uint ea = M68KMAKE_GET_EA_AY_16;\r
8775 uint src = m68ki_read_16(ea);\r
8776 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));\r
8777\r
8778 m68ki_write_16(ea, res);\r
8779\r
8780 FLAG_N = NFLAG_16(res);\r
8781 FLAG_Z = res;\r
8782 FLAG_C = src >> 7;\r
8783 FLAG_V = VFLAG_CLEAR;\r
8784}\r
8785\r
8786\r
8787M68KMAKE_OP(roxr, 8, s, .)\r
8788{\r
8789 uint* r_dst = &DY;\r
8790 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8791 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8792 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8793\r
8794 if(shift != 0)\r
8795 USE_CYCLES(shift<<CYC_SHIFT);\r
8796\r
8797 FLAG_C = FLAG_X = res;\r
8798 res = MASK_OUT_ABOVE_8(res);\r
8799\r
8800 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8801\r
8802 FLAG_N = NFLAG_8(res);\r
8803 FLAG_Z = res;\r
8804 FLAG_V = VFLAG_CLEAR;\r
8805}\r
8806\r
8807\r
8808M68KMAKE_OP(roxr, 16, s, .)\r
8809{\r
8810 uint* r_dst = &DY;\r
8811 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8812 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8813 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8814\r
8815 if(shift != 0)\r
8816 USE_CYCLES(shift<<CYC_SHIFT);\r
8817\r
8818 FLAG_C = FLAG_X = res >> 8;\r
8819 res = MASK_OUT_ABOVE_16(res);\r
8820\r
8821 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8822\r
8823 FLAG_N = NFLAG_16(res);\r
8824 FLAG_Z = res;\r
8825 FLAG_V = VFLAG_CLEAR;\r
8826}\r
8827\r
8828\r
8829M68KMAKE_OP(roxr, 32, s, .)\r
8830{\r
8831#if M68K_USE_64_BIT\r
8832\r
8833 uint* r_dst = &DY;\r
8834 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8835 uint64 src = *r_dst;\r
8836 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8837\r
8838 if(shift != 0)\r
8839 USE_CYCLES(shift<<CYC_SHIFT);\r
8840\r
8841 res = ROR_33_64(res, shift);\r
8842\r
8843 FLAG_C = FLAG_X = res >> 24;\r
8844 res = MASK_OUT_ABOVE_32(res);\r
8845\r
8846 *r_dst = res;\r
8847\r
8848 FLAG_N = NFLAG_32(res);\r
8849 FLAG_Z = res;\r
8850 FLAG_V = VFLAG_CLEAR;\r
8851\r
8852#else\r
8853\r
8854 uint* r_dst = &DY;\r
8855 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8856 uint src = *r_dst;\r
8857 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8858 uint new_x_flag = src & (1 << (shift - 1));\r
8859\r
8860 if(shift != 0)\r
8861 USE_CYCLES(shift<<CYC_SHIFT);\r
8862\r
8863 *r_dst = res;\r
8864\r
8865 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
8866 FLAG_N = NFLAG_32(res);\r
8867 FLAG_Z = res;\r
8868 FLAG_V = VFLAG_CLEAR;\r
8869\r
8870#endif\r
8871}\r
8872\r
8873\r
8874M68KMAKE_OP(roxr, 8, r, .)\r
8875{\r
8876 uint* r_dst = &DY;\r
8877 uint orig_shift = DX & 0x3f;\r
8878\r
8879 if(orig_shift != 0)\r
8880 {\r
8881 uint shift = orig_shift % 9;\r
8882 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8883 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8884\r
8885 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8886\r
8887 FLAG_C = FLAG_X = res;\r
8888 res = MASK_OUT_ABOVE_8(res);\r
8889\r
8890 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8891 FLAG_N = NFLAG_8(res);\r
8892 FLAG_Z = res;\r
8893 FLAG_V = VFLAG_CLEAR;\r
8894 return;\r
8895 }\r
8896\r
8897 FLAG_C = FLAG_X;\r
8898 FLAG_N = NFLAG_8(*r_dst);\r
8899 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
8900 FLAG_V = VFLAG_CLEAR;\r
8901}\r
8902\r
8903\r
8904M68KMAKE_OP(roxr, 16, r, .)\r
8905{\r
8906 uint* r_dst = &DY;\r
8907 uint orig_shift = DX & 0x3f;\r
8908\r
8909 if(orig_shift != 0)\r
8910 {\r
8911 uint shift = orig_shift % 17;\r
8912 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8913 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8914\r
8915 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8916\r
8917 FLAG_C = FLAG_X = res >> 8;\r
8918 res = MASK_OUT_ABOVE_16(res);\r
8919\r
8920 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8921 FLAG_N = NFLAG_16(res);\r
8922 FLAG_Z = res;\r
8923 FLAG_V = VFLAG_CLEAR;\r
8924 return;\r
8925 }\r
8926\r
8927 FLAG_C = FLAG_X;\r
8928 FLAG_N = NFLAG_16(*r_dst);\r
8929 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
8930 FLAG_V = VFLAG_CLEAR;\r
8931}\r
8932\r
8933\r
8934M68KMAKE_OP(roxr, 32, r, .)\r
8935{\r
8936#if M68K_USE_64_BIT\r
8937\r
8938 uint* r_dst = &DY;\r
8939 uint orig_shift = DX & 0x3f;\r
8940\r
8941 if(orig_shift != 0)\r
8942 {\r
8943 uint shift = orig_shift % 33;\r
8944 uint64 src = *r_dst;\r
8945 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8946\r
8947 res = ROR_33_64(res, shift);\r
8948\r
8949 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8950\r
8951 FLAG_C = FLAG_X = res >> 24;\r
8952 res = MASK_OUT_ABOVE_32(res);\r
8953\r
8954 *r_dst = res;\r
8955 FLAG_N = NFLAG_32(res);\r
8956 FLAG_Z = res;\r
8957 FLAG_V = VFLAG_CLEAR;\r
8958 return;\r
8959 }\r
8960\r
8961 FLAG_C = FLAG_X;\r
8962 FLAG_N = NFLAG_32(*r_dst);\r
8963 FLAG_Z = *r_dst;\r
8964 FLAG_V = VFLAG_CLEAR;\r
8965\r
8966#else\r
8967\r
8968 uint* r_dst = &DY;\r
8969 uint orig_shift = DX & 0x3f;\r
8970 uint shift = orig_shift % 33;\r
8971 uint src = *r_dst;\r
8972 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8973 uint new_x_flag = src & (1 << (shift - 1));\r
8974\r
8975 if(orig_shift != 0)\r
8976 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8977\r
8978 if(shift != 0)\r
8979 {\r
8980 *r_dst = res;\r
8981 FLAG_X = (new_x_flag != 0)<<8;\r
8982 }\r
8983 else\r
8984 res = src;\r
8985 FLAG_C = FLAG_X;\r
8986 FLAG_N = NFLAG_32(res);\r
8987 FLAG_Z = res;\r
8988 FLAG_V = VFLAG_CLEAR;\r
8989\r
8990#endif\r
8991}\r
8992\r
8993\r
8994M68KMAKE_OP(roxr, 16, ., .)\r
8995{\r
8996 uint ea = M68KMAKE_GET_EA_AY_16;\r
8997 uint src = m68ki_read_16(ea);\r
8998 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);\r
8999\r
9000 FLAG_C = FLAG_X = res >> 8;\r
9001 res = MASK_OUT_ABOVE_16(res);\r
9002\r
9003 m68ki_write_16(ea, res);\r
9004\r
9005 FLAG_N = NFLAG_16(res);\r
9006 FLAG_Z = res;\r
9007 FLAG_V = VFLAG_CLEAR;\r
9008}\r
9009\r
9010\r
9011M68KMAKE_OP(roxl, 8, s, .)\r
9012{\r
9013 uint* r_dst = &DY;\r
9014 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9015 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9016 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9017\r
9018 if(shift != 0)\r
9019 USE_CYCLES(shift<<CYC_SHIFT);\r
9020\r
9021 FLAG_C = FLAG_X = res;\r
9022 res = MASK_OUT_ABOVE_8(res);\r
9023\r
9024 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9025\r
9026 FLAG_N = NFLAG_8(res);\r
9027 FLAG_Z = res;\r
9028 FLAG_V = VFLAG_CLEAR;\r
9029}\r
9030\r
9031\r
9032M68KMAKE_OP(roxl, 16, s, .)\r
9033{\r
9034 uint* r_dst = &DY;\r
9035 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9036 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9037 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9038\r
9039 if(shift != 0)\r
9040 USE_CYCLES(shift<<CYC_SHIFT);\r
9041\r
9042 FLAG_C = FLAG_X = res >> 8;\r
9043 res = MASK_OUT_ABOVE_16(res);\r
9044\r
9045 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9046\r
9047 FLAG_N = NFLAG_16(res);\r
9048 FLAG_Z = res;\r
9049 FLAG_V = VFLAG_CLEAR;\r
9050}\r
9051\r
9052\r
9053M68KMAKE_OP(roxl, 32, s, .)\r
9054{\r
9055#if M68K_USE_64_BIT\r
9056\r
9057 uint* r_dst = &DY;\r
9058 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9059 uint64 src = *r_dst;\r
9060 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9061\r
9062 if(shift != 0)\r
9063 USE_CYCLES(shift<<CYC_SHIFT);\r
9064\r
9065 res = ROL_33_64(res, shift);\r
9066\r
9067 FLAG_C = FLAG_X = res >> 24;\r
9068 res = MASK_OUT_ABOVE_32(res);\r
9069\r
9070 *r_dst = res;\r
9071\r
9072 FLAG_N = NFLAG_32(res);\r
9073 FLAG_Z = res;\r
9074 FLAG_V = VFLAG_CLEAR;\r
9075\r
9076#else\r
9077\r
9078 uint* r_dst = &DY;\r
9079 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9080 uint src = *r_dst;\r
9081 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9082 uint new_x_flag = src & (1 << (32 - shift));\r
9083\r
9084 if(shift != 0)\r
9085 USE_CYCLES(shift<<CYC_SHIFT);\r
9086\r
9087 *r_dst = res;\r
9088\r
9089 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
9090 FLAG_N = NFLAG_32(res);\r
9091 FLAG_Z = res;\r
9092 FLAG_V = VFLAG_CLEAR;\r
9093\r
9094#endif\r
9095}\r
9096\r
9097\r
9098M68KMAKE_OP(roxl, 8, r, .)\r
9099{\r
9100 uint* r_dst = &DY;\r
9101 uint orig_shift = DX & 0x3f;\r
9102\r
9103\r
9104 if(orig_shift != 0)\r
9105 {\r
9106 uint shift = orig_shift % 9;\r
9107 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9108 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9109\r
9110 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9111\r
9112 FLAG_C = FLAG_X = res;\r
9113 res = MASK_OUT_ABOVE_8(res);\r
9114\r
9115 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9116 FLAG_N = NFLAG_8(res);\r
9117 FLAG_Z = res;\r
9118 FLAG_V = VFLAG_CLEAR;\r
9119 return;\r
9120 }\r
9121\r
9122 FLAG_C = FLAG_X;\r
9123 FLAG_N = NFLAG_8(*r_dst);\r
9124 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
9125 FLAG_V = VFLAG_CLEAR;\r
9126}\r
9127\r
9128\r
9129M68KMAKE_OP(roxl, 16, r, .)\r
9130{\r
9131 uint* r_dst = &DY;\r
9132 uint orig_shift = DX & 0x3f;\r
9133\r
9134 if(orig_shift != 0)\r
9135 {\r
9136 uint shift = orig_shift % 17;\r
9137 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9138 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9139\r
9140 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9141\r
9142 FLAG_C = FLAG_X = res >> 8;\r
9143 res = MASK_OUT_ABOVE_16(res);\r
9144\r
9145 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9146 FLAG_N = NFLAG_16(res);\r
9147 FLAG_Z = res;\r
9148 FLAG_V = VFLAG_CLEAR;\r
9149 return;\r
9150 }\r
9151\r
9152 FLAG_C = FLAG_X;\r
9153 FLAG_N = NFLAG_16(*r_dst);\r
9154 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
9155 FLAG_V = VFLAG_CLEAR;\r
9156}\r
9157\r
9158\r
9159M68KMAKE_OP(roxl, 32, r, .)\r
9160{\r
9161#if M68K_USE_64_BIT\r
9162\r
9163 uint* r_dst = &DY;\r
9164 uint orig_shift = DX & 0x3f;\r
9165\r
9166 if(orig_shift != 0)\r
9167 {\r
9168 uint shift = orig_shift % 33;\r
9169 uint64 src = *r_dst;\r
9170 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9171\r
9172 res = ROL_33_64(res, shift);\r
9173\r
9174 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9175\r
9176 FLAG_C = FLAG_X = res >> 24;\r
9177 res = MASK_OUT_ABOVE_32(res);\r
9178\r
9179 *r_dst = res;\r
9180 FLAG_N = NFLAG_32(res);\r
9181 FLAG_Z = res;\r
9182 FLAG_V = VFLAG_CLEAR;\r
9183 return;\r
9184 }\r
9185\r
9186 FLAG_C = FLAG_X;\r
9187 FLAG_N = NFLAG_32(*r_dst);\r
9188 FLAG_Z = *r_dst;\r
9189 FLAG_V = VFLAG_CLEAR;\r
9190\r
9191#else\r
9192\r
9193 uint* r_dst = &DY;\r
9194 uint orig_shift = DX & 0x3f;\r
9195 uint shift = orig_shift % 33;\r
9196 uint src = *r_dst;\r
9197 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9198 uint new_x_flag = src & (1 << (32 - shift));\r
9199\r
9200 if(orig_shift != 0)\r
9201 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9202\r
9203 if(shift != 0)\r
9204 {\r
9205 *r_dst = res;\r
9206 FLAG_X = (new_x_flag != 0)<<8;\r
9207 }\r
9208 else\r
9209 res = src;\r
9210 FLAG_C = FLAG_X;\r
9211 FLAG_N = NFLAG_32(res);\r
9212 FLAG_Z = res;\r
9213 FLAG_V = VFLAG_CLEAR;\r
9214\r
9215#endif\r
9216}\r
9217\r
9218\r
9219M68KMAKE_OP(roxl, 16, ., .)\r
9220{\r
9221 uint ea = M68KMAKE_GET_EA_AY_16;\r
9222 uint src = m68ki_read_16(ea);\r
9223 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);\r
9224\r
9225 FLAG_C = FLAG_X = res >> 8;\r
9226 res = MASK_OUT_ABOVE_16(res);\r
9227\r
9228 m68ki_write_16(ea, res);\r
9229\r
9230 FLAG_N = NFLAG_16(res);\r
9231 FLAG_Z = res;\r
9232 FLAG_V = VFLAG_CLEAR;\r
9233}\r
9234\r
9235\r
9236M68KMAKE_OP(rtd, 32, ., .)\r
9237{\r
9238 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
9239 {\r
9240 uint new_pc = m68ki_pull_32();\r
9241\r
9242 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9243 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
9244 m68ki_jump(new_pc);\r
9245 return;\r
9246 }\r
9247 m68ki_exception_illegal();\r
9248}\r
9249\r
9250\r
9251M68KMAKE_OP(rte, 32, ., .)\r
9252{\r
9253 if(FLAG_S)\r
9254 {\r
9255 uint new_sr;\r
9256 uint new_pc;\r
9257 uint format_word;\r
9258\r
9259 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */\r
9260 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9261\r
9262 if(CPU_TYPE_IS_000(CPU_TYPE))\r
9263 {\r
9264 new_sr = m68ki_pull_16();\r
9265 new_pc = m68ki_pull_32();\r
9266 m68ki_jump(new_pc);\r
9267 m68ki_set_sr(new_sr);\r
9268\r
9269 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9270 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9271\r
9272 return;\r
9273 }\r
9274\r
9275 if(CPU_TYPE_IS_010(CPU_TYPE))\r
9276 {\r
9277 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9278 if(format_word == 0)\r
9279 {\r
9280 new_sr = m68ki_pull_16();\r
9281 new_pc = m68ki_pull_32();\r
9282 m68ki_fake_pull_16(); /* format word */\r
9283 m68ki_jump(new_pc);\r
9284 m68ki_set_sr(new_sr);\r
9285 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9286 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9287 return;\r
9288 }\r
9289 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9290 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9291 /* Not handling bus fault (9) */\r
9292 m68ki_exception_format_error();\r
9293 return;\r
9294 }\r
9295\r
9296 /* Otherwise it's 020 */\r
9297rte_loop:\r
9298 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9299 switch(format_word)\r
9300 {\r
9301 case 0: /* Normal */\r
9302 new_sr = m68ki_pull_16();\r
9303 new_pc = m68ki_pull_32();\r
9304 m68ki_fake_pull_16(); /* format word */\r
9305 m68ki_jump(new_pc);\r
9306 m68ki_set_sr(new_sr);\r
9307 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9308 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9309 return;\r
9310 case 1: /* Throwaway */\r
9311 new_sr = m68ki_pull_16();\r
9312 m68ki_fake_pull_32(); /* program counter */\r
9313 m68ki_fake_pull_16(); /* format word */\r
9314 m68ki_set_sr_noint(new_sr);\r
9315 goto rte_loop;\r
9316 case 2: /* Trap */\r
9317 new_sr = m68ki_pull_16();\r
9318 new_pc = m68ki_pull_32();\r
9319 m68ki_fake_pull_16(); /* format word */\r
9320 m68ki_fake_pull_32(); /* address */\r
9321 m68ki_jump(new_pc);\r
9322 m68ki_set_sr(new_sr);\r
9323 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9324 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9325 return;\r
9326 }\r
9327 /* Not handling long or short bus fault */\r
9328 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9329 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9330 m68ki_exception_format_error();\r
9331 return;\r
9332 }\r
9333 m68ki_exception_privilege_violation();\r
9334}\r
9335\r
9336\r
9337M68KMAKE_OP(rtm, 32, ., .)\r
9338{\r
9339 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
9340 {\r
9341 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9342 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
9343 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
9344 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
9345 return;\r
9346 }\r
9347 m68ki_exception_illegal();\r
9348}\r
9349\r
9350\r
9351M68KMAKE_OP(rtr, 32, ., .)\r
9352{\r
9353 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9354 m68ki_set_ccr(m68ki_pull_16());\r
9355 m68ki_jump(m68ki_pull_32());\r
9356}\r
9357\r
9358\r
9359M68KMAKE_OP(rts, 32, ., .)\r
9360{\r
9361 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9362 m68ki_jump(m68ki_pull_32());\r
9363}\r
9364\r
9365\r
9366M68KMAKE_OP(sbcd, 8, rr, .)\r
9367{\r
9368 uint* r_dst = &DX;\r
9369 uint src = DY;\r
9370 uint dst = *r_dst;\r
9371 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
c6e1e977 9372 uint corf = 0;\r
cc68a136 9373\r
c6e1e977 9374 if(res > 0xf)\r
9375 corf = 6;\r
cc68a136 9376 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
c6e1e977 9377 FLAG_V = res; /* Undefined V behavior */\r
9378 if(res > 0xff)\r
cc68a136 9379 {\r
9380 res += 0xa0;\r
9381 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9382 }\r
c6e1e977 9383 else if(res < corf)\r
9384 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9385 else\r
c6e1e977 9386 FLAG_X = FLAG_C = 0;\r
cc68a136 9387\r
c6e1e977 9388 res = MASK_OUT_ABOVE_8(res - corf);\r
cc68a136 9389\r
c6e1e977 9390 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9391 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
cc68a136 9392 FLAG_Z |= res;\r
9393\r
9394 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9395}\r
9396\r
9397\r
9398M68KMAKE_OP(sbcd, 8, mm, ax7)\r
9399{\r
9400 uint src = OPER_AY_PD_8();\r
9401 uint ea = EA_A7_PD_8();\r
9402 uint dst = m68ki_read_8(ea);\r
9403 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
c6e1e977 9404 uint corf = 0;\r
cc68a136 9405\r
c6e1e977 9406 if(res > 0xf)\r
9407 corf = 6;\r
cc68a136 9408 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
c6e1e977 9409 FLAG_V = res; /* Undefined V behavior */\r
9410 if(res > 0xff)\r
cc68a136 9411 {\r
9412 res += 0xa0;\r
9413 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9414 }\r
c6e1e977 9415 else if(res < corf)\r
9416 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9417 else\r
c6e1e977 9418 FLAG_X = FLAG_C = 0;\r
cc68a136 9419\r
c6e1e977 9420 res = MASK_OUT_ABOVE_8(res - corf);\r
cc68a136 9421\r
c6e1e977 9422 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9423 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
cc68a136 9424 FLAG_Z |= res;\r
9425\r
9426 m68ki_write_8(ea, res);\r
9427}\r
9428\r
9429\r
9430M68KMAKE_OP(sbcd, 8, mm, ay7)\r
9431{\r
9432 uint src = OPER_A7_PD_8();\r
9433 uint ea = EA_AX_PD_8();\r
9434 uint dst = m68ki_read_8(ea);\r
9435 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
c6e1e977 9436 uint corf = 0;\r
cc68a136 9437\r
c6e1e977 9438 if(res > 0xf)\r
9439 corf = 6;\r
cc68a136 9440 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
c6e1e977 9441 FLAG_V = res; /* Undefined V behavior */\r
9442 if(res > 0xff)\r
cc68a136 9443 {\r
9444 res += 0xa0;\r
9445 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9446 }\r
c6e1e977 9447 else if(res < corf)\r
9448 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9449 else\r
c6e1e977 9450 FLAG_X = FLAG_C = 0;\r
cc68a136 9451\r
c6e1e977 9452 res = MASK_OUT_ABOVE_8(res - corf);\r
cc68a136 9453\r
c6e1e977 9454 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9455 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
cc68a136 9456 FLAG_Z |= res;\r
9457\r
9458 m68ki_write_8(ea, res);\r
9459}\r
9460\r
9461\r
9462M68KMAKE_OP(sbcd, 8, mm, axy7)\r
9463{\r
9464 uint src = OPER_A7_PD_8();\r
9465 uint ea = EA_A7_PD_8();\r
9466 uint dst = m68ki_read_8(ea);\r
9467 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
c6e1e977 9468 uint corf = 0;\r
cc68a136 9469\r
c6e1e977 9470 if(res > 0xf)\r
9471 corf = 6;\r
cc68a136 9472 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
c6e1e977 9473 FLAG_V = res; /* Undefined V behavior */\r
9474 if(res > 0xff)\r
cc68a136 9475 {\r
9476 res += 0xa0;\r
9477 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9478 }\r
c6e1e977 9479 else if(res < corf)\r
9480 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9481 else\r
c6e1e977 9482 FLAG_X = FLAG_C = 0;\r
cc68a136 9483\r
c6e1e977 9484 res = MASK_OUT_ABOVE_8(res - corf);\r
cc68a136 9485\r
c6e1e977 9486 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9487 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
cc68a136 9488 FLAG_Z |= res;\r
9489\r
9490 m68ki_write_8(ea, res);\r
9491}\r
9492\r
9493\r
9494M68KMAKE_OP(sbcd, 8, mm, .)\r
9495{\r
9496 uint src = OPER_AY_PD_8();\r
9497 uint ea = EA_AX_PD_8();\r
9498 uint dst = m68ki_read_8(ea);\r
9499 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
c6e1e977 9500 uint corf = 0;\r
cc68a136 9501\r
c6e1e977 9502 if(res > 0xf)\r
9503 corf = 6;\r
cc68a136 9504 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
c6e1e977 9505 FLAG_V = res; /* Undefined V behavior */\r
9506 if(res > 0xff)\r
cc68a136 9507 {\r
9508 res += 0xa0;\r
9509 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9510 }\r
c6e1e977 9511 else if(res < corf)\r
9512 FLAG_X = FLAG_C = CFLAG_SET;\r
cc68a136 9513 else\r
c6e1e977 9514 FLAG_X = FLAG_C = 0;\r
cc68a136 9515\r
c6e1e977 9516 res = MASK_OUT_ABOVE_8(res - corf);\r
cc68a136 9517\r
c6e1e977 9518 FLAG_V &= ~res; /* Undefined V behavior part II */\r
9519 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
cc68a136 9520 FLAG_Z |= res;\r
9521\r
9522 m68ki_write_8(ea, res);\r
9523}\r
9524\r
9525\r
9526M68KMAKE_OP(st, 8, ., d)\r
9527{\r
9528 DY |= 0xff;\r
9529}\r
9530\r
9531\r
9532M68KMAKE_OP(st, 8, ., .)\r
9533{\r
9534 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);\r
9535}\r
9536\r
9537\r
9538M68KMAKE_OP(sf, 8, ., d)\r
9539{\r
9540 DY &= 0xffffff00;\r
9541}\r
9542\r
9543\r
9544M68KMAKE_OP(sf, 8, ., .)\r
9545{\r
9546 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
9547}\r
9548\r
9549\r
9550M68KMAKE_OP(scc, 8, ., d)\r
9551{\r
9552 if(M68KMAKE_CC)\r
9553 {\r
9554 DY |= 0xff;\r
9555 USE_CYCLES(CYC_SCC_R_TRUE);\r
9556 return;\r
9557 }\r
9558 DY &= 0xffffff00;\r
9559}\r
9560\r
9561\r
9562M68KMAKE_OP(scc, 8, ., .)\r
9563{\r
9564 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);\r
9565}\r
9566\r
9567\r
9568M68KMAKE_OP(stop, 0, ., .)\r
9569{\r
9570 if(FLAG_S)\r
9571 {\r
9572 uint new_sr = OPER_I_16();\r
9573 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9574 CPU_STOPPED |= STOP_LEVEL_STOP;\r
9575 m68ki_set_sr(new_sr);\r
9576 m68ki_remaining_cycles = 0;\r
9577 return;\r
9578 }\r
9579 m68ki_exception_privilege_violation();\r
9580}\r
9581\r
9582\r
9583M68KMAKE_OP(sub, 8, er, d)\r
9584{\r
9585 uint* r_dst = &DX;\r
9586 uint src = MASK_OUT_ABOVE_8(DY);\r
9587 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9588 uint res = dst - src;\r
9589\r
9590 FLAG_N = NFLAG_8(res);\r
9591 FLAG_X = FLAG_C = CFLAG_8(res);\r
9592 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9593 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9594\r
9595 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9596}\r
9597\r
9598\r
9599M68KMAKE_OP(sub, 8, er, .)\r
9600{\r
9601 uint* r_dst = &DX;\r
9602 uint src = M68KMAKE_GET_OPER_AY_8;\r
9603 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9604 uint res = dst - src;\r
9605\r
9606 FLAG_N = NFLAG_8(res);\r
9607 FLAG_X = FLAG_C = CFLAG_8(res);\r
9608 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9609 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9610\r
9611 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9612}\r
9613\r
9614\r
9615M68KMAKE_OP(sub, 16, er, d)\r
9616{\r
9617 uint* r_dst = &DX;\r
9618 uint src = MASK_OUT_ABOVE_16(DY);\r
9619 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9620 uint res = dst - src;\r
9621\r
9622 FLAG_N = NFLAG_16(res);\r
9623 FLAG_X = FLAG_C = CFLAG_16(res);\r
9624 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9625 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9626\r
9627 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9628}\r
9629\r
9630\r
9631M68KMAKE_OP(sub, 16, er, a)\r
9632{\r
9633 uint* r_dst = &DX;\r
9634 uint src = MASK_OUT_ABOVE_16(AY);\r
9635 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9636 uint res = dst - src;\r
9637\r
9638 FLAG_N = NFLAG_16(res);\r
9639 FLAG_X = FLAG_C = CFLAG_16(res);\r
9640 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9641 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9642\r
9643 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9644}\r
9645\r
9646\r
9647M68KMAKE_OP(sub, 16, er, .)\r
9648{\r
9649 uint* r_dst = &DX;\r
9650 uint src = M68KMAKE_GET_OPER_AY_16;\r
9651 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9652 uint res = dst - src;\r
9653\r
9654 FLAG_N = NFLAG_16(res);\r
9655 FLAG_X = FLAG_C = CFLAG_16(res);\r
9656 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9657 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9658\r
9659 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9660}\r
9661\r
9662\r
9663M68KMAKE_OP(sub, 32, er, d)\r
9664{\r
9665 uint* r_dst = &DX;\r
9666 uint src = DY;\r
9667 uint dst = *r_dst;\r
9668 uint res = dst - src;\r
9669\r
9670 FLAG_N = NFLAG_32(res);\r
9671 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9672 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9673 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9674\r
9675 *r_dst = FLAG_Z;\r
9676}\r
9677\r
9678\r
9679M68KMAKE_OP(sub, 32, er, a)\r
9680{\r
9681 uint* r_dst = &DX;\r
9682 uint src = AY;\r
9683 uint dst = *r_dst;\r
9684 uint res = dst - src;\r
9685\r
9686 FLAG_N = NFLAG_32(res);\r
9687 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9688 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9689 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9690\r
9691 *r_dst = FLAG_Z;\r
9692}\r
9693\r
9694\r
9695M68KMAKE_OP(sub, 32, er, .)\r
9696{\r
9697 uint* r_dst = &DX;\r
9698 uint src = M68KMAKE_GET_OPER_AY_32;\r
9699 uint dst = *r_dst;\r
9700 uint res = dst - src;\r
9701\r
9702 FLAG_N = NFLAG_32(res);\r
9703 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9704 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9705 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9706\r
9707 *r_dst = FLAG_Z;\r
9708}\r
9709\r
9710\r
9711M68KMAKE_OP(sub, 8, re, .)\r
9712{\r
9713 uint ea = M68KMAKE_GET_EA_AY_8;\r
9714 uint src = MASK_OUT_ABOVE_8(DX);\r
9715 uint dst = m68ki_read_8(ea);\r
9716 uint res = dst - src;\r
9717\r
9718 FLAG_N = NFLAG_8(res);\r
9719 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9720 FLAG_X = FLAG_C = CFLAG_8(res);\r
9721 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9722\r
9723 m68ki_write_8(ea, FLAG_Z);\r
9724}\r
9725\r
9726\r
9727M68KMAKE_OP(sub, 16, re, .)\r
9728{\r
9729 uint ea = M68KMAKE_GET_EA_AY_16;\r
9730 uint src = MASK_OUT_ABOVE_16(DX);\r
9731 uint dst = m68ki_read_16(ea);\r
9732 uint res = dst - src;\r
9733\r
9734 FLAG_N = NFLAG_16(res);\r
9735 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9736 FLAG_X = FLAG_C = CFLAG_16(res);\r
9737 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9738\r
9739 m68ki_write_16(ea, FLAG_Z);\r
9740}\r
9741\r
9742\r
9743M68KMAKE_OP(sub, 32, re, .)\r
9744{\r
9745 uint ea = M68KMAKE_GET_EA_AY_32;\r
9746 uint src = DX;\r
9747 uint dst = m68ki_read_32(ea);\r
9748 uint res = dst - src;\r
9749\r
9750 FLAG_N = NFLAG_32(res);\r
9751 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9752 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9753 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9754\r
9755 m68ki_write_32(ea, FLAG_Z);\r
9756}\r
9757\r
9758\r
9759M68KMAKE_OP(suba, 16, ., d)\r
9760{\r
9761 uint* r_dst = &AX;\r
9762\r
9763 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));\r
9764}\r
9765\r
9766\r
9767M68KMAKE_OP(suba, 16, ., a)\r
9768{\r
9769 uint* r_dst = &AX;\r
9770\r
9771 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));\r
9772}\r
9773\r
9774\r
9775M68KMAKE_OP(suba, 16, ., .)\r
9776{\r
9777 uint* r_dst = &AX;\r
c6a4c892 9778 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
cc68a136 9779\r
c6a4c892 9780 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);\r
cc68a136 9781}\r
9782\r
9783\r
9784M68KMAKE_OP(suba, 32, ., d)\r
9785{\r
9786 uint* r_dst = &AX;\r
9787\r
9788 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);\r
9789}\r
9790\r
9791\r
9792M68KMAKE_OP(suba, 32, ., a)\r
9793{\r
9794 uint* r_dst = &AX;\r
9795\r
9796 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);\r
9797}\r
9798\r
9799\r
9800M68KMAKE_OP(suba, 32, ., .)\r
9801{\r
9802 uint* r_dst = &AX;\r
3335750a 9803 uint src = M68KMAKE_GET_OPER_AY_32; // notaz\r
cc68a136 9804\r
3335750a 9805 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);\r
cc68a136 9806}\r
9807\r
9808\r
9809M68KMAKE_OP(subi, 8, ., d)\r
9810{\r
9811 uint* r_dst = &DY;\r
9812 uint src = OPER_I_8();\r
9813 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9814 uint res = dst - src;\r
9815\r
9816 FLAG_N = NFLAG_8(res);\r
9817 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9818 FLAG_X = FLAG_C = CFLAG_8(res);\r
9819 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9820\r
9821 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9822}\r
9823\r
9824\r
9825M68KMAKE_OP(subi, 8, ., .)\r
9826{\r
9827 uint src = OPER_I_8();\r
9828 uint ea = M68KMAKE_GET_EA_AY_8;\r
9829 uint dst = m68ki_read_8(ea);\r
9830 uint res = dst - src;\r
9831\r
9832 FLAG_N = NFLAG_8(res);\r
9833 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9834 FLAG_X = FLAG_C = CFLAG_8(res);\r
9835 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9836\r
9837 m68ki_write_8(ea, FLAG_Z);\r
9838}\r
9839\r
9840\r
9841M68KMAKE_OP(subi, 16, ., d)\r
9842{\r
9843 uint* r_dst = &DY;\r
9844 uint src = OPER_I_16();\r
9845 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9846 uint res = dst - src;\r
9847\r
9848 FLAG_N = NFLAG_16(res);\r
9849 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9850 FLAG_X = FLAG_C = CFLAG_16(res);\r
9851 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9852\r
9853 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9854}\r
9855\r
9856\r
9857M68KMAKE_OP(subi, 16, ., .)\r
9858{\r
9859 uint src = OPER_I_16();\r
9860 uint ea = M68KMAKE_GET_EA_AY_16;\r
9861 uint dst = m68ki_read_16(ea);\r
9862 uint res = dst - src;\r
9863\r
9864 FLAG_N = NFLAG_16(res);\r
9865 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9866 FLAG_X = FLAG_C = CFLAG_16(res);\r
9867 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9868\r
9869 m68ki_write_16(ea, FLAG_Z);\r
9870}\r
9871\r
9872\r
9873M68KMAKE_OP(subi, 32, ., d)\r
9874{\r
9875 uint* r_dst = &DY;\r
9876 uint src = OPER_I_32();\r
9877 uint dst = *r_dst;\r
9878 uint res = dst - src;\r
9879\r
9880 FLAG_N = NFLAG_32(res);\r
9881 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9882 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9883 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9884\r
9885 *r_dst = FLAG_Z;\r
9886}\r
9887\r
9888\r
9889M68KMAKE_OP(subi, 32, ., .)\r
9890{\r
9891 uint src = OPER_I_32();\r
9892 uint ea = M68KMAKE_GET_EA_AY_32;\r
9893 uint dst = m68ki_read_32(ea);\r
9894 uint res = dst - src;\r
9895\r
9896 FLAG_N = NFLAG_32(res);\r
9897 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9898 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9899 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9900\r
9901 m68ki_write_32(ea, FLAG_Z);\r
9902}\r
9903\r
9904\r
9905M68KMAKE_OP(subq, 8, ., d)\r
9906{\r
9907 uint* r_dst = &DY;\r
9908 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9909 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9910 uint res = dst - src;\r
9911\r
9912 FLAG_N = NFLAG_8(res);\r
9913 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9914 FLAG_X = FLAG_C = CFLAG_8(res);\r
9915 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9916\r
9917 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9918}\r
9919\r
9920\r
9921M68KMAKE_OP(subq, 8, ., .)\r
9922{\r
9923 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9924 uint ea = M68KMAKE_GET_EA_AY_8;\r
9925 uint dst = m68ki_read_8(ea);\r
9926 uint res = dst - src;\r
9927\r
9928 FLAG_N = NFLAG_8(res);\r
9929 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9930 FLAG_X = FLAG_C = CFLAG_8(res);\r
9931 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9932\r
9933 m68ki_write_8(ea, FLAG_Z);\r
9934}\r
9935\r
9936\r
9937M68KMAKE_OP(subq, 16, ., d)\r
9938{\r
9939 uint* r_dst = &DY;\r
9940 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9941 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9942 uint res = dst - src;\r
9943\r
9944 FLAG_N = NFLAG_16(res);\r
9945 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9946 FLAG_X = FLAG_C = CFLAG_16(res);\r
9947 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9948\r
9949 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9950}\r
9951\r
9952\r
9953M68KMAKE_OP(subq, 16, ., a)\r
9954{\r
9955 uint* r_dst = &AY;\r
9956\r
9957 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
9958}\r
9959\r
9960\r
9961M68KMAKE_OP(subq, 16, ., .)\r
9962{\r
9963 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9964 uint ea = M68KMAKE_GET_EA_AY_16;\r
9965 uint dst = m68ki_read_16(ea);\r
9966 uint res = dst - src;\r
9967\r
9968 FLAG_N = NFLAG_16(res);\r
9969 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9970 FLAG_X = FLAG_C = CFLAG_16(res);\r
9971 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9972\r
9973 m68ki_write_16(ea, FLAG_Z);\r
9974}\r
9975\r
9976\r
9977M68KMAKE_OP(subq, 32, ., d)\r
9978{\r
9979 uint* r_dst = &DY;\r
9980 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9981 uint dst = *r_dst;\r
9982 uint res = dst - src;\r
9983\r
9984 FLAG_N = NFLAG_32(res);\r
9985 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9986 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9987 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9988\r
9989 *r_dst = FLAG_Z;\r
9990}\r
9991\r
9992\r
9993M68KMAKE_OP(subq, 32, ., a)\r
9994{\r
9995 uint* r_dst = &AY;\r
9996\r
9997 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
9998}\r
9999\r
10000\r
10001M68KMAKE_OP(subq, 32, ., .)\r
10002{\r
10003 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
10004 uint ea = M68KMAKE_GET_EA_AY_32;\r
10005 uint dst = m68ki_read_32(ea);\r
10006 uint res = dst - src;\r
10007\r
10008 FLAG_N = NFLAG_32(res);\r
10009 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
10010 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10011 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10012\r
10013 m68ki_write_32(ea, FLAG_Z);\r
10014}\r
10015\r
10016\r
10017M68KMAKE_OP(subx, 8, rr, .)\r
10018{\r
10019 uint* r_dst = &DX;\r
10020 uint src = MASK_OUT_ABOVE_8(DY);\r
10021 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
10022 uint res = dst - src - XFLAG_AS_1();\r
10023\r
10024 FLAG_N = NFLAG_8(res);\r
10025 FLAG_X = FLAG_C = CFLAG_8(res);\r
10026 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10027\r
10028 res = MASK_OUT_ABOVE_8(res);\r
10029 FLAG_Z |= res;\r
10030\r
10031 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
10032}\r
10033\r
10034\r
10035M68KMAKE_OP(subx, 16, rr, .)\r
10036{\r
10037 uint* r_dst = &DX;\r
10038 uint src = MASK_OUT_ABOVE_16(DY);\r
10039 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
10040 uint res = dst - src - XFLAG_AS_1();\r
10041\r
10042 FLAG_N = NFLAG_16(res);\r
10043 FLAG_X = FLAG_C = CFLAG_16(res);\r
10044 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10045\r
10046 res = MASK_OUT_ABOVE_16(res);\r
10047 FLAG_Z |= res;\r
10048\r
10049 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
10050}\r
10051\r
10052\r
10053M68KMAKE_OP(subx, 32, rr, .)\r
10054{\r
10055 uint* r_dst = &DX;\r
10056 uint src = DY;\r
10057 uint dst = *r_dst;\r
10058 uint res = dst - src - XFLAG_AS_1();\r
10059\r
10060 FLAG_N = NFLAG_32(res);\r
10061 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10062 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10063\r
10064 res = MASK_OUT_ABOVE_32(res);\r
10065 FLAG_Z |= res;\r
10066\r
10067 *r_dst = res;\r
10068}\r
10069\r
10070\r
10071M68KMAKE_OP(subx, 8, mm, ax7)\r
10072{\r
10073 uint src = OPER_AY_PD_8();\r
10074 uint ea = EA_A7_PD_8();\r
10075 uint dst = m68ki_read_8(ea);\r
10076 uint res = dst - src - XFLAG_AS_1();\r
10077\r
10078 FLAG_N = NFLAG_8(res);\r
10079 FLAG_X = FLAG_C = CFLAG_8(res);\r
10080 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10081\r
10082 res = MASK_OUT_ABOVE_8(res);\r
10083 FLAG_Z |= res;\r
10084\r
10085 m68ki_write_8(ea, res);\r
10086}\r
10087\r
10088\r
10089M68KMAKE_OP(subx, 8, mm, ay7)\r
10090{\r
10091 uint src = OPER_A7_PD_8();\r
10092 uint ea = EA_AX_PD_8();\r
10093 uint dst = m68ki_read_8(ea);\r
10094 uint res = dst - src - XFLAG_AS_1();\r
10095\r
10096 FLAG_N = NFLAG_8(res);\r
10097 FLAG_X = FLAG_C = CFLAG_8(res);\r
10098 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10099\r
10100 res = MASK_OUT_ABOVE_8(res);\r
10101 FLAG_Z |= res;\r
10102\r
10103 m68ki_write_8(ea, res);\r
10104}\r
10105\r
10106\r
10107M68KMAKE_OP(subx, 8, mm, axy7)\r
10108{\r
10109 uint src = OPER_A7_PD_8();\r
10110 uint ea = EA_A7_PD_8();\r
10111 uint dst = m68ki_read_8(ea);\r
10112 uint res = dst - src - XFLAG_AS_1();\r
10113\r
10114 FLAG_N = NFLAG_8(res);\r
10115 FLAG_X = FLAG_C = CFLAG_8(res);\r
10116 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10117\r
10118 res = MASK_OUT_ABOVE_8(res);\r
10119 FLAG_Z |= res;\r
10120\r
10121 m68ki_write_8(ea, res);\r
10122}\r
10123\r
10124\r
10125M68KMAKE_OP(subx, 8, mm, .)\r
10126{\r
10127 uint src = OPER_AY_PD_8();\r
10128 uint ea = EA_AX_PD_8();\r
10129 uint dst = m68ki_read_8(ea);\r
10130 uint res = dst - src - XFLAG_AS_1();\r
10131\r
10132 FLAG_N = NFLAG_8(res);\r
10133 FLAG_X = FLAG_C = CFLAG_8(res);\r
10134 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10135\r
10136 res = MASK_OUT_ABOVE_8(res);\r
10137 FLAG_Z |= res;\r
10138\r
10139 m68ki_write_8(ea, res);\r
10140}\r
10141\r
10142\r
10143M68KMAKE_OP(subx, 16, mm, .)\r
10144{\r
10145 uint src = OPER_AY_PD_16();\r
10146 uint ea = EA_AX_PD_16();\r
10147 uint dst = m68ki_read_16(ea);\r
10148 uint res = dst - src - XFLAG_AS_1();\r
10149\r
10150 FLAG_N = NFLAG_16(res);\r
10151 FLAG_X = FLAG_C = CFLAG_16(res);\r
10152 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10153\r
10154 res = MASK_OUT_ABOVE_16(res);\r
10155 FLAG_Z |= res;\r
10156\r
10157 m68ki_write_16(ea, res);\r
10158}\r
10159\r
10160\r
10161M68KMAKE_OP(subx, 32, mm, .)\r
10162{\r
10163 uint src = OPER_AY_PD_32();\r
10164 uint ea = EA_AX_PD_32();\r
10165 uint dst = m68ki_read_32(ea);\r
10166 uint res = dst - src - XFLAG_AS_1();\r
10167\r
10168 FLAG_N = NFLAG_32(res);\r
10169 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10170 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10171\r
10172 res = MASK_OUT_ABOVE_32(res);\r
10173 FLAG_Z |= res;\r
10174\r
10175 m68ki_write_32(ea, res);\r
10176}\r
10177\r
10178\r
10179M68KMAKE_OP(swap, 32, ., .)\r
10180{\r
10181 uint* r_dst = &DY;\r
10182\r
10183 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);\r
10184 *r_dst = (*r_dst>>16) | FLAG_Z;\r
10185\r
10186 FLAG_Z = *r_dst;\r
10187 FLAG_N = NFLAG_32(*r_dst);\r
10188 FLAG_C = CFLAG_CLEAR;\r
10189 FLAG_V = VFLAG_CLEAR;\r
10190}\r
10191\r
10192\r
10193M68KMAKE_OP(tas, 8, ., d)\r
10194{\r
10195 uint* r_dst = &DY;\r
10196\r
10197 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
10198 FLAG_N = NFLAG_8(*r_dst);\r
10199 FLAG_V = VFLAG_CLEAR;\r
10200 FLAG_C = CFLAG_CLEAR;\r
10201 *r_dst |= 0x80;\r
10202}\r
10203\r
10204\r
10205M68KMAKE_OP(tas, 8, ., .)\r
10206{\r
10207 uint ea = M68KMAKE_GET_EA_AY_8;\r
10208 uint dst = m68ki_read_8(ea);\r
c6a4c892 10209 uint allow_writeback;\r
cc68a136 10210\r
10211 FLAG_Z = dst;\r
10212 FLAG_N = NFLAG_8(dst);\r
10213 FLAG_V = VFLAG_CLEAR;\r
10214 FLAG_C = CFLAG_CLEAR;\r
c6a4c892 10215\r
10216 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback\r
10217 disabled in order to function properly. Some Amiga software may also rely\r
10218 on this, but only when accessing specific addresses so additional functionality\r
10219 will be needed. */\r
10220 allow_writeback = m68ki_tas_callback();\r
10221\r
10222 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);\r
cc68a136 10223}\r
10224\r
10225\r
10226M68KMAKE_OP(trap, 0, ., .)\r
10227{\r
10228 /* Trap#n stacks exception frame type 0 */\r
10229 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */\r
10230}\r
10231\r
10232\r
10233M68KMAKE_OP(trapt, 0, ., .)\r
10234{\r
10235 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10236 {\r
10237 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10238 return;\r
10239 }\r
10240 m68ki_exception_illegal();\r
10241}\r
10242\r
10243\r
10244M68KMAKE_OP(trapt, 16, ., .)\r
10245{\r
10246 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10247 {\r
10248 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10249 return;\r
10250 }\r
10251 m68ki_exception_illegal();\r
10252}\r
10253\r
10254\r
10255M68KMAKE_OP(trapt, 32, ., .)\r
10256{\r
10257 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10258 {\r
10259 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10260 return;\r
10261 }\r
10262 m68ki_exception_illegal();\r
10263}\r
10264\r
10265\r
10266M68KMAKE_OP(trapf, 0, ., .)\r
10267{\r
10268 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10269 {\r
10270 return;\r
10271 }\r
10272 m68ki_exception_illegal();\r
10273}\r
10274\r
10275\r
10276M68KMAKE_OP(trapf, 16, ., .)\r
10277{\r
10278 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10279 {\r
10280 REG_PC += 2;\r
10281 return;\r
10282 }\r
10283 m68ki_exception_illegal();\r
10284}\r
10285\r
10286\r
10287M68KMAKE_OP(trapf, 32, ., .)\r
10288{\r
10289 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10290 {\r
10291 REG_PC += 4;\r
10292 return;\r
10293 }\r
10294 m68ki_exception_illegal();\r
10295}\r
10296\r
10297\r
10298M68KMAKE_OP(trapcc, 0, ., .)\r
10299{\r
10300 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10301 {\r
10302 if(M68KMAKE_CC)\r
10303 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10304 return;\r
10305 }\r
10306 m68ki_exception_illegal();\r
10307}\r
10308\r
10309\r
10310M68KMAKE_OP(trapcc, 16, ., .)\r
10311{\r
10312 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10313 {\r
10314 if(M68KMAKE_CC)\r
10315 {\r
10316 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10317 return;\r
10318 }\r
10319 REG_PC += 2;\r
10320 return;\r
10321 }\r
10322 m68ki_exception_illegal();\r
10323}\r
10324\r
10325\r
10326M68KMAKE_OP(trapcc, 32, ., .)\r
10327{\r
10328 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10329 {\r
10330 if(M68KMAKE_CC)\r
10331 {\r
10332 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10333 return;\r
10334 }\r
10335 REG_PC += 4;\r
10336 return;\r
10337 }\r
10338 m68ki_exception_illegal();\r
10339}\r
10340\r
10341\r
10342M68KMAKE_OP(trapv, 0, ., .)\r
10343{\r
10344 if(COND_VC())\r
10345 {\r
10346 return;\r
10347 }\r
10348 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10349}\r
10350\r
10351\r
10352M68KMAKE_OP(tst, 8, ., d)\r
10353{\r
10354 uint res = MASK_OUT_ABOVE_8(DY);\r
10355\r
10356 FLAG_N = NFLAG_8(res);\r
10357 FLAG_Z = res;\r
10358 FLAG_V = VFLAG_CLEAR;\r
10359 FLAG_C = CFLAG_CLEAR;\r
10360}\r
10361\r
10362\r
10363M68KMAKE_OP(tst, 8, ., .)\r
10364{\r
10365 uint res = M68KMAKE_GET_OPER_AY_8;\r
10366\r
10367 FLAG_N = NFLAG_8(res);\r
10368 FLAG_Z = res;\r
10369 FLAG_V = VFLAG_CLEAR;\r
10370 FLAG_C = CFLAG_CLEAR;\r
10371}\r
10372\r
10373\r
10374M68KMAKE_OP(tst, 8, ., pcdi)\r
10375{\r
10376 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10377 {\r
10378 uint res = OPER_PCDI_8();\r
10379\r
10380 FLAG_N = NFLAG_8(res);\r
10381 FLAG_Z = res;\r
10382 FLAG_V = VFLAG_CLEAR;\r
10383 FLAG_C = CFLAG_CLEAR;\r
10384 return;\r
10385 }\r
10386 m68ki_exception_illegal();\r
10387}\r
10388\r
10389\r
10390M68KMAKE_OP(tst, 8, ., pcix)\r
10391{\r
10392 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10393 {\r
10394 uint res = OPER_PCIX_8();\r
10395\r
10396 FLAG_N = NFLAG_8(res);\r
10397 FLAG_Z = res;\r
10398 FLAG_V = VFLAG_CLEAR;\r
10399 FLAG_C = CFLAG_CLEAR;\r
10400 return;\r
10401 }\r
10402 m68ki_exception_illegal();\r
10403}\r
10404\r
10405\r
10406M68KMAKE_OP(tst, 8, ., i)\r
10407{\r
10408 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10409 {\r
10410 uint res = OPER_I_8();\r
10411\r
10412 FLAG_N = NFLAG_8(res);\r
10413 FLAG_Z = res;\r
10414 FLAG_V = VFLAG_CLEAR;\r
10415 FLAG_C = CFLAG_CLEAR;\r
10416 return;\r
10417 }\r
10418 m68ki_exception_illegal();\r
10419}\r
10420\r
10421\r
10422M68KMAKE_OP(tst, 16, ., d)\r
10423{\r
10424 uint res = MASK_OUT_ABOVE_16(DY);\r
10425\r
10426 FLAG_N = NFLAG_16(res);\r
10427 FLAG_Z = res;\r
10428 FLAG_V = VFLAG_CLEAR;\r
10429 FLAG_C = CFLAG_CLEAR;\r
10430}\r
10431\r
10432\r
10433M68KMAKE_OP(tst, 16, ., a)\r
10434{\r
10435 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10436 {\r
10437 uint res = MAKE_INT_16(AY);\r
10438\r
10439 FLAG_N = NFLAG_16(res);\r
10440 FLAG_Z = res;\r
10441 FLAG_V = VFLAG_CLEAR;\r
10442 FLAG_C = CFLAG_CLEAR;\r
10443 return;\r
10444 }\r
10445 m68ki_exception_illegal();\r
10446}\r
10447\r
10448\r
10449M68KMAKE_OP(tst, 16, ., .)\r
10450{\r
10451 uint res = M68KMAKE_GET_OPER_AY_16;\r
10452\r
10453 FLAG_N = NFLAG_16(res);\r
10454 FLAG_Z = res;\r
10455 FLAG_V = VFLAG_CLEAR;\r
10456 FLAG_C = CFLAG_CLEAR;\r
10457}\r
10458\r
10459\r
10460M68KMAKE_OP(tst, 16, ., pcdi)\r
10461{\r
10462 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10463 {\r
10464 uint res = OPER_PCDI_16();\r
10465\r
10466 FLAG_N = NFLAG_16(res);\r
10467 FLAG_Z = res;\r
10468 FLAG_V = VFLAG_CLEAR;\r
10469 FLAG_C = CFLAG_CLEAR;\r
10470 return;\r
10471 }\r
10472 m68ki_exception_illegal();\r
10473}\r
10474\r
10475\r
10476M68KMAKE_OP(tst, 16, ., pcix)\r
10477{\r
10478 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10479 {\r
10480 uint res = OPER_PCIX_16();\r
10481\r
10482 FLAG_N = NFLAG_16(res);\r
10483 FLAG_Z = res;\r
10484 FLAG_V = VFLAG_CLEAR;\r
10485 FLAG_C = CFLAG_CLEAR;\r
10486 return;\r
10487 }\r
10488 m68ki_exception_illegal();\r
10489}\r
10490\r
10491\r
10492M68KMAKE_OP(tst, 16, ., i)\r
10493{\r
10494 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10495 {\r
10496 uint res = OPER_I_16();\r
10497\r
10498 FLAG_N = NFLAG_16(res);\r
10499 FLAG_Z = res;\r
10500 FLAG_V = VFLAG_CLEAR;\r
10501 FLAG_C = CFLAG_CLEAR;\r
10502 return;\r
10503 }\r
10504 m68ki_exception_illegal();\r
10505}\r
10506\r
10507\r
10508M68KMAKE_OP(tst, 32, ., d)\r
10509{\r
10510 uint res = DY;\r
10511\r
10512 FLAG_N = NFLAG_32(res);\r
10513 FLAG_Z = res;\r
10514 FLAG_V = VFLAG_CLEAR;\r
10515 FLAG_C = CFLAG_CLEAR;\r
10516}\r
10517\r
10518\r
10519M68KMAKE_OP(tst, 32, ., a)\r
10520{\r
10521 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10522 {\r
10523 uint res = AY;\r
10524\r
10525 FLAG_N = NFLAG_32(res);\r
10526 FLAG_Z = res;\r
10527 FLAG_V = VFLAG_CLEAR;\r
10528 FLAG_C = CFLAG_CLEAR;\r
10529 return;\r
10530 }\r
10531 m68ki_exception_illegal();\r
10532}\r
10533\r
10534\r
10535M68KMAKE_OP(tst, 32, ., .)\r
10536{\r
10537 uint res = M68KMAKE_GET_OPER_AY_32;\r
10538\r
10539 FLAG_N = NFLAG_32(res);\r
10540 FLAG_Z = res;\r
10541 FLAG_V = VFLAG_CLEAR;\r
10542 FLAG_C = CFLAG_CLEAR;\r
10543}\r
10544\r
10545\r
10546M68KMAKE_OP(tst, 32, ., pcdi)\r
10547{\r
10548 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10549 {\r
10550 uint res = OPER_PCDI_32();\r
10551\r
10552 FLAG_N = NFLAG_32(res);\r
10553 FLAG_Z = res;\r
10554 FLAG_V = VFLAG_CLEAR;\r
10555 FLAG_C = CFLAG_CLEAR;\r
10556 return;\r
10557 }\r
10558 m68ki_exception_illegal();\r
10559}\r
10560\r
10561\r
10562M68KMAKE_OP(tst, 32, ., pcix)\r
10563{\r
10564 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10565 {\r
10566 uint res = OPER_PCIX_32();\r
10567\r
10568 FLAG_N = NFLAG_32(res);\r
10569 FLAG_Z = res;\r
10570 FLAG_V = VFLAG_CLEAR;\r
10571 FLAG_C = CFLAG_CLEAR;\r
10572 return;\r
10573 }\r
10574 m68ki_exception_illegal();\r
10575}\r
10576\r
10577\r
10578M68KMAKE_OP(tst, 32, ., i)\r
10579{\r
10580 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10581 {\r
10582 uint res = OPER_I_32();\r
10583\r
10584 FLAG_N = NFLAG_32(res);\r
10585 FLAG_Z = res;\r
10586 FLAG_V = VFLAG_CLEAR;\r
10587 FLAG_C = CFLAG_CLEAR;\r
10588 return;\r
10589 }\r
10590 m68ki_exception_illegal();\r
10591}\r
10592\r
10593\r
10594M68KMAKE_OP(unlk, 32, ., a7)\r
10595{\r
10596 REG_A[7] = m68ki_read_32(REG_A[7]);\r
10597}\r
10598\r
10599\r
10600M68KMAKE_OP(unlk, 32, ., .)\r
10601{\r
10602 uint* r_dst = &AY;\r
10603\r
10604 REG_A[7] = *r_dst;\r
10605 *r_dst = m68ki_pull_32();\r
10606}\r
10607\r
10608\r
10609M68KMAKE_OP(unpk, 16, rr, .)\r
10610{\r
10611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10612 {\r
10613 /* Note: DX and DY are reversed in Motorola's docs */\r
10614 uint src = DY;\r
10615 uint* r_dst = &DX;\r
10616\r
10617 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);\r
10618 return;\r
10619 }\r
10620 m68ki_exception_illegal();\r
10621}\r
10622\r
10623\r
10624M68KMAKE_OP(unpk, 16, mm, ax7)\r
10625{\r
10626 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10627 {\r
10628 /* Note: AX and AY are reversed in Motorola's docs */\r
10629 uint src = OPER_AY_PD_8();\r
10630 uint ea_dst;\r
10631\r
10632 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10633 ea_dst = EA_A7_PD_8();\r
10634 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10635 ea_dst = EA_A7_PD_8();\r
10636 m68ki_write_8(ea_dst, src & 0xff);\r
10637 return;\r
10638 }\r
10639 m68ki_exception_illegal();\r
10640}\r
10641\r
10642\r
10643M68KMAKE_OP(unpk, 16, mm, ay7)\r
10644{\r
10645 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10646 {\r
10647 /* Note: AX and AY are reversed in Motorola's docs */\r
10648 uint src = OPER_A7_PD_8();\r
10649 uint ea_dst;\r
10650\r
10651 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10652 ea_dst = EA_AX_PD_8();\r
10653 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10654 ea_dst = EA_AX_PD_8();\r
10655 m68ki_write_8(ea_dst, src & 0xff);\r
10656 return;\r
10657 }\r
10658 m68ki_exception_illegal();\r
10659}\r
10660\r
10661\r
10662M68KMAKE_OP(unpk, 16, mm, axy7)\r
10663{\r
10664 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10665 {\r
10666 uint src = OPER_A7_PD_8();\r
10667 uint ea_dst;\r
10668\r
10669 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10670 ea_dst = EA_A7_PD_8();\r
10671 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10672 ea_dst = EA_A7_PD_8();\r
10673 m68ki_write_8(ea_dst, src & 0xff);\r
10674 return;\r
10675 }\r
10676 m68ki_exception_illegal();\r
10677}\r
10678\r
10679\r
10680M68KMAKE_OP(unpk, 16, mm, .)\r
10681{\r
10682 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10683 {\r
10684 /* Note: AX and AY are reversed in Motorola's docs */\r
10685 uint src = OPER_AY_PD_8();\r
10686 uint ea_dst;\r
10687\r
10688 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10689 ea_dst = EA_AX_PD_8();\r
10690 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10691 ea_dst = EA_AX_PD_8();\r
10692 m68ki_write_8(ea_dst, src & 0xff);\r
10693 return;\r
10694 }\r
10695 m68ki_exception_illegal();\r
10696}\r
10697\r
10698\r
10699\r
10700XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
10701M68KMAKE_END\r
fast MegaDrive/MegaCD/32X emulator