e898de13 |
1 | /* |
2 | * vim:shiftwidth=2:expandtab |
3 | */ |
679af8a3 |
4 | #include <stdio.h> |
5 | #include <stdlib.h> |
6 | #include <assert.h> |
41397701 |
7 | |
f4bb5d6b |
8 | #include "../../pico/pico_int.h" |
679af8a3 |
9 | #include "sh2.h" |
10 | #include "compiler.h" |
11 | #include "../drc/cmn.h" |
12 | |
e898de13 |
13 | #ifndef DRC_DEBUG |
14 | #define DRC_DEBUG 0 |
15 | #endif |
16 | |
f4bb5d6b |
17 | #define dbg(l,...) { \ |
18 | if ((l) & DRC_DEBUG) \ |
19 | elprintf(EL_STATUS, ##__VA_ARGS__); \ |
20 | } |
21 | |
e898de13 |
22 | #if DRC_DEBUG |
23 | #include "mame/sh2dasm.h" |
24 | #include <platform/linux/host_dasm.h> |
25 | static int insns_compiled, hash_collisions, host_insn_count; |
26 | #endif |
27 | #if (DRC_DEBUG & 2) |
f4bb5d6b |
28 | static u8 *tcache_dsm_ptrs[3]; |
e898de13 |
29 | static char sh2dasm_buff[64]; |
f4bb5d6b |
30 | #define do_host_disasm(tcid) \ |
31 | host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \ |
32 | tcache_dsm_ptrs[tcid] = tcache_ptr |
33 | #else |
34 | #define do_host_disasm(x) |
e898de13 |
35 | #endif |
36 | |
679af8a3 |
37 | #define BLOCK_CYCLE_LIMIT 100 |
f4bb5d6b |
38 | #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) |
39 | |
40 | // we have 3 translation cache buffers, split from one drc/cmn buffer. |
41 | // BIOS shares tcache with data array because it's only used for init |
42 | // and can be discarded early |
43 | static const int tcache_sizes[3] = { |
44 | DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM |
45 | DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 |
46 | DRC_TCACHE_SIZE / 8, // ... slave |
47 | }; |
679af8a3 |
48 | |
f4bb5d6b |
49 | static u8 *tcache_bases[3]; |
50 | static u8 *tcache_ptrs[3]; |
51 | |
52 | // ptr for code emiters |
53 | static u8 *tcache_ptr; |
e898de13 |
54 | |
55 | #include "../drc/emit_x86.c" |
56 | |
679af8a3 |
57 | typedef enum { |
58 | SHR_R0 = 0, SHR_R15 = 15, |
59 | SHR_PC, SHR_PPC, SHR_PR, SHR_SR, |
60 | SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL, |
61 | } sh2_reg_e; |
62 | |
63 | typedef struct block_desc_ { |
64 | u32 addr; // SH2 PC address |
f4bb5d6b |
65 | u32 end_addr; // TODO rm? |
679af8a3 |
66 | void *tcache_ptr; // translated block for above PC |
f4bb5d6b |
67 | struct block_desc_ *next; // next block with the same PC hash |
68 | #if (DRC_DEBUG & 1) |
69 | int refcount; |
70 | #endif |
679af8a3 |
71 | } block_desc; |
72 | |
f4bb5d6b |
73 | static const int block_max_counts[3] = { |
74 | 4*1024, |
75 | 256, |
76 | 256, |
77 | }; |
78 | static block_desc *block_tables[3]; |
79 | static int block_counts[3]; |
679af8a3 |
80 | |
f4bb5d6b |
81 | // ROM hash table |
679af8a3 |
82 | #define MAX_HASH_ENTRIES 1024 |
83 | #define HASH_MASK (MAX_HASH_ENTRIES - 1) |
f4bb5d6b |
84 | static void **hash_table; |
679af8a3 |
85 | |
679af8a3 |
86 | extern void sh2_drc_entry(SH2 *sh2, void *block); |
87 | extern void sh2_drc_exit(void); |
88 | |
89 | // tmp |
90 | extern void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2, int opcode); |
e898de13 |
91 | static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2); |
679af8a3 |
92 | |
f4bb5d6b |
93 | static void flush_tcache(int tcid) |
94 | { |
95 | printf("tcache #%d flush! (%d/%d, bds %d/%d)\n", tcid, |
96 | tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], |
97 | block_counts[tcid], block_max_counts[tcid]); |
98 | |
99 | block_counts[tcid] = 0; |
100 | tcache_ptrs[tcid] = tcache_bases[tcid]; |
101 | if (tcid == 0) { // ROM, RAM |
102 | memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); |
103 | memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); |
104 | } |
105 | else |
106 | memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); |
107 | #if (DRC_DEBUG & 2) |
108 | tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; |
109 | #endif |
110 | } |
111 | |
679af8a3 |
112 | static void *dr_find_block(block_desc *tab, u32 addr) |
113 | { |
114 | for (tab = tab->next; tab != NULL; tab = tab->next) |
115 | if (tab->addr == addr) |
116 | break; |
117 | |
118 | if (tab != NULL) |
119 | return tab->tcache_ptr; |
120 | |
121 | printf("block miss for %08x\n", addr); |
122 | return NULL; |
123 | } |
124 | |
f4bb5d6b |
125 | static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id) |
679af8a3 |
126 | { |
f4bb5d6b |
127 | int *bcount = &block_counts[tcache_id]; |
679af8a3 |
128 | block_desc *bd; |
129 | |
f4bb5d6b |
130 | if (*bcount >= block_max_counts[tcache_id]) |
131 | return NULL; |
679af8a3 |
132 | |
f4bb5d6b |
133 | bd = &block_tables[tcache_id][*bcount]; |
679af8a3 |
134 | bd->addr = addr; |
135 | bd->tcache_ptr = tcache_ptr; |
f4bb5d6b |
136 | *blk_id = *bcount; |
137 | (*bcount)++; |
679af8a3 |
138 | |
139 | return bd; |
140 | } |
141 | |
142 | #define HASH_FUNC(hash_tab, addr) \ |
143 | ((block_desc **)(hash_tab))[(addr) & HASH_MASK] |
144 | |
145 | // --------------------------------------------------------------- |
146 | |
147 | static void emit_move_r_imm32(sh2_reg_e dst, u32 imm) |
41397701 |
148 | { |
679af8a3 |
149 | int host_dst = reg_map_g2h[dst]; |
150 | int tmp = 0; |
151 | |
152 | if (host_dst != -1) |
153 | tmp = host_dst; |
154 | emith_move_r_imm(tmp, imm); |
155 | if (host_dst == -1) |
156 | emith_ctx_write(tmp, dst * 4); |
157 | } |
158 | |
159 | static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) |
160 | { |
161 | int host_dst = reg_map_g2h[dst], host_src = reg_map_g2h[src]; |
162 | int tmp = 0; |
163 | |
164 | if (host_dst != -1 && host_src != -1) { |
165 | emith_move_r_r(host_dst, host_src); |
166 | return; |
167 | } |
168 | |
169 | if (host_src != -1) |
170 | tmp = host_src; |
171 | if (host_dst != -1) |
172 | tmp = host_dst; |
173 | |
174 | if (host_src == -1) |
175 | emith_ctx_read(tmp, src * 4); |
176 | if (host_dst == -1) |
177 | emith_ctx_write(tmp, dst * 4); |
178 | } |
179 | |
180 | static void emit_braf(sh2_reg_e reg, u32 pc) |
181 | { |
182 | int host_reg = reg_map_g2h[reg]; |
183 | if (host_reg == -1) { |
184 | emith_ctx_read(0, reg * 4); |
185 | } else |
186 | emith_move_r_r(0, host_reg); |
187 | emith_add_r_imm(0, pc); |
188 | |
e898de13 |
189 | emith_ctx_write(0, SHR_PPC * 4); |
679af8a3 |
190 | } |
191 | |
679af8a3 |
192 | /* |
193 | static int sh2_translate_op4(int op) |
194 | { |
195 | switch (op & 0x000f) |
196 | { |
197 | case 0x0b: |
198 | default: |
199 | emith_pass_arg(2, sh2, op); |
200 | emith_call(sh2_do_op); |
201 | break; |
202 | } |
203 | |
204 | return 0; |
205 | } |
206 | */ |
207 | |
e898de13 |
208 | #define DELAYED_OP \ |
209 | delayed_op = 2 |
210 | |
211 | #define CHECK_UNHANDLED_BITS(mask) { \ |
212 | if ((op & (mask)) != 0) \ |
213 | goto default_; \ |
214 | } |
215 | |
679af8a3 |
216 | static void *sh2_translate(SH2 *sh2, block_desc *other_block) |
217 | { |
f4bb5d6b |
218 | void *block_entry; |
679af8a3 |
219 | block_desc *this_block; |
41397701 |
220 | unsigned int pc = sh2->pc; |
e898de13 |
221 | int op, delayed_op = 0, test_irq = 0; |
f4bb5d6b |
222 | int tcache_id = 0, blkid = 0; |
679af8a3 |
223 | int cycles = 0; |
e898de13 |
224 | u32 tmp, tmp2; |
679af8a3 |
225 | |
f4bb5d6b |
226 | // validate PC |
227 | tmp = sh2->pc >> 29; |
228 | if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) { |
229 | printf("invalid PC, aborting: %08x\n", sh2->pc); |
230 | // FIXME: be less destructive |
231 | exit(1); |
232 | } |
233 | |
234 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
235 | // data_array, BIOS have separate tcache (shared) |
236 | tcache_id = 1 + sh2->is_slave; |
237 | } |
238 | |
239 | tcache_ptr = tcache_ptrs[tcache_id]; |
240 | this_block = dr_add_block(pc, tcache_id, &blkid); |
241 | |
242 | tmp = tcache_ptr - tcache_bases[tcache_id]; |
243 | if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) { |
244 | flush_tcache(tcache_id); |
245 | tcache_ptr = tcache_ptrs[tcache_id]; |
246 | other_block = NULL; // also gone too due to flush |
247 | this_block = dr_add_block(pc, tcache_id, &blkid); |
248 | } |
e898de13 |
249 | |
f4bb5d6b |
250 | this_block->next = other_block; |
251 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
252 | HASH_FUNC(hash_table, pc) = this_block; |
679af8a3 |
253 | |
f4bb5d6b |
254 | block_entry = tcache_ptr; |
e898de13 |
255 | #if (DRC_DEBUG & 1) |
f4bb5d6b |
256 | printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', |
257 | tcache_id, block_counts[tcache_id], pc, block_entry); |
e898de13 |
258 | if (other_block != NULL) { |
259 | printf(" hash collision with %08x\n", other_block->addr); |
260 | hash_collisions++; |
261 | } |
679af8a3 |
262 | #endif |
263 | |
e898de13 |
264 | while (cycles < BLOCK_CYCLE_LIMIT || delayed_op) |
679af8a3 |
265 | { |
e898de13 |
266 | if (delayed_op > 0) |
267 | delayed_op--; |
268 | |
2b2b46b0 |
269 | op = p32x_sh2_read16(pc, sh2); |
e898de13 |
270 | |
271 | #if (DRC_DEBUG & 3) |
272 | insns_compiled++; |
273 | #if (DRC_DEBUG & 2) |
274 | DasmSH2(sh2dasm_buff, pc, op); |
275 | printf("%08x %04x %s\n", pc, op, sh2dasm_buff); |
276 | #endif |
679af8a3 |
277 | #endif |
679af8a3 |
278 | |
279 | pc += 2; |
280 | cycles++; |
281 | |
282 | switch ((op >> 12) & 0x0f) |
283 | { |
284 | case 0x00: |
e898de13 |
285 | switch (op & 0x0f) { |
286 | case 0x03: |
287 | CHECK_UNHANDLED_BITS(0xd0); |
288 | // BRAF Rm 0000mmmm00100011 |
289 | // BSRF Rm 0000mmmm00000011 |
679af8a3 |
290 | DELAYED_OP; |
e898de13 |
291 | if (!(op & 0x20)) |
292 | emit_move_r_imm32(SHR_PR, pc + 2); |
293 | emit_braf((op >> 8) & 0x0f, pc + 2); |
679af8a3 |
294 | cycles++; |
e898de13 |
295 | goto end_op; |
296 | case 0x09: |
297 | CHECK_UNHANDLED_BITS(0xf0); |
298 | // NOP 0000000000001001 |
299 | goto end_op; |
300 | case 0x0b: |
301 | CHECK_UNHANDLED_BITS(0xd0); |
679af8a3 |
302 | DELAYED_OP; |
e898de13 |
303 | if (!(op & 0x20)) { |
304 | // RTS 0000000000001011 |
305 | emit_move_r_r(SHR_PPC, SHR_PR); |
306 | cycles++; |
307 | } else { |
308 | // RTE 0000000000101011 |
309 | //emit_move_r_r(SHR_PC, SHR_PR); |
310 | emit_move_r_imm32(SHR_PC, pc - 2); |
f4bb5d6b |
311 | emith_pass_arg_r(0, CONTEXT_REG); |
312 | emith_pass_arg_imm(1, op); |
e898de13 |
313 | emith_call(sh2_do_op); |
314 | emit_move_r_r(SHR_PPC, SHR_PC); |
315 | test_irq = 1; |
316 | cycles += 3; |
317 | } |
318 | goto end_op; |
679af8a3 |
319 | } |
320 | goto default_; |
321 | |
322 | case 0x04: |
e898de13 |
323 | switch (op & 0x0f) { |
324 | case 0x07: |
325 | if ((op & 0xf0) != 0) |
326 | goto default_; |
327 | // LDC.L @Rm+,SR 0100mmmm00000111 |
328 | test_irq = 1; |
329 | goto default_; |
330 | case 0x0b: |
331 | if ((op & 0xd0) != 0) |
332 | goto default_; |
333 | // JMP @Rm 0100mmmm00101011 |
334 | // JSR @Rm 0100mmmm00001011 |
679af8a3 |
335 | DELAYED_OP; |
e898de13 |
336 | if (!(op & 0x20)) |
337 | emit_move_r_imm32(SHR_PR, pc + 2); |
338 | emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f); |
679af8a3 |
339 | cycles++; |
e898de13 |
340 | goto end_op; |
341 | case 0x0e: |
342 | if ((op & 0xf0) != 0) |
343 | goto default_; |
344 | // LDC Rm,SR 0100mmmm00001110 |
345 | test_irq = 1; |
346 | goto default_; |
679af8a3 |
347 | } |
348 | goto default_; |
349 | |
e898de13 |
350 | case 0x08: |
679af8a3 |
351 | switch (op & 0x0f00) { |
352 | // BT/S label 10001101dddddddd |
353 | case 0x0d00: |
354 | // BF/S label 10001111dddddddd |
355 | case 0x0f00: |
356 | DELAYED_OP; |
357 | cycles--; |
679af8a3 |
358 | // fallthrough |
359 | // BT label 10001001dddddddd |
360 | case 0x0900: |
361 | // BF label 10001011dddddddd |
362 | case 0x0b00: |
679af8a3 |
363 | tmp = ((signed int)(op << 24) >> 23); |
e898de13 |
364 | tmp2 = delayed_op ? SHR_PPC : SHR_PC; |
365 | emit_move_r_imm32(tmp2, pc + (delayed_op ? 2 : 0)); |
366 | emith_test_t(); |
367 | EMIT_CONDITIONAL(emit_move_r_imm32(tmp2, pc + tmp + 2), (op & 0x0200) ? 1 : 0); |
368 | cycles += 2; |
369 | if (!delayed_op) |
370 | goto end_block; |
371 | goto end_op; |
679af8a3 |
372 | } |
373 | goto default_; |
679af8a3 |
374 | |
375 | case 0x0a: |
376 | // BRA label 1010dddddddddddd |
377 | DELAYED_OP; |
378 | do_bra: |
379 | tmp = ((signed int)(op << 20) >> 19); |
e898de13 |
380 | emit_move_r_imm32(SHR_PPC, pc + tmp + 2); |
679af8a3 |
381 | cycles++; |
e898de13 |
382 | break; |
679af8a3 |
383 | |
384 | case 0x0b: |
385 | // BSR label 1011dddddddddddd |
386 | DELAYED_OP; |
e898de13 |
387 | emit_move_r_imm32(SHR_PR, pc + 2); |
679af8a3 |
388 | goto do_bra; |
389 | |
390 | default: |
391 | default_: |
392 | emit_move_r_imm32(SHR_PC, pc - 2); |
f4bb5d6b |
393 | emith_pass_arg_r(0, CONTEXT_REG); |
394 | emith_pass_arg_imm(1, op); |
679af8a3 |
395 | emith_call(sh2_do_op); |
396 | break; |
397 | } |
398 | |
e898de13 |
399 | end_op: |
6add7875 |
400 | if (delayed_op == 1) |
e898de13 |
401 | emit_move_r_r(SHR_PC, SHR_PPC); |
6add7875 |
402 | |
e898de13 |
403 | if (test_irq && delayed_op != 2) { |
f4bb5d6b |
404 | emith_pass_arg_r(0, CONTEXT_REG); |
e898de13 |
405 | emith_call(sh2_test_irq); |
406 | break; |
407 | } |
6add7875 |
408 | if (delayed_op == 1) |
409 | break; |
e898de13 |
410 | |
f4bb5d6b |
411 | do_host_disasm(tcache_id); |
679af8a3 |
412 | } |
413 | |
414 | end_block: |
f4bb5d6b |
415 | this_block->end_addr = pc; |
416 | |
417 | // mark memory blocks as containing compiled code |
418 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
419 | // data array, BIOS |
420 | u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; |
421 | tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
422 | tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
423 | Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1; |
424 | for (++tmp; tmp < tmp2; tmp++) { |
425 | if (drcblk[tmp]) |
426 | break; // dont overwrite overlay block |
427 | drcblk[tmp] = blkid << 1; |
428 | } |
429 | } |
430 | else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM |
431 | tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
432 | tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
433 | Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1; |
434 | for (++tmp; tmp < tmp2; tmp++) { |
435 | if (Pico32xMem->drcblk_ram[tmp]) |
436 | break; |
437 | Pico32xMem->drcblk_ram[tmp] = blkid << 1; |
438 | } |
679af8a3 |
439 | } |
440 | |
441 | if (reg_map_g2h[SHR_SR] == -1) { |
442 | emith_ctx_sub(cycles << 12, SHR_SR * 4); |
443 | } else |
444 | emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12); |
445 | emith_jump(sh2_drc_exit); |
f4bb5d6b |
446 | tcache_ptrs[tcache_id] = tcache_ptr; |
447 | |
448 | do_host_disasm(tcache_id); |
449 | dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", |
450 | tcache_id, block_counts[tcache_id], |
451 | tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], |
452 | insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); |
453 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
454 | dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); |
679af8a3 |
455 | return block_entry; |
f4bb5d6b |
456 | /* |
679af8a3 |
457 | unimplemented: |
458 | // last op |
f4bb5d6b |
459 | do_host_disasm(tcache_id); |
679af8a3 |
460 | exit(1); |
f4bb5d6b |
461 | */ |
679af8a3 |
462 | } |
463 | |
464 | void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) |
465 | { |
466 | while (((signed int)sh2->sr >> 12) > 0) |
467 | { |
679af8a3 |
468 | void *block = NULL; |
f4bb5d6b |
469 | block_desc *bd = NULL; |
6add7875 |
470 | |
471 | // FIXME: must avoid doing it so often.. |
472 | sh2_test_irq(sh2); |
473 | |
f4bb5d6b |
474 | // we have full block id tables for data_array and RAM |
475 | // BIOS goes to data_array table too |
476 | if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
477 | int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; |
478 | if (blkid & 1) { |
479 | bd = &block_tables[1 + sh2->is_slave][blkid >> 1]; |
480 | block = bd->tcache_ptr; |
481 | } |
482 | } |
483 | // RAM |
484 | else if ((sh2->pc & 0xc6000000) == 0x06000000) { |
485 | int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; |
486 | if (blkid & 1) { |
487 | bd = &block_tables[0][blkid >> 1]; |
679af8a3 |
488 | block = bd->tcache_ptr; |
f4bb5d6b |
489 | } |
490 | } |
491 | // ROM |
492 | else if ((sh2->pc & 0xc6000000) == 0x02000000) { |
493 | bd = HASH_FUNC(hash_table, sh2->pc); |
494 | |
495 | if (bd != NULL) { |
496 | if (bd->addr == sh2->pc) |
497 | block = bd->tcache_ptr; |
498 | else |
499 | block = dr_find_block(bd, sh2->pc); |
500 | } |
679af8a3 |
501 | } |
502 | |
503 | if (block == NULL) |
504 | block = sh2_translate(sh2, bd); |
505 | |
f4bb5d6b |
506 | dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', |
507 | sh2->pc, block, (signed int)sh2->sr >> 12); |
508 | #if (DRC_DEBUG & 1) |
509 | if (bd != NULL) |
510 | bd->refcount++; |
679af8a3 |
511 | #endif |
512 | sh2_drc_entry(sh2, block); |
513 | } |
514 | } |
515 | |
f4bb5d6b |
516 | static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) |
517 | { |
518 | u16 id = *p >> 1; |
519 | block_desc *bd = btab + id; |
520 | |
521 | dbg(1, " killing block %08x", bd->addr); |
522 | bd->addr = bd->end_addr = 0; |
523 | |
524 | while (p > drcblk && (p[-1] >> 1) == id) |
525 | p--; |
526 | |
527 | // check for possible overlay block |
528 | if (p > 0 && p[-1] != 0) { |
529 | bd = btab + (p[-1] >> 1); |
530 | if (bd->addr <= a && a < bd->end_addr) |
531 | sh2_smc_rm_block(drcblk, p - 1, btab, a); |
532 | } |
533 | |
534 | do { |
535 | *p++ = 0; |
536 | } |
537 | while ((*p >> 1) == id); |
538 | } |
539 | |
540 | void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) |
541 | { |
542 | u16 *drcblk = Pico32xMem->drcblk_ram; |
543 | u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT); |
544 | |
545 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
546 | sh2_smc_rm_block(drcblk, p, block_tables[0], a); |
547 | } |
548 | |
549 | void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) |
550 | { |
551 | u16 *drcblk = Pico32xMem->drcblk_da[cpuid]; |
552 | u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT); |
553 | |
554 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
555 | sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a); |
556 | } |
557 | |
679af8a3 |
558 | void sh2_execute(SH2 *sh2, int cycles) |
559 | { |
560 | sh2->cycles_aim += cycles; |
561 | cycles = sh2->cycles_aim - sh2->cycles_done; |
562 | |
563 | // cycles are kept in SHR_SR unused bits (upper 20) |
564 | sh2->sr &= 0x3f3; |
565 | sh2->sr |= cycles << 12; |
566 | sh2_drc_dispatcher(sh2); |
567 | |
568 | sh2->cycles_done += cycles - ((signed int)sh2->sr >> 12); |
569 | } |
570 | |
e898de13 |
571 | static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2) |
679af8a3 |
572 | { |
6add7875 |
573 | if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f)) |
574 | { |
575 | if (sh2->pending_irl > sh2->pending_int_irq) |
576 | sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2); |
577 | else { |
578 | sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector); |
579 | sh2->pending_int_irq = 0; // auto-clear |
580 | sh2->pending_level = sh2->pending_irl; |
581 | } |
582 | } |
679af8a3 |
583 | } |
584 | |
f4bb5d6b |
585 | #if (DRC_DEBUG & 1) |
586 | static void block_stats(void) |
587 | { |
588 | int c, b, i, total = 0; |
589 | |
590 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
591 | for (i = 0; i < block_counts[b]; i++) |
592 | if (block_tables[b][i].addr != 0) |
593 | total += block_tables[b][i].refcount; |
594 | |
595 | for (c = 0; c < 10; c++) { |
596 | block_desc *blk, *maxb = NULL; |
597 | int max = 0; |
598 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) { |
599 | for (i = 0; i < block_counts[b]; i++) { |
600 | blk = &block_tables[b][i]; |
601 | if (blk->addr != 0 && blk->refcount > max) { |
602 | max = blk->refcount; |
603 | maxb = blk; |
604 | } |
605 | } |
606 | } |
607 | if (maxb == NULL) |
608 | break; |
609 | printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount, |
610 | (double)maxb->refcount / total * 100.0); |
611 | maxb->refcount = 0; |
612 | } |
613 | } |
614 | #endif |
615 | |
679af8a3 |
616 | int sh2_drc_init(SH2 *sh2) |
617 | { |
f4bb5d6b |
618 | if (block_tables[0] == NULL) { |
619 | int i, cnt; |
620 | cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2]; |
621 | block_tables[0] = calloc(cnt, sizeof(*block_tables[0])); |
622 | if (block_tables[0] == NULL) |
e898de13 |
623 | return -1; |
624 | |
f4bb5d6b |
625 | memset(block_counts, 0, sizeof(block_counts)); |
626 | tcache_bases[0] = tcache_ptrs[0] = tcache; |
627 | |
628 | for (i = 1; i < ARRAY_SIZE(block_tables); i++) { |
629 | block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1]; |
630 | tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1]; |
631 | } |
632 | |
633 | #if (DRC_DEBUG & 2) |
634 | for (i = 0; i < ARRAY_SIZE(block_tables); i++) |
635 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
636 | #endif |
e898de13 |
637 | #if (DRC_DEBUG & 1) |
638 | hash_collisions = 0; |
639 | #endif |
679af8a3 |
640 | } |
641 | |
f4bb5d6b |
642 | if (hash_table == NULL) { |
643 | hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); |
644 | if (hash_table == NULL) |
645 | return -1; |
646 | } |
41397701 |
647 | |
679af8a3 |
648 | return 0; |
41397701 |
649 | } |
650 | |
e898de13 |
651 | void sh2_drc_finish(SH2 *sh2) |
652 | { |
f4bb5d6b |
653 | if (block_tables[0] != NULL) { |
654 | #if (DRC_DEBUG & 1) |
655 | block_stats(); |
656 | #endif |
657 | free(block_tables[0]); |
658 | memset(block_tables, 0, sizeof(block_tables)); |
e898de13 |
659 | } |
660 | |
f4bb5d6b |
661 | if (hash_table != NULL) { |
662 | free(hash_table); |
663 | hash_table = NULL; |
664 | } |
e898de13 |
665 | } |