[picodrive.git] / cpu / sh2 / mame / sh2pico.c

#include "../sh2.h"

#ifdef DRC_CMP
#include "../compiler.c"
#define BUSY_LOOP_HACKS 0
#else
#define BUSY_LOOP_HACKS 1
#endif

// MAME types
#ifndef INT8
typedef signed char  INT8;
typedef signed short INT16;
typedef signed int   INT32;
typedef unsigned int   UINT32;
typedef unsigned short UINT16;
typedef unsigned char  UINT8;
#endif

#ifdef DRC_SH2

// this nasty conversion is needed for drc-expecting memhandlers
#define MAKE_READFUNC(name, cname) \
static inline unsigned int name(SH2 *sh2, unsigned int a) \
{ \
	unsigned int ret; \
	sh2->sr |= sh2->icount << 12; \
	ret = cname(a, sh2); \
	sh2->icount = (signed int)sh2->sr >> 12; \
	sh2->sr &= 0x3f3; \
	return ret; \
}

#define MAKE_WRITEFUNC(name, cname) \
static inline void name(SH2 *sh2, unsigned int a, unsigned int d) \
{ \
	sh2->sr |= sh2->icount << 12; \
	cname(a, d, sh2); \
	sh2->icount = (signed int)sh2->sr >> 12; \
	sh2->sr &= 0x3f3; \
}

MAKE_READFUNC(RB, p32x_sh2_read8)
MAKE_READFUNC(RW, p32x_sh2_read16)
MAKE_READFUNC(RL, p32x_sh2_read32)
MAKE_WRITEFUNC(WB, p32x_sh2_write8)
MAKE_WRITEFUNC(WW, p32x_sh2_write16)
MAKE_WRITEFUNC(WL, p32x_sh2_write32)

#else

#define RB(sh2, a) p32x_sh2_read8(a, sh2)
#define RW(sh2, a) p32x_sh2_read16(a, sh2)
#define RL(sh2, a) p32x_sh2_read32(a, sh2)
#define WB(sh2, a, d) p32x_sh2_write8(a, d, sh2)
#define WW(sh2, a, d) p32x_sh2_write16(a, d, sh2)
#define WL(sh2, a, d) p32x_sh2_write32(a, d, sh2)

#endif

// some stuff from sh2comn.h
#define T	0x00000001
#define S	0x00000002
#define I	0x000000f0
#define Q	0x00000100
#define M	0x00000200

#define AM	0xc7ffffff

#define FLAGS	(M|Q|I|S|T)

#define Rn	((opcode>>8)&15)
#define Rm	((opcode>>4)&15)

#define sh2_state SH2

extern void lprintf(const char *fmt, ...);
#define logerror lprintf

#ifdef SH2_STATS
static SH2 sh2_stats;
static unsigned int op_refs[0x10000];
# define LRN  1
# define LRM  2
# define LRNM (LRN|LRM)
# define rlog(rnm) {   \
  int op = opcode;     \
  if ((rnm) & LRN) {   \
    op &= ~0x0f00;     \
    sh2_stats.r[Rn]++; \
  }                    \
  if ((rnm) & LRM) {   \
    op &= ~0x00f0;     \
    sh2_stats.r[Rm]++; \
  }                    \
  op_refs[op]++;       \
}
# define rlog1(x) sh2_stats.r[x]++
# define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++
#else
# define rlog(x)
# define rlog1(...)
# define rlog2(...)
#endif

#include "sh2.c"

#ifndef DRC_CMP

int sh2_execute_interpreter(SH2 *sh2, int cycles)
{
	UINT32 opcode;

	sh2->icount = cycles;

	if (sh2->icount <= 0)
		goto out;

	do
	{
		if (sh2->delay)
		{
			sh2->ppc = sh2->delay;
			opcode = RW(sh2, sh2->delay);
			sh2->pc -= 2;
		}
		else
		{
			sh2->ppc = sh2->pc;
			opcode = RW(sh2, sh2->pc);
		}

		sh2->delay = 0;
		sh2->pc += 2;

		switch (opcode & ( 15 << 12))
		{
		case  0<<12: op0000(sh2, opcode); break;
		case  1<<12: op0001(sh2, opcode); break;
		case  2<<12: op0010(sh2, opcode); break;
		case  3<<12: op0011(sh2, opcode); break;
		case  4<<12: op0100(sh2, opcode); break;
		case  5<<12: op0101(sh2, opcode); break;
		case  6<<12: op0110(sh2, opcode); break;
		case  7<<12: op0111(sh2, opcode); break;
		case  8<<12: op1000(sh2, opcode); break;
		case  9<<12: op1001(sh2, opcode); break;
		case 10<<12: op1010(sh2, opcode); break;
		case 11<<12: op1011(sh2, opcode); break;
		case 12<<12: op1100(sh2, opcode); break;
		case 13<<12: op1101(sh2, opcode); break;
		case 14<<12: op1110(sh2, opcode); break;
		default: op1111(sh2, opcode); break;
		}

		sh2->icount--;

		if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
		{
			int level = sh2->pending_level;
			int vector = sh2->irq_callback(sh2, level);
			sh2_do_irq(sh2, level, vector);
			sh2->test_irq = 0;
		}

	}
	while (sh2->icount > 0 || sh2->delay);	/* can't interrupt before delay */

out:
	return sh2->icount;
}

#else // if DRC_CMP

int sh2_execute_interpreter(SH2 *sh2, int cycles)
{
	static unsigned int base_pc_[2] = { 0, 0 };
	static unsigned int end_pc_[2] = { 0, 0 };
	static unsigned char op_flags_[2][BLOCK_INSN_LIMIT];
	unsigned int *base_pc = &base_pc_[sh2->is_slave];
	unsigned int *end_pc = &end_pc_[sh2->is_slave];
	unsigned char *op_flags = op_flags_[sh2->is_slave];
	unsigned int pc_expect;
	UINT32 opcode;

	sh2->icount = sh2->cycles_timeslice = cycles;

	if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
	{
		int level = sh2->pending_level;
		int vector = sh2->irq_callback(sh2, level);
		sh2_do_irq(sh2, level, vector);
	}
	pc_expect = sh2->pc;

	if (sh2->icount <= 0)
		goto out;

	do
	{
		if (!sh2->delay) {
			if (sh2->pc < *base_pc || sh2->pc >= *end_pc) {
				*base_pc = sh2->pc;
				scan_block(*base_pc, sh2->is_slave,
					op_flags, end_pc, NULL);
			}
			if ((op_flags[(sh2->pc - *base_pc) / 2]
				& OF_BTARGET) || sh2->pc == *base_pc
				|| pc_expect != sh2->pc) // branched
			{
				pc_expect = sh2->pc;
				if (sh2->icount < 0)
					break;
			}

			do_sh2_trace(sh2, sh2->icount);
		}
		pc_expect += 2;

		if (sh2->delay)
		{
			sh2->ppc = sh2->delay;
			opcode = RW(sh2, sh2->delay);
			sh2->pc -= 2;
		}
		else
		{
			sh2->ppc = sh2->pc;
			opcode = RW(sh2, sh2->pc);
		}

		sh2->delay = 0;
		sh2->pc += 2;

		switch (opcode & ( 15 << 12))
		{
		case  0<<12: op0000(sh2, opcode); break;
		case  1<<12: op0001(sh2, opcode); break;
		case  2<<12: op0010(sh2, opcode); break;
		case  3<<12: op0011(sh2, opcode); break;
		case  4<<12: op0100(sh2, opcode); break;
		case  5<<12: op0101(sh2, opcode); break;
		case  6<<12: op0110(sh2, opcode); break;
		case  7<<12: op0111(sh2, opcode); break;
		case  8<<12: op1000(sh2, opcode); break;
		case  9<<12: op1001(sh2, opcode); break;
		case 10<<12: op1010(sh2, opcode); break;
		case 11<<12: op1011(sh2, opcode); break;
		case 12<<12: op1100(sh2, opcode); break;
		case 13<<12: op1101(sh2, opcode); break;
		case 14<<12: op1110(sh2, opcode); break;
		default: op1111(sh2, opcode); break;
		}

		sh2->icount--;

		if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
		{
			int level = sh2->pending_level;
			int vector = sh2->irq_callback(sh2, level);
			sh2_do_irq(sh2, level, vector);
			sh2->test_irq = 0;
		}

	}
	while (1);

out:
	return sh2->icount;
}

#endif // DRC_CMP

#ifdef SH2_STATS
#include <stdio.h>
#include <string.h>
#include "sh2dasm.h"

void sh2_dump_stats(void)
{
	static const char *rnames[] = {
		"R0", "R1", "R2",  "R3",  "R4",  "R5",  "R6",  "R7",
		"R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP",
		"PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL"
	};
	long long total;
	char buff[64];
	int u, i;

	// dump reg usage
	total = 0;
	for (i = 0; i < 24; i++)
		total += sh2_stats.r[i];

	for (i = 0; i < 24; i++) {
		if (i == 16 || i == 17 || i == 19)
			continue;
		printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total,
			rnames[i], sh2_stats.r[i]);
	}

	memset(&sh2_stats, 0, sizeof(sh2_stats));

	// dump ops
	printf("\n");
	total = 0;
	for (i = 0; i < 0x10000; i++)
		total += op_refs[i];

	for (u = 0; u < 16; u++) {
		int max = 0, op = 0;
		for (i = 0; i < 0x10000; i++) {
			if (op_refs[i] > max) {
				max = op_refs[i];
				op = i;
			}
		}
		DasmSH2(buff, 0, op);
		printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total,
			op_refs[op], buff);
		op_refs[op] = 0;
	}
	memset(op_refs, 0, sizeof(op_refs));
}
#endif
Commit	Line	Data
41397701	1	#include "../sh2.h"
405dfdd7	2
00faec9c	3	#ifdef DRC_CMP
00faec9c	4	#include "../compiler.c"
405dfdd7	5	#define BUSY_LOOP_HACKS 0
	6	#else
	7	#define BUSY_LOOP_HACKS 1
00faec9c	8	#endif
eaa10a6e	9
eaa10a6e	10	// MAME types
00faec9c	11	#ifndef INT8
eaa10a6e	12	typedef signed char INT8;
	13	typedef signed short INT16;
	14	typedef signed int INT32;
	15	typedef unsigned int UINT32;
	16	typedef unsigned short UINT16;
	17	typedef unsigned char UINT8;
00faec9c	18	#endif
eaa10a6e	19
0185b677	20	#ifdef DRC_SH2
	21
	22	// this nasty conversion is needed for drc-expecting memhandlers
	23	#define MAKE_READFUNC(name, cname) \
	24	static inline unsigned int name(SH2 *sh2, unsigned int a) \
	25	{ \
	26	unsigned int ret; \
	27	sh2->sr \|= sh2->icount << 12; \
	28	ret = cname(a, sh2); \
	29	sh2->icount = (signed int)sh2->sr >> 12; \
	30	sh2->sr &= 0x3f3; \
	31	return ret; \
	32	}
	33
	34	#define MAKE_WRITEFUNC(name, cname) \
	35	static inline void name(SH2 *sh2, unsigned int a, unsigned int d) \
	36	{ \
	37	sh2->sr \|= sh2->icount << 12; \
	38	cname(a, d, sh2); \
	39	sh2->icount = (signed int)sh2->sr >> 12; \
	40	sh2->sr &= 0x3f3; \
	41	}
	42
	43	MAKE_READFUNC(RB, p32x_sh2_read8)
	44	MAKE_READFUNC(RW, p32x_sh2_read16)
	45	MAKE_READFUNC(RL, p32x_sh2_read32)
	46	MAKE_WRITEFUNC(WB, p32x_sh2_write8)
	47	MAKE_WRITEFUNC(WW, p32x_sh2_write16)
	48	MAKE_WRITEFUNC(WL, p32x_sh2_write32)
	49
	50	#else
	51
	52	#define RB(sh2, a) p32x_sh2_read8(a, sh2)
	53	#define RW(sh2, a) p32x_sh2_read16(a, sh2)
	54	#define RL(sh2, a) p32x_sh2_read32(a, sh2)
	55	#define WB(sh2, a, d) p32x_sh2_write8(a, d, sh2)
	56	#define WW(sh2, a, d) p32x_sh2_write16(a, d, sh2)
	57	#define WL(sh2, a, d) p32x_sh2_write32(a, d, sh2)
	58
	59	#endif
eaa10a6e	60
	61	// some stuff from sh2comn.h
	62	#define T 0x00000001
	63	#define S 0x00000002
	64	#define I 0x000000f0
	65	#define Q 0x00000100
	66	#define M 0x00000200
	67
	68	#define AM 0xc7ffffff
	69
	70	#define FLAGS (M\|Q\|I\|S\|T)
	71
	72	#define Rn ((opcode>>8)&15)
	73	#define Rm ((opcode>>4)&15)
	74
f4c0720c	75	#define sh2_state SH2
	76
	77	extern void lprintf(const char *fmt, ...);
	78	#define logerror lprintf
1d7a28a7	79
71f68165	80	#ifdef SH2_STATS
	81	static SH2 sh2_stats;
	82	static unsigned int op_refs[0x10000];
	83	# define LRN 1
	84	# define LRM 2
	85	# define LRNM (LRN\|LRM)
	86	# define rlog(rnm) { \
	87	int op = opcode; \
	88	if ((rnm) & LRN) { \
	89	op &= ~0x0f00; \
	90	sh2_stats.r[Rn]++; \
	91	} \
	92	if ((rnm) & LRM) { \
	93	op &= ~0x00f0; \
	94	sh2_stats.r[Rm]++; \
	95	} \
	96	op_refs[op]++; \
	97	}
	98	# define rlog1(x) sh2_stats.r[x]++
	99	# define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++
	100	#else
	101	# define rlog(x)
	102	# define rlog1(...)
	103	# define rlog2(...)
	104	#endif
	105
41397701	106	#include "sh2.c"
1d7a28a7	107
405dfdd7	108	#ifndef DRC_CMP
405dfdd7	109
0185b677	110	int sh2_execute_interpreter(SH2 *sh2, int cycles)
405dfdd7	111	{
	112	UINT32 opcode;
	113
0185b677	114	sh2->icount = cycles;
405dfdd7	115
	116	if (sh2->icount <= 0)
	117	goto out;
	118
	119	do
	120	{
	121	if (sh2->delay)
	122	{
	123	sh2->ppc = sh2->delay;
	124	opcode = RW(sh2, sh2->delay);
	125	sh2->pc -= 2;
	126	}
	127	else
	128	{
	129	sh2->ppc = sh2->pc;
	130	opcode = RW(sh2, sh2->pc);
	131	}
	132
	133	sh2->delay = 0;
	134	sh2->pc += 2;
	135
	136	switch (opcode & ( 15 << 12))
	137	{
	138	case 0<<12: op0000(sh2, opcode); break;
	139	case 1<<12: op0001(sh2, opcode); break;
	140	case 2<<12: op0010(sh2, opcode); break;
	141	case 3<<12: op0011(sh2, opcode); break;
	142	case 4<<12: op0100(sh2, opcode); break;
	143	case 5<<12: op0101(sh2, opcode); break;
	144	case 6<<12: op0110(sh2, opcode); break;
	145	case 7<<12: op0111(sh2, opcode); break;
	146	case 8<<12: op1000(sh2, opcode); break;
	147	case 9<<12: op1001(sh2, opcode); break;
	148	case 10<<12: op1010(sh2, opcode); break;
	149	case 11<<12: op1011(sh2, opcode); break;
	150	case 12<<12: op1100(sh2, opcode); break;
	151	case 13<<12: op1101(sh2, opcode); break;
	152	case 14<<12: op1110(sh2, opcode); break;
	153	default: op1111(sh2, opcode); break;
	154	}
	155
	156	sh2->icount--;
	157
	158	if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
	159	{
	160	int level = sh2->pending_level;
	161	int vector = sh2->irq_callback(sh2, level);
	162	sh2_do_irq(sh2, level, vector);
	163	sh2->test_irq = 0;
	164	}
	165
	166	}
	167	while (sh2->icount > 0 \|\| sh2->delay); /* can't interrupt before delay */
	168
	169	out:
0185b677	170	return sh2->icount;
405dfdd7	171	}
	172
	173	#else // if DRC_CMP
679af8a3	174
0185b677	175	int sh2_execute_interpreter(SH2 *sh2, int cycles)
eaa10a6e	176	{
6d797957	177	static unsigned int base_pc_[2] = { 0, 0 };
	178	static unsigned int end_pc_[2] = { 0, 0 };
	179	static unsigned char op_flags_[2][BLOCK_INSN_LIMIT];
	180	unsigned int *base_pc = &base_pc_[sh2->is_slave];
	181	unsigned int *end_pc = &end_pc_[sh2->is_slave];
	182	unsigned char *op_flags = op_flags_[sh2->is_slave];
405dfdd7	183	unsigned int pc_expect;
00faec9c	184	UINT32 opcode;
00faec9c	185
405dfdd7	186	sh2->icount = sh2->cycles_timeslice = cycles;
41397701	187
405dfdd7	188	if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
	189	{
	190	int level = sh2->pending_level;
	191	int vector = sh2->irq_callback(sh2, level);
	192	sh2_do_irq(sh2, level, vector);
	193	}
	194	pc_expect = sh2->pc;
ed4402a7	195
405dfdd7	196	if (sh2->icount <= 0)
405dfdd7	197	goto out;
eaa10a6e	198
	199	do
	200	{
00faec9c	201	if (!sh2->delay) {
6d797957	202	if (sh2->pc < base_pc \|\| sh2->pc >= end_pc) {
	203	*base_pc = sh2->pc;
	204	scan_block(*base_pc, sh2->is_slave,
	205	op_flags, end_pc, NULL);
00faec9c	206	}
6d797957	207	if ((op_flags[(sh2->pc - *base_pc) / 2]
	208	& OF_BTARGET) \|\| sh2->pc == *base_pc
	209	\|\| pc_expect != sh2->pc) // branched
bf092a36	210	{
6d797957	211	pc_expect = sh2->pc;
00faec9c	212	if (sh2->icount < 0)
	213	break;
	214	}
	215
	216	do_sh2_trace(sh2, sh2->icount);
	217	}
6d797957	218	pc_expect += 2;
eaa10a6e	219
3cf9570b	220	if (sh2->delay)
3cf9570b	221	{
a44737c1	222	sh2->ppc = sh2->delay;
f4c0720c	223	opcode = RW(sh2, sh2->delay);
3cf9570b	224	sh2->pc -= 2;
	225	}
	226	else
a44737c1	227	{
a44737c1	228	sh2->ppc = sh2->pc;
f4c0720c	229	opcode = RW(sh2, sh2->pc);
a44737c1	230	}
eaa10a6e	231
	232	sh2->delay = 0;
	233	sh2->pc += 2;
eaa10a6e	234
	235	switch (opcode & ( 15 << 12))
	236	{
f4c0720c	237	case 0<<12: op0000(sh2, opcode); break;
	238	case 1<<12: op0001(sh2, opcode); break;
	239	case 2<<12: op0010(sh2, opcode); break;
	240	case 3<<12: op0011(sh2, opcode); break;
	241	case 4<<12: op0100(sh2, opcode); break;
	242	case 5<<12: op0101(sh2, opcode); break;
	243	case 6<<12: op0110(sh2, opcode); break;
	244	case 7<<12: op0111(sh2, opcode); break;
	245	case 8<<12: op1000(sh2, opcode); break;
	246	case 9<<12: op1001(sh2, opcode); break;
	247	case 10<<12: op1010(sh2, opcode); break;
	248	case 11<<12: op1011(sh2, opcode); break;
	249	case 12<<12: op1100(sh2, opcode); break;
	250	case 13<<12: op1101(sh2, opcode); break;
	251	case 14<<12: op1110(sh2, opcode); break;
	252	default: op1111(sh2, opcode); break;
eaa10a6e	253	}
eaa10a6e	254
41397701	255	sh2->icount--;
1f1ff763	256
	257	if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
	258	{
	259	int level = sh2->pending_level;
	260	int vector = sh2->irq_callback(sh2, level);
	261	sh2_do_irq(sh2, level, vector);
	262	sh2->test_irq = 0;
	263	}
	264
eaa10a6e	265	}
00faec9c	266	while (1);
553c3eaa	267
405dfdd7	268	out:
0185b677	269	return sh2->icount;
679af8a3	270	}
679af8a3	271
405dfdd7	272	#endif // DRC_CMP
679af8a3	273
71f68165	274	#ifdef SH2_STATS
	275	#include <stdio.h>
	276	#include <string.h>
	277	#include "sh2dasm.h"
	278
	279	void sh2_dump_stats(void)
	280	{
	281	static const char *rnames[] = {
	282	"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
	283	"R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP",
	284	"PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL"
	285	};
	286	long long total;
	287	char buff[64];
	288	int u, i;
	289
	290	// dump reg usage
	291	total = 0;
	292	for (i = 0; i < 24; i++)
	293	total += sh2_stats.r[i];
	294
	295	for (i = 0; i < 24; i++) {
	296	if (i == 16 \|\| i == 17 \|\| i == 19)
	297	continue;
	298	printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total,
	299	rnames[i], sh2_stats.r[i]);
	300	}
	301
	302	memset(&sh2_stats, 0, sizeof(sh2_stats));
	303
	304	// dump ops
	305	printf("\n");
	306	total = 0;
	307	for (i = 0; i < 0x10000; i++)
	308	total += op_refs[i];
	309
	310	for (u = 0; u < 16; u++) {
	311	int max = 0, op = 0;
	312	for (i = 0; i < 0x10000; i++) {
	313	if (op_refs[i] > max) {
	314	max = op_refs[i];
	315	op = i;
	316	}
	317	}
	318	DasmSH2(buff, 0, op);
	319	printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total,
	320	op_refs[op], buff);
	321	op_refs[op] = 0;
	322	}
	323	memset(op_refs, 0, sizeof(op_refs));
	324	}
	325	#endif
	326