32x: sh2 stat code, disabled by default
[picodrive.git] / cpu / sh2 / mame / sh2pico.c
CommitLineData
41397701 1#include "../sh2.h"
eaa10a6e 2
3// MAME types
4typedef signed char INT8;
5typedef signed short INT16;
6typedef signed int INT32;
7typedef unsigned int UINT32;
8typedef unsigned short UINT16;
9typedef unsigned char UINT8;
10
bcf65fd6 11#define RB(a) p32x_sh2_read8(a,sh2)
12#define RW(a) p32x_sh2_read16(a,sh2)
13#define RL(a) p32x_sh2_read32(a,sh2)
14#define WB(a,d) p32x_sh2_write8(a,d,sh2)
15#define WW(a,d) p32x_sh2_write16(a,d,sh2)
16#define WL(a,d) p32x_sh2_write32(a,d,sh2)
eaa10a6e 17
18// some stuff from sh2comn.h
19#define T 0x00000001
20#define S 0x00000002
21#define I 0x000000f0
22#define Q 0x00000100
23#define M 0x00000200
24
25#define AM 0xc7ffffff
26
27#define FLAGS (M|Q|I|S|T)
28
29#define Rn ((opcode>>8)&15)
30#define Rm ((opcode>>4)&15)
31
41397701 32#define sh2_icount sh2->icount
1d7a28a7 33
71f68165 34#ifdef SH2_STATS
35static SH2 sh2_stats;
36static unsigned int op_refs[0x10000];
37# define LRN 1
38# define LRM 2
39# define LRNM (LRN|LRM)
40# define rlog(rnm) { \
41 int op = opcode; \
42 if ((rnm) & LRN) { \
43 op &= ~0x0f00; \
44 sh2_stats.r[Rn]++; \
45 } \
46 if ((rnm) & LRM) { \
47 op &= ~0x00f0; \
48 sh2_stats.r[Rm]++; \
49 } \
50 op_refs[op]++; \
51}
52# define rlog1(x) sh2_stats.r[x]++
53# define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++
54#else
55# define rlog(x)
56# define rlog1(...)
57# define rlog2(...)
58#endif
59
41397701 60#include "sh2.c"
1d7a28a7 61
f0d7b1fa 62#ifndef DRC_SH2
679af8a3 63
41397701 64void sh2_execute(SH2 *sh2_, int cycles)
eaa10a6e 65{
66 sh2 = sh2_;
2ea2cbfe 67 sh2->cycles_aim += cycles;
41397701 68 sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done;
69
70 if (sh2->icount <= 0)
71 return;
eaa10a6e 72
73 do
74 {
75 UINT32 opcode;
76
f0d7b1fa 77 /* FIXME: Darxide doesn't like this */
6add7875 78 if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
79 {
80 if (sh2->pending_irl > sh2->pending_int_irq)
81 sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2);
82 else {
83 sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
84 sh2->pending_int_irq = 0; // auto-clear
85 sh2->pending_level = sh2->pending_irl;
86 }
87 sh2->test_irq = 0;
88 }
89
3cf9570b 90 if (sh2->delay)
91 {
a44737c1 92 sh2->ppc = sh2->delay;
3cf9570b 93 opcode = RW(sh2->delay);
94 sh2->pc -= 2;
95 }
96 else
a44737c1 97 {
98 sh2->ppc = sh2->pc;
3cf9570b 99 opcode = RW(sh2->pc);
a44737c1 100 }
eaa10a6e 101
102 sh2->delay = 0;
103 sh2->pc += 2;
eaa10a6e 104
105 switch (opcode & ( 15 << 12))
106 {
107 case 0<<12: op0000(opcode); break;
108 case 1<<12: op0001(opcode); break;
109 case 2<<12: op0010(opcode); break;
110 case 3<<12: op0011(opcode); break;
111 case 4<<12: op0100(opcode); break;
112 case 5<<12: op0101(opcode); break;
113 case 6<<12: op0110(opcode); break;
114 case 7<<12: op0111(opcode); break;
115 case 8<<12: op1000(opcode); break;
116 case 9<<12: op1001(opcode); break;
117 case 10<<12: op1010(opcode); break;
118 case 11<<12: op1011(opcode); break;
119 case 12<<12: op1100(opcode); break;
120 case 13<<12: op1101(opcode); break;
121 case 14<<12: op1110(opcode); break;
122 default: op1111(opcode); break;
123 }
124
41397701 125 sh2->icount--;
eaa10a6e 126 }
41397701 127 while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */
4ea707e1 128
41397701 129 sh2->cycles_done += cycles - sh2->icount;
4ea707e1 130}
eaa10a6e 131
f0d7b1fa 132#else // DRC_SH2
679af8a3 133
553c3eaa 134#ifdef __i386__
135#define REGPARM(x) __attribute__((regparm(x)))
136#else
137#define REGPARM(x)
138#endif
139
f0d7b1fa 140// drc debug
553c3eaa 141void REGPARM(2) sh2_do_op(SH2 *sh2_, int opcode)
679af8a3 142{
143 sh2 = sh2_;
144 sh2->pc += 2;
145
146 switch (opcode & ( 15 << 12))
147 {
148 case 0<<12: op0000(opcode); break;
149 case 1<<12: op0001(opcode); break;
150 case 2<<12: op0010(opcode); break;
151 case 3<<12: op0011(opcode); break;
152 case 4<<12: op0100(opcode); break;
153 case 5<<12: op0101(opcode); break;
154 case 6<<12: op0110(opcode); break;
155 case 7<<12: op0111(opcode); break;
156 case 8<<12: op1000(opcode); break;
157 case 9<<12: op1001(opcode); break;
158 case 10<<12: op1010(opcode); break;
159 case 11<<12: op1011(opcode); break;
160 case 12<<12: op1100(opcode); break;
161 case 13<<12: op1101(opcode); break;
162 case 14<<12: op1110(opcode); break;
163 default: op1111(opcode); break;
164 }
679af8a3 165}
166
167#endif
168
71f68165 169#ifdef SH2_STATS
170#include <stdio.h>
171#include <string.h>
172#include "sh2dasm.h"
173
174void sh2_dump_stats(void)
175{
176 static const char *rnames[] = {
177 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
178 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP",
179 "PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL"
180 };
181 long long total;
182 char buff[64];
183 int u, i;
184
185 // dump reg usage
186 total = 0;
187 for (i = 0; i < 24; i++)
188 total += sh2_stats.r[i];
189
190 for (i = 0; i < 24; i++) {
191 if (i == 16 || i == 17 || i == 19)
192 continue;
193 printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total,
194 rnames[i], sh2_stats.r[i]);
195 }
196
197 memset(&sh2_stats, 0, sizeof(sh2_stats));
198
199 // dump ops
200 printf("\n");
201 total = 0;
202 for (i = 0; i < 0x10000; i++)
203 total += op_refs[i];
204
205 for (u = 0; u < 16; u++) {
206 int max = 0, op = 0;
207 for (i = 0; i < 0x10000; i++) {
208 if (op_refs[i] > max) {
209 max = op_refs[i];
210 op = i;
211 }
212 }
213 DasmSH2(buff, 0, op);
214 printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total,
215 op_refs[op], buff);
216 op_refs[op] = 0;
217 }
218 memset(op_refs, 0, sizeof(op_refs));
219}
220#endif
221