sound: remove cd rate limitations
[picodrive.git] / pico / 32x / 32x.c
CommitLineData
cff531af 1/*
2 * PicoDrive
6a98f03e 3 * (C) notaz, 2009,2010,2013
cff531af 4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 */
be2c4208 8#include "../pico_int.h"
974fdb5b 9#include "../sound/ym2612.h"
51d86e55 10#include "../../cpu/sh2/compiler.h"
be2c4208 11
12struct Pico32x Pico32x;
83ff19ec 13SH2 sh2s[2];
be2c4208 14
19886062 15#define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
16
e05b81fc 17static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
4ea707e1 18{
e05b81fc 19 if (sh2->pending_irl > sh2->pending_int_irq) {
f8675e28 20 elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
21 level, sh2_pc(sh2));
e05b81fc 22 return 64 + sh2->pending_irl / 2;
23 } else {
f8675e28 24 elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
25 level, sh2->pending_int_vector, sh2_pc(sh2));
e05b81fc 26 sh2->pending_int_irq = 0; // auto-clear
27 sh2->pending_level = sh2->pending_irl;
28 return sh2->pending_int_vector;
29 }
4ea707e1 30}
31
c1931173 32// MUST specify active_sh2 when called from sh2 memhandlers
4d5dfee8 33void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
4ea707e1 34{
35 int irqs, mlvl = 0, slvl = 0;
a8fd6e37 36 int mrun, srun;
4ea707e1 37
19886062 38 if (active_sh2 != NULL)
39 m68k_cycles = sh2_cycles_done_m68k(active_sh2);
40
4ea707e1 41 // msh2
9e1fa0a6 42 irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
4ea707e1 43 while ((irqs >>= 1))
44 mlvl++;
45 mlvl *= 2;
46
47 // ssh2
9e1fa0a6 48 irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
4ea707e1 49 while ((irqs >>= 1))
50 slvl++;
51 slvl *= 2;
52
c1931173 53 mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
54 if (mrun) {
19886062 55 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
c1931173 56 if (active_sh2 == &msh2)
57 sh2_end_run(active_sh2, 1);
58 }
19886062 59
c1931173 60 srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
61 if (srun) {
19886062 62 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
c1931173 63 if (active_sh2 == &ssh2)
64 sh2_end_run(active_sh2, 1);
65 }
19886062 66
a8fd6e37 67 elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
4ea707e1 68}
69
9e1fa0a6 70// the mask register is inconsistent, CMD is supposed to be a mask,
71// while others are actually irq trigger enables?
72// TODO: test on hw..
73void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
74{
75 Pico32x.sh2irqs |= mask & P32XI_VRES;
76 Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
77 Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
78
79 p32x_update_irls(sh2, m68k_cycles);
80}
81
82void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
83{
84 if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
85 Pico32x.sh2irqi[0] |= P32XI_CMD;
86 else
87 Pico32x.sh2irqi[0] &= ~P32XI_CMD;
88
89 if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
90 Pico32x.sh2irqi[1] |= P32XI_CMD;
91 else
92 Pico32x.sh2irqi[1] &= ~P32XI_CMD;
93
94 p32x_update_irls(sh2, m68k_cycles);
95}
96
be2c4208 97void Pico32xStartup(void)
98{
99 elprintf(EL_STATUS|EL_32X, "32X startup");
100
679af8a3 101 // TODO: OOM handling
be2c4208 102 PicoAHW |= PAHW_32X;
f81107f5 103 sh2_init(&msh2, 0, &ssh2);
4ea707e1 104 msh2.irq_callback = sh2_irq_cb;
f81107f5 105 sh2_init(&ssh2, 1, &msh2);
4ea707e1 106 ssh2.irq_callback = sh2_irq_cb;
83ff19ec 107
108 PicoMemSetup32x();
045a4c52 109 p32x_pwm_ctl_changed();
a8fd6e37 110 p32x_timers_recalc();
acd35d4c 111
fa8fb754 112 Pico32x.sh2_regs[0] = P32XS2_ADEN;
113 if (Pico.m.ncart_in)
114 Pico32x.sh2_regs[0] |= P32XS_nCART;
115
be2c4208 116 if (!Pico.m.pal)
974fdb5b 117 Pico32x.vdp_regs[0] |= P32XV_nPAL;
be2c4208 118
2446536b 119 rendstatus_old = -1;
120
974fdb5b 121 emu_32x_startup();
be2c4208 122}
123
83ff19ec 124#define HWSWAP(x) (((x) << 16) | ((x) >> 16))
125void p32x_reset_sh2s(void)
126{
127 elprintf(EL_32X, "sh2 reset");
128
129 sh2_reset(&msh2);
130 sh2_reset(&ssh2);
cd0ace28 131 sh2_peripheral_reset(&msh2);
132 sh2_peripheral_reset(&ssh2);
83ff19ec 133
134 // if we don't have BIOS set, perform it's work here.
135 // MSH2
136 if (p32x_bios_m == NULL) {
137 unsigned int idl_src, idl_dst, idl_size; // initial data load
138 unsigned int vbr;
139
140 // initial data
141 idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
142 idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
143 idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
144 if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
145 idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
146 elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
147 idl_src, idl_dst, idl_size);
148 }
149 else
150 memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
151
152 // GBR/VBR
153 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
154 sh2_set_gbr(0, 0x20004000);
155 sh2_set_vbr(0, vbr);
156
157 // checksum and M_OK
158 Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
159 // program will set M_OK
160 }
161
162 // SSH2
163 if (p32x_bios_s == NULL) {
164 unsigned int vbr;
165
166 // GBR/VBR
167 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
168 sh2_set_gbr(1, 0x20004000);
169 sh2_set_vbr(1, vbr);
170 // program will set S_OK
171 }
ed4402a7 172
ae214f1c 173 msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
83ff19ec 174}
175
be2c4208 176void Pico32xInit(void)
177{
ed4402a7 178 if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
179 Pico32xSetClocks(PICO_MSH2_HZ, 0);
180 if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
181 Pico32xSetClocks(0, PICO_MSH2_HZ);
974fdb5b 182}
183
184void PicoPower32x(void)
185{
186 memset(&Pico32x, 0, sizeof(Pico32x));
5e49c3a8 187
83ff19ec 188 Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
4a1fb183 189 Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
be2c4208 190}
191
5e49c3a8 192void PicoUnload32x(void)
193{
194 if (Pico32xMem != NULL)
b081408f 195 plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
5e49c3a8 196 Pico32xMem = NULL;
e898de13 197 sh2_finish(&msh2);
198 sh2_finish(&ssh2);
5e49c3a8 199
200 PicoAHW &= ~PAHW_32X;
201}
202
be2c4208 203void PicoReset32x(void)
204{
83ff19ec 205 if (PicoAHW & PAHW_32X) {
ae214f1c 206 p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
19886062 207 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
208 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
045a4c52 209 p32x_pwm_ctl_changed();
a8fd6e37 210 p32x_timers_recalc();
83ff19ec 211 }
be2c4208 212}
213
974fdb5b 214static void p32x_start_blank(void)
215{
7a961c19 216 if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
5aec752d 217 int offs, lines;
218
219 pprof_start(draw);
220
221 offs = 8; lines = 224;
7a961c19 222 if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
223 offs = 0;
224 lines = 240;
225 }
226
227 // XXX: no proper handling of 32col mode..
5a681086 228 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
229 (Pico.video.reg[12] & 1) && // 40col mode
230 (PicoDrawMask & PDRAW_32X_ON))
231 {
232 int md_bg = Pico.video.reg[7] & 0x3f;
5a681086 233
234 // we draw full layer (not line-by-line)
235 PicoDraw32xLayer(offs, lines, md_bg);
236 }
7a961c19 237 else if (Pico32xDrawMode != PDM32X_32X_ONLY)
238 PicoDraw32xLayerMdOnly(offs, lines);
5aec752d 239
240 pprof_end(draw);
5a681086 241 }
242
974fdb5b 243 // enter vblank
244 Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
245
4ea707e1 246 // FB swap waits until vblank
974fdb5b 247 if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
248 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
249 Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
250 Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
251 }
4ea707e1 252
ae214f1c 253 p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT);
19886062 254 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
255 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
974fdb5b 256}
257
5ac99d9a 258void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
259{
260 // rather rough, 32x hint is useless in practice
261 int after;
262
263 if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
264 return; // nobody cares
265 // note: when Pico.m.scanline is 224, SH2s might
266 // still be at scanline 93 (or so)
267 if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
268 return;
269
270 after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
271 if (sh2 != NULL)
272 p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
273 else
274 p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
275}
276
a8fd6e37 277/* events */
a8fd6e37 278static void fillend_event(unsigned int now)
279{
280 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
19886062 281 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
282 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
a8fd6e37 283}
284
5ac99d9a 285static void hint_event(unsigned int now)
286{
9e1fa0a6 287 p32x_trigger_irq(NULL, now, P32XI_HINT);
5ac99d9a 288 p32x_schedule_hint(NULL, now);
289}
290
a8fd6e37 291typedef void (event_cb)(unsigned int now);
292
ae214f1c 293/* times are in m68k (7.6MHz) cycles */
294unsigned int p32x_event_times[P32X_EVENT_COUNT];
a8fd6e37 295static unsigned int event_time_next;
ae214f1c 296static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = {
df63f1a6 297 [P32X_EVENT_PWM] = p32x_pwm_irq_event,
a8fd6e37 298 [P32X_EVENT_FILLEND] = fillend_event,
5ac99d9a 299 [P32X_EVENT_HINT] = hint_event,
a8fd6e37 300};
301
19886062 302// schedule event at some time 'after', in m68k clocks
303void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
a8fd6e37 304{
19886062 305 unsigned int when;
306
307 when = (now + after) | 1;
a8fd6e37 308
ae214f1c 309 elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when);
310 p32x_event_times[event] = when;
a8fd6e37 311
19886062 312 if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
a8fd6e37 313 event_time_next = when;
314}
315
19886062 316void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
317{
318 unsigned int now = sh2_cycles_done_m68k(sh2);
319 int left_to_next;
320
321 p32x_event_schedule(now, event, after);
322
323 left_to_next = (event_time_next - now) * 3;
c1931173 324 sh2_end_run(sh2, left_to_next);
19886062 325}
326
ae214f1c 327static void p32x_run_events(unsigned int until)
a8fd6e37 328{
329 int oldest, oldest_diff, time;
330 int i, diff;
331
332 while (1) {
333 oldest = -1, oldest_diff = 0x7fffffff;
334
335 for (i = 0; i < P32X_EVENT_COUNT; i++) {
ae214f1c 336 if (p32x_event_times[i]) {
337 diff = p32x_event_times[i] - until;
a8fd6e37 338 if (diff < oldest_diff) {
339 oldest_diff = diff;
340 oldest = i;
341 }
342 }
343 }
344
345 if (oldest_diff <= 0) {
ae214f1c 346 time = p32x_event_times[oldest];
347 p32x_event_times[oldest] = 0;
348 elprintf(EL_32X, "32x: run event #%d %u", oldest, time);
349 p32x_event_cbs[oldest](time);
a8fd6e37 350 }
351 else if (oldest_diff < 0x7fffffff) {
ae214f1c 352 event_time_next = p32x_event_times[oldest];
a8fd6e37 353 break;
354 }
355 else {
356 event_time_next = 0;
357 break;
358 }
359 }
360
361 if (oldest != -1)
ae214f1c 362 elprintf(EL_32X, "32x: next event #%d at %u",
363 oldest, event_time_next);
a8fd6e37 364}
365
19886062 366static inline void run_sh2(SH2 *sh2, int m68k_cycles)
367{
368 int cycles, done;
369
370 pevt_log_sh2_o(sh2, EVT_RUN_START);
371 sh2->state |= SH2_STATE_RUN;
372 cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
f8675e28 373 elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
374 sh2->m68krcycles_done, cycles, sh2->pc);
19886062 375
0185b677 376 done = sh2_execute(sh2, cycles, PicoOpt & POPT_EN_DRC);
19886062 377
378 sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
379 sh2->state &= ~SH2_STATE_RUN;
380 pevt_log_sh2_o(sh2, EVT_RUN_END);
f8675e28 381 elprintf_sh2(sh2, EL_32X, "-run %u %d",
382 sh2->m68krcycles_done, done);
19886062 383}
384
385// sync other sh2 to this one
386// note: recursive call
387void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
388{
f81107f5 389 SH2 *osh2 = sh2->other_sh2;
19886062 390 int left_to_event;
391 int m68k_cycles;
392
393 if (osh2->state & SH2_STATE_RUN)
394 return;
395
396 m68k_cycles = m68k_target - osh2->m68krcycles_done;
397 if (m68k_cycles < 200)
398 return;
399
400 if (osh2->state & SH2_IDLE_STATES) {
401 osh2->m68krcycles_done = m68k_target;
402 return;
403 }
404
f8675e28 405 elprintf_sh2(osh2, EL_32X, "sync to %u %d",
406 m68k_target, m68k_cycles);
19886062 407
408 run_sh2(osh2, m68k_cycles);
409
410 // there might be new event to schedule current sh2 to
411 if (event_time_next) {
412 left_to_event = event_time_next - m68k_target;
413 left_to_event *= 3;
414 if (sh2_cycles_left(sh2) > left_to_event) {
415 if (left_to_event < 1)
416 left_to_event = 1;
417 sh2_end_run(sh2, left_to_event);
418 }
419 }
420}
a8fd6e37 421
ed4402a7 422#define sync_sh2s_normal p32x_sync_sh2s
423//#define sync_sh2s_lockstep p32x_sync_sh2s
974fdb5b 424
a8fd6e37 425/* most timing is in 68k clock */
ed4402a7 426void sync_sh2s_normal(unsigned int m68k_target)
427{
a8fd6e37 428 unsigned int now, target, timer_cycles;
19886062 429 int cycles;
ed4402a7 430
a8fd6e37 431 elprintf(EL_32X, "sh2 sync to %u", m68k_target);
ed4402a7 432
27e26273 433 if (!(Pico32x.regs[0] & P32XS_nRES)) {
434 msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
ed4402a7 435 return; // rare
27e26273 436 }
ed4402a7 437
a8fd6e37 438 now = msh2.m68krcycles_done;
439 if (CYCLES_GT(now, ssh2.m68krcycles_done))
440 now = ssh2.m68krcycles_done;
441 timer_cycles = now;
442
443 while (CYCLES_GT(m68k_target, now))
ed4402a7 444 {
a8fd6e37 445 if (event_time_next && CYCLES_GE(now, event_time_next))
ae214f1c 446 p32x_run_events(now);
ed4402a7 447
a8fd6e37 448 target = m68k_target;
449 if (event_time_next && CYCLES_GT(target, event_time_next))
450 target = event_time_next;
451
452 while (CYCLES_GT(target, now))
453 {
454 elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
455 target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
456 m68k_target - now, Pico32x.emu_flags);
ed4402a7 457
19886062 458 if (!(ssh2.state & SH2_IDLE_STATES)) {
a8fd6e37 459 cycles = target - ssh2.m68krcycles_done;
460 if (cycles > 0) {
19886062 461 run_sh2(&ssh2, cycles);
a8fd6e37 462
463 if (event_time_next && CYCLES_GT(target, event_time_next))
464 target = event_time_next;
465 }
ed4402a7 466 }
467
19886062 468 if (!(msh2.state & SH2_IDLE_STATES)) {
a8fd6e37 469 cycles = target - msh2.m68krcycles_done;
470 if (cycles > 0) {
19886062 471 run_sh2(&msh2, cycles);
a8fd6e37 472
473 if (event_time_next && CYCLES_GT(target, event_time_next))
474 target = event_time_next;
475 }
ed4402a7 476 }
a8fd6e37 477
19886062 478 now = target;
479 if (!(msh2.state & SH2_IDLE_STATES)) {
480 if (CYCLES_GT(now, msh2.m68krcycles_done))
481 now = msh2.m68krcycles_done;
482 }
483 if (!(ssh2.state & SH2_IDLE_STATES)) {
484 if (CYCLES_GT(now, ssh2.m68krcycles_done))
485 now = ssh2.m68krcycles_done;
486 }
ed4402a7 487 }
a8fd6e37 488
045a4c52 489 p32x_timers_do(now - timer_cycles);
a8fd6e37 490 timer_cycles = now;
ed4402a7 491 }
19886062 492
493 // advance idle CPUs
494 if (msh2.state & SH2_IDLE_STATES) {
495 if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
496 msh2.m68krcycles_done = m68k_target;
497 }
498 if (ssh2.state & SH2_IDLE_STATES) {
499 if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
500 ssh2.m68krcycles_done = m68k_target;
501 }
236990cf 502}
acd35d4c 503
c987bb5c 504#define STEP_68K 24
ed4402a7 505
506void sync_sh2s_lockstep(unsigned int m68k_target)
507{
508 unsigned int mcycles;
509
510 mcycles = msh2.m68krcycles_done;
511 if (ssh2.m68krcycles_done < mcycles)
512 mcycles = ssh2.m68krcycles_done;
513
514 while (mcycles < m68k_target) {
515 mcycles += STEP_68K;
516 sync_sh2s_normal(mcycles);
517 }
87accdf7 518}
519
ae214f1c 520#define CPUS_RUN(m68k_cycles) do { \
fa8fb754 521 if (PicoAHW & PAHW_MCD) \
522 pcd_run_cpus(m68k_cycles); \
523 else \
524 SekRunM68k(m68k_cycles); \
525 \
ae214f1c 526 if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
527 && !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \
528 PicoSyncZ80(SekCyclesDone()); \
19886062 529 if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
ae214f1c 530 p32x_sync_sh2s(SekCyclesDone()); \
ed4402a7 531} while (0)
87accdf7 532
ed4402a7 533#define PICO_32X
fa8fb754 534#define PICO_CD
974fdb5b 535#include "../pico_cmn.c"
536
537void PicoFrame32x(void)
538{
5ac99d9a 539 Pico.m.scanline = 0;
540
4ea707e1 541 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
db1d3564 542 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
543 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
4ea707e1 544
5ac99d9a 545 if (!(Pico32x.sh2_regs[0] & 0x80))
ae214f1c 546 p32x_schedule_hint(NULL, SekCyclesDone());
19886062 547 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
548 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
974fdb5b 549
550 PicoFrameStart();
551 PicoFrameHints();
51d86e55 552 sh2_drc_frame();
553
19886062 554 elprintf(EL_32X, "poll: %02x %02x %02x",
555 Pico32x.emu_flags & 3, msh2.state, ssh2.state);
974fdb5b 556}
db1d3564 557
ed4402a7 558// calculate multipliers against 68k clock (7670442)
559// normally * 3, but effectively slower due to high latencies everywhere
560// however using something lower breaks MK2 animations
561void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
562{
563 float m68k_clk = (float)(OSC_NTSC / 7);
564 if (msh2_hz > 0) {
565 msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
566 msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
567 }
568 if (ssh2_hz > 0) {
569 ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
570 ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
571 }
572}
573
27e26273 574void Pico32xStateLoaded(int is_early)
575{
576 if (is_early) {
577 Pico32xMemStateLoaded();
578 return;
579 }
580
ae214f1c 581 sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone();
582 p32x_update_irls(NULL, SekCyclesDone());
df63f1a6 583 p32x_pwm_state_loaded();
ae214f1c 584 p32x_run_events(SekCyclesDone());
27e26273 585}
586
ed4402a7 587// vim:shiftwidth=2:ts=2:expandtab