cff531af |
1 | /* |
2 | * PicoDrive |
6a98f03e |
3 | * (C) notaz, 2009,2010,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
be2c4208 |
8 | #include "../pico_int.h" |
974fdb5b |
9 | #include "../sound/ym2612.h" |
51d86e55 |
10 | #include "../../cpu/sh2/compiler.h" |
be2c4208 |
11 | |
12 | struct Pico32x Pico32x; |
83ff19ec |
13 | SH2 sh2s[2]; |
be2c4208 |
14 | |
19886062 |
15 | #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP) |
16 | |
e05b81fc |
17 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
4ea707e1 |
18 | { |
e05b81fc |
19 | if (sh2->pending_irl > sh2->pending_int_irq) { |
f8675e28 |
20 | elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x", |
21 | level, sh2_pc(sh2)); |
e05b81fc |
22 | return 64 + sh2->pending_irl / 2; |
23 | } else { |
f8675e28 |
24 | elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x", |
25 | level, sh2->pending_int_vector, sh2_pc(sh2)); |
e05b81fc |
26 | sh2->pending_int_irq = 0; // auto-clear |
27 | sh2->pending_level = sh2->pending_irl; |
28 | return sh2->pending_int_vector; |
29 | } |
4ea707e1 |
30 | } |
31 | |
c1931173 |
32 | // MUST specify active_sh2 when called from sh2 memhandlers |
4d5dfee8 |
33 | void p32x_update_irls(SH2 *active_sh2, int m68k_cycles) |
4ea707e1 |
34 | { |
35 | int irqs, mlvl = 0, slvl = 0; |
a8fd6e37 |
36 | int mrun, srun; |
4ea707e1 |
37 | |
19886062 |
38 | if (active_sh2 != NULL) |
39 | m68k_cycles = sh2_cycles_done_m68k(active_sh2); |
40 | |
4ea707e1 |
41 | // msh2 |
9e1fa0a6 |
42 | irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0]; |
4ea707e1 |
43 | while ((irqs >>= 1)) |
44 | mlvl++; |
45 | mlvl *= 2; |
46 | |
47 | // ssh2 |
9e1fa0a6 |
48 | irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1]; |
4ea707e1 |
49 | while ((irqs >>= 1)) |
50 | slvl++; |
51 | slvl *= 2; |
52 | |
c1931173 |
53 | mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2); |
54 | if (mrun) { |
19886062 |
55 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles); |
c1931173 |
56 | if (active_sh2 == &msh2) |
57 | sh2_end_run(active_sh2, 1); |
58 | } |
19886062 |
59 | |
c1931173 |
60 | srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2); |
61 | if (srun) { |
19886062 |
62 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles); |
c1931173 |
63 | if (active_sh2 == &ssh2) |
64 | sh2_end_run(active_sh2, 1); |
65 | } |
19886062 |
66 | |
a8fd6e37 |
67 | elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun); |
4ea707e1 |
68 | } |
69 | |
9e1fa0a6 |
70 | // the mask register is inconsistent, CMD is supposed to be a mask, |
71 | // while others are actually irq trigger enables? |
72 | // TODO: test on hw.. |
73 | void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask) |
74 | { |
75 | Pico32x.sh2irqs |= mask & P32XI_VRES; |
76 | Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3); |
77 | Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3); |
78 | |
79 | p32x_update_irls(sh2, m68k_cycles); |
80 | } |
81 | |
82 | void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles) |
83 | { |
84 | if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1)) |
85 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
86 | else |
87 | Pico32x.sh2irqi[0] &= ~P32XI_CMD; |
88 | |
89 | if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2)) |
90 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
91 | else |
92 | Pico32x.sh2irqi[1] &= ~P32XI_CMD; |
93 | |
94 | p32x_update_irls(sh2, m68k_cycles); |
95 | } |
96 | |
be2c4208 |
97 | void Pico32xStartup(void) |
98 | { |
99 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
100 | |
679af8a3 |
101 | // TODO: OOM handling |
be2c4208 |
102 | PicoAHW |= PAHW_32X; |
f81107f5 |
103 | sh2_init(&msh2, 0, &ssh2); |
4ea707e1 |
104 | msh2.irq_callback = sh2_irq_cb; |
f81107f5 |
105 | sh2_init(&ssh2, 1, &msh2); |
4ea707e1 |
106 | ssh2.irq_callback = sh2_irq_cb; |
83ff19ec |
107 | |
108 | PicoMemSetup32x(); |
045a4c52 |
109 | p32x_pwm_ctl_changed(); |
a8fd6e37 |
110 | p32x_timers_recalc(); |
acd35d4c |
111 | |
fa8fb754 |
112 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
113 | if (Pico.m.ncart_in) |
114 | Pico32x.sh2_regs[0] |= P32XS_nCART; |
115 | |
be2c4208 |
116 | if (!Pico.m.pal) |
974fdb5b |
117 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
be2c4208 |
118 | |
2446536b |
119 | rendstatus_old = -1; |
120 | |
974fdb5b |
121 | emu_32x_startup(); |
be2c4208 |
122 | } |
123 | |
83ff19ec |
124 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
125 | void p32x_reset_sh2s(void) |
126 | { |
127 | elprintf(EL_32X, "sh2 reset"); |
128 | |
129 | sh2_reset(&msh2); |
130 | sh2_reset(&ssh2); |
cd0ace28 |
131 | sh2_peripheral_reset(&msh2); |
132 | sh2_peripheral_reset(&ssh2); |
83ff19ec |
133 | |
134 | // if we don't have BIOS set, perform it's work here. |
135 | // MSH2 |
136 | if (p32x_bios_m == NULL) { |
137 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
138 | unsigned int vbr; |
139 | |
140 | // initial data |
141 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
142 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
143 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
144 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
145 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
146 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
147 | idl_src, idl_dst, idl_size); |
148 | } |
149 | else |
150 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
151 | |
152 | // GBR/VBR |
153 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
154 | sh2_set_gbr(0, 0x20004000); |
155 | sh2_set_vbr(0, vbr); |
156 | |
157 | // checksum and M_OK |
158 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
159 | // program will set M_OK |
160 | } |
161 | |
162 | // SSH2 |
163 | if (p32x_bios_s == NULL) { |
164 | unsigned int vbr; |
165 | |
166 | // GBR/VBR |
167 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
168 | sh2_set_gbr(1, 0x20004000); |
169 | sh2_set_vbr(1, vbr); |
170 | // program will set S_OK |
171 | } |
ed4402a7 |
172 | |
ae214f1c |
173 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone(); |
83ff19ec |
174 | } |
175 | |
be2c4208 |
176 | void Pico32xInit(void) |
177 | { |
ed4402a7 |
178 | if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0) |
179 | Pico32xSetClocks(PICO_MSH2_HZ, 0); |
180 | if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0) |
181 | Pico32xSetClocks(0, PICO_MSH2_HZ); |
974fdb5b |
182 | } |
183 | |
184 | void PicoPower32x(void) |
185 | { |
186 | memset(&Pico32x, 0, sizeof(Pico32x)); |
5e49c3a8 |
187 | |
83ff19ec |
188 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
4a1fb183 |
189 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN; |
be2c4208 |
190 | } |
191 | |
5e49c3a8 |
192 | void PicoUnload32x(void) |
193 | { |
194 | if (Pico32xMem != NULL) |
b081408f |
195 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
5e49c3a8 |
196 | Pico32xMem = NULL; |
e898de13 |
197 | sh2_finish(&msh2); |
198 | sh2_finish(&ssh2); |
5e49c3a8 |
199 | |
200 | PicoAHW &= ~PAHW_32X; |
201 | } |
202 | |
be2c4208 |
203 | void PicoReset32x(void) |
204 | { |
83ff19ec |
205 | if (PicoAHW & PAHW_32X) { |
ae214f1c |
206 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone(); |
207 | p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES); |
19886062 |
208 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0); |
209 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0); |
045a4c52 |
210 | p32x_pwm_ctl_changed(); |
a8fd6e37 |
211 | p32x_timers_recalc(); |
83ff19ec |
212 | } |
be2c4208 |
213 | } |
214 | |
974fdb5b |
215 | static void p32x_start_blank(void) |
216 | { |
7a961c19 |
217 | if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) { |
5aec752d |
218 | int offs, lines; |
219 | |
220 | pprof_start(draw); |
221 | |
222 | offs = 8; lines = 224; |
7a961c19 |
223 | if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) { |
224 | offs = 0; |
225 | lines = 240; |
226 | } |
227 | |
228 | // XXX: no proper handling of 32col mode.. |
5a681086 |
229 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
230 | (Pico.video.reg[12] & 1) && // 40col mode |
231 | (PicoDrawMask & PDRAW_32X_ON)) |
232 | { |
233 | int md_bg = Pico.video.reg[7] & 0x3f; |
5a681086 |
234 | |
235 | // we draw full layer (not line-by-line) |
236 | PicoDraw32xLayer(offs, lines, md_bg); |
237 | } |
7a961c19 |
238 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
239 | PicoDraw32xLayerMdOnly(offs, lines); |
5aec752d |
240 | |
241 | pprof_end(draw); |
5a681086 |
242 | } |
243 | |
974fdb5b |
244 | // enter vblank |
245 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
246 | |
4ea707e1 |
247 | // FB swap waits until vblank |
974fdb5b |
248 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
249 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
250 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
251 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
252 | } |
4ea707e1 |
253 | |
ae214f1c |
254 | p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT); |
19886062 |
255 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
256 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
974fdb5b |
257 | } |
258 | |
5ac99d9a |
259 | void p32x_schedule_hint(SH2 *sh2, int m68k_cycles) |
260 | { |
261 | // rather rough, 32x hint is useless in practice |
262 | int after; |
263 | |
264 | if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4)) |
265 | return; // nobody cares |
266 | // note: when Pico.m.scanline is 224, SH2s might |
267 | // still be at scanline 93 (or so) |
268 | if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224) |
269 | return; |
270 | |
271 | after = (Pico32x.sh2_regs[4 / 2] + 1) * 488; |
272 | if (sh2 != NULL) |
273 | p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after); |
274 | else |
275 | p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after); |
276 | } |
277 | |
a8fd6e37 |
278 | /* events */ |
a8fd6e37 |
279 | static void fillend_event(unsigned int now) |
280 | { |
281 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN; |
19886062 |
282 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now); |
283 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now); |
a8fd6e37 |
284 | } |
285 | |
5ac99d9a |
286 | static void hint_event(unsigned int now) |
287 | { |
9e1fa0a6 |
288 | p32x_trigger_irq(NULL, now, P32XI_HINT); |
5ac99d9a |
289 | p32x_schedule_hint(NULL, now); |
290 | } |
291 | |
a8fd6e37 |
292 | typedef void (event_cb)(unsigned int now); |
293 | |
ae214f1c |
294 | /* times are in m68k (7.6MHz) cycles */ |
295 | unsigned int p32x_event_times[P32X_EVENT_COUNT]; |
a8fd6e37 |
296 | static unsigned int event_time_next; |
ae214f1c |
297 | static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = { |
df63f1a6 |
298 | [P32X_EVENT_PWM] = p32x_pwm_irq_event, |
a8fd6e37 |
299 | [P32X_EVENT_FILLEND] = fillend_event, |
5ac99d9a |
300 | [P32X_EVENT_HINT] = hint_event, |
a8fd6e37 |
301 | }; |
302 | |
19886062 |
303 | // schedule event at some time 'after', in m68k clocks |
304 | void p32x_event_schedule(unsigned int now, enum p32x_event event, int after) |
a8fd6e37 |
305 | { |
19886062 |
306 | unsigned int when; |
307 | |
308 | when = (now + after) | 1; |
a8fd6e37 |
309 | |
ae214f1c |
310 | elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when); |
311 | p32x_event_times[event] = when; |
a8fd6e37 |
312 | |
19886062 |
313 | if (event_time_next == 0 || CYCLES_GT(event_time_next, when)) |
a8fd6e37 |
314 | event_time_next = when; |
315 | } |
316 | |
19886062 |
317 | void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after) |
318 | { |
319 | unsigned int now = sh2_cycles_done_m68k(sh2); |
320 | int left_to_next; |
321 | |
322 | p32x_event_schedule(now, event, after); |
323 | |
324 | left_to_next = (event_time_next - now) * 3; |
c1931173 |
325 | sh2_end_run(sh2, left_to_next); |
19886062 |
326 | } |
327 | |
ae214f1c |
328 | static void p32x_run_events(unsigned int until) |
a8fd6e37 |
329 | { |
330 | int oldest, oldest_diff, time; |
331 | int i, diff; |
332 | |
333 | while (1) { |
334 | oldest = -1, oldest_diff = 0x7fffffff; |
335 | |
336 | for (i = 0; i < P32X_EVENT_COUNT; i++) { |
ae214f1c |
337 | if (p32x_event_times[i]) { |
338 | diff = p32x_event_times[i] - until; |
a8fd6e37 |
339 | if (diff < oldest_diff) { |
340 | oldest_diff = diff; |
341 | oldest = i; |
342 | } |
343 | } |
344 | } |
345 | |
346 | if (oldest_diff <= 0) { |
ae214f1c |
347 | time = p32x_event_times[oldest]; |
348 | p32x_event_times[oldest] = 0; |
349 | elprintf(EL_32X, "32x: run event #%d %u", oldest, time); |
350 | p32x_event_cbs[oldest](time); |
a8fd6e37 |
351 | } |
352 | else if (oldest_diff < 0x7fffffff) { |
ae214f1c |
353 | event_time_next = p32x_event_times[oldest]; |
a8fd6e37 |
354 | break; |
355 | } |
356 | else { |
357 | event_time_next = 0; |
358 | break; |
359 | } |
360 | } |
361 | |
362 | if (oldest != -1) |
ae214f1c |
363 | elprintf(EL_32X, "32x: next event #%d at %u", |
364 | oldest, event_time_next); |
a8fd6e37 |
365 | } |
366 | |
19886062 |
367 | static inline void run_sh2(SH2 *sh2, int m68k_cycles) |
368 | { |
369 | int cycles, done; |
370 | |
371 | pevt_log_sh2_o(sh2, EVT_RUN_START); |
372 | sh2->state |= SH2_STATE_RUN; |
373 | cycles = C_M68K_TO_SH2(*sh2, m68k_cycles); |
f8675e28 |
374 | elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x", |
375 | sh2->m68krcycles_done, cycles, sh2->pc); |
19886062 |
376 | |
0185b677 |
377 | done = sh2_execute(sh2, cycles, PicoOpt & POPT_EN_DRC); |
19886062 |
378 | |
379 | sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done); |
380 | sh2->state &= ~SH2_STATE_RUN; |
381 | pevt_log_sh2_o(sh2, EVT_RUN_END); |
f8675e28 |
382 | elprintf_sh2(sh2, EL_32X, "-run %u %d", |
383 | sh2->m68krcycles_done, done); |
19886062 |
384 | } |
385 | |
386 | // sync other sh2 to this one |
387 | // note: recursive call |
388 | void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target) |
389 | { |
f81107f5 |
390 | SH2 *osh2 = sh2->other_sh2; |
19886062 |
391 | int left_to_event; |
392 | int m68k_cycles; |
393 | |
394 | if (osh2->state & SH2_STATE_RUN) |
395 | return; |
396 | |
397 | m68k_cycles = m68k_target - osh2->m68krcycles_done; |
398 | if (m68k_cycles < 200) |
399 | return; |
400 | |
401 | if (osh2->state & SH2_IDLE_STATES) { |
402 | osh2->m68krcycles_done = m68k_target; |
403 | return; |
404 | } |
405 | |
f8675e28 |
406 | elprintf_sh2(osh2, EL_32X, "sync to %u %d", |
407 | m68k_target, m68k_cycles); |
19886062 |
408 | |
409 | run_sh2(osh2, m68k_cycles); |
410 | |
411 | // there might be new event to schedule current sh2 to |
412 | if (event_time_next) { |
413 | left_to_event = event_time_next - m68k_target; |
414 | left_to_event *= 3; |
415 | if (sh2_cycles_left(sh2) > left_to_event) { |
416 | if (left_to_event < 1) |
417 | left_to_event = 1; |
418 | sh2_end_run(sh2, left_to_event); |
419 | } |
420 | } |
421 | } |
a8fd6e37 |
422 | |
ed4402a7 |
423 | #define sync_sh2s_normal p32x_sync_sh2s |
424 | //#define sync_sh2s_lockstep p32x_sync_sh2s |
974fdb5b |
425 | |
a8fd6e37 |
426 | /* most timing is in 68k clock */ |
ed4402a7 |
427 | void sync_sh2s_normal(unsigned int m68k_target) |
428 | { |
a8fd6e37 |
429 | unsigned int now, target, timer_cycles; |
19886062 |
430 | int cycles; |
ed4402a7 |
431 | |
a8fd6e37 |
432 | elprintf(EL_32X, "sh2 sync to %u", m68k_target); |
ed4402a7 |
433 | |
27e26273 |
434 | if (!(Pico32x.regs[0] & P32XS_nRES)) { |
435 | msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target; |
ed4402a7 |
436 | return; // rare |
27e26273 |
437 | } |
ed4402a7 |
438 | |
a8fd6e37 |
439 | now = msh2.m68krcycles_done; |
440 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
441 | now = ssh2.m68krcycles_done; |
442 | timer_cycles = now; |
443 | |
444 | while (CYCLES_GT(m68k_target, now)) |
ed4402a7 |
445 | { |
a8fd6e37 |
446 | if (event_time_next && CYCLES_GE(now, event_time_next)) |
ae214f1c |
447 | p32x_run_events(now); |
ed4402a7 |
448 | |
a8fd6e37 |
449 | target = m68k_target; |
450 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
451 | target = event_time_next; |
452 | |
453 | while (CYCLES_GT(target, now)) |
454 | { |
455 | elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target, |
456 | target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done, |
457 | m68k_target - now, Pico32x.emu_flags); |
ed4402a7 |
458 | |
19886062 |
459 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
a8fd6e37 |
460 | cycles = target - ssh2.m68krcycles_done; |
461 | if (cycles > 0) { |
19886062 |
462 | run_sh2(&ssh2, cycles); |
a8fd6e37 |
463 | |
464 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
465 | target = event_time_next; |
466 | } |
ed4402a7 |
467 | } |
468 | |
19886062 |
469 | if (!(msh2.state & SH2_IDLE_STATES)) { |
a8fd6e37 |
470 | cycles = target - msh2.m68krcycles_done; |
471 | if (cycles > 0) { |
19886062 |
472 | run_sh2(&msh2, cycles); |
a8fd6e37 |
473 | |
474 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
475 | target = event_time_next; |
476 | } |
ed4402a7 |
477 | } |
a8fd6e37 |
478 | |
19886062 |
479 | now = target; |
480 | if (!(msh2.state & SH2_IDLE_STATES)) { |
481 | if (CYCLES_GT(now, msh2.m68krcycles_done)) |
482 | now = msh2.m68krcycles_done; |
483 | } |
484 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
485 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
486 | now = ssh2.m68krcycles_done; |
487 | } |
ed4402a7 |
488 | } |
a8fd6e37 |
489 | |
045a4c52 |
490 | p32x_timers_do(now - timer_cycles); |
a8fd6e37 |
491 | timer_cycles = now; |
ed4402a7 |
492 | } |
19886062 |
493 | |
494 | // advance idle CPUs |
495 | if (msh2.state & SH2_IDLE_STATES) { |
496 | if (CYCLES_GT(m68k_target, msh2.m68krcycles_done)) |
497 | msh2.m68krcycles_done = m68k_target; |
498 | } |
499 | if (ssh2.state & SH2_IDLE_STATES) { |
500 | if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done)) |
501 | ssh2.m68krcycles_done = m68k_target; |
502 | } |
236990cf |
503 | } |
acd35d4c |
504 | |
c987bb5c |
505 | #define STEP_68K 24 |
ed4402a7 |
506 | |
507 | void sync_sh2s_lockstep(unsigned int m68k_target) |
508 | { |
509 | unsigned int mcycles; |
510 | |
511 | mcycles = msh2.m68krcycles_done; |
512 | if (ssh2.m68krcycles_done < mcycles) |
513 | mcycles = ssh2.m68krcycles_done; |
514 | |
515 | while (mcycles < m68k_target) { |
516 | mcycles += STEP_68K; |
517 | sync_sh2s_normal(mcycles); |
518 | } |
87accdf7 |
519 | } |
520 | |
ae214f1c |
521 | #define CPUS_RUN(m68k_cycles) do { \ |
fa8fb754 |
522 | if (PicoAHW & PAHW_MCD) \ |
523 | pcd_run_cpus(m68k_cycles); \ |
524 | else \ |
525 | SekRunM68k(m68k_cycles); \ |
526 | \ |
ae214f1c |
527 | if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \ |
528 | && !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \ |
529 | PicoSyncZ80(SekCyclesDone()); \ |
19886062 |
530 | if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \ |
ae214f1c |
531 | p32x_sync_sh2s(SekCyclesDone()); \ |
ed4402a7 |
532 | } while (0) |
87accdf7 |
533 | |
ed4402a7 |
534 | #define PICO_32X |
fa8fb754 |
535 | #define PICO_CD |
974fdb5b |
536 | #include "../pico_cmn.c" |
537 | |
538 | void PicoFrame32x(void) |
539 | { |
5ac99d9a |
540 | Pico.m.scanline = 0; |
541 | |
4ea707e1 |
542 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
db1d3564 |
543 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
544 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
4ea707e1 |
545 | |
5ac99d9a |
546 | if (!(Pico32x.sh2_regs[0] & 0x80)) |
ae214f1c |
547 | p32x_schedule_hint(NULL, SekCyclesDone()); |
19886062 |
548 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
549 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
974fdb5b |
550 | |
551 | PicoFrameStart(); |
552 | PicoFrameHints(); |
51d86e55 |
553 | sh2_drc_frame(); |
554 | |
19886062 |
555 | elprintf(EL_32X, "poll: %02x %02x %02x", |
556 | Pico32x.emu_flags & 3, msh2.state, ssh2.state); |
974fdb5b |
557 | } |
db1d3564 |
558 | |
ed4402a7 |
559 | // calculate multipliers against 68k clock (7670442) |
560 | // normally * 3, but effectively slower due to high latencies everywhere |
561 | // however using something lower breaks MK2 animations |
562 | void Pico32xSetClocks(int msh2_hz, int ssh2_hz) |
563 | { |
564 | float m68k_clk = (float)(OSC_NTSC / 7); |
565 | if (msh2_hz > 0) { |
566 | msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
567 | msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz); |
568 | } |
569 | if (ssh2_hz > 0) { |
570 | ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
571 | ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz); |
572 | } |
573 | } |
574 | |
27e26273 |
575 | void Pico32xStateLoaded(int is_early) |
576 | { |
577 | if (is_early) { |
578 | Pico32xMemStateLoaded(); |
579 | return; |
580 | } |
581 | |
ae214f1c |
582 | sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone(); |
583 | p32x_update_irls(NULL, SekCyclesDone()); |
df63f1a6 |
584 | p32x_pwm_state_loaded(); |
ae214f1c |
585 | p32x_run_events(SekCyclesDone()); |
27e26273 |
586 | } |
587 | |
ed4402a7 |
588 | // vim:shiftwidth=2:ts=2:expandtab |