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32x: implement more sh2 peripherals
[picodrive.git] / pico / 32x / sh2soc.c
CommitLineData
045a4c52 1/*
2 * SH2 peripherals/"system on chip"
3 * (C) notaz, 2013
4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 *
8 * rough fffffe00-ffffffff map:
9 * e00-e05 SCI serial communication interface
10 * e10-e1a FRT free-running timer
11 * e60-e68 VCRx irq vectors
12 * e71-e72 DRCR dma selection
13 * e80-e83 WDT watchdog timer
14 * e91 SBYCR standby control
15 * e92 CCR cache control
16 * ee0 ICR irq control
17 * ee2 IPRA irq priorities
18 * ee4 VCRWDT WDT irq vectors
19 * f00-f17 DIVU
20 * f40-f7b UBC user break controller
21 * f80-fb3 DMAC
22 * fe0-ffb BSC bus state controller
23 */
24
25#include "../pico_int.h"
26#include "../memory.h"
27
28// DMAC handling
29struct dma_chan {
30 unsigned int sar, dar; // src, dst addr
31 unsigned int tcr; // transfer count
32 unsigned int chcr; // chan ctl
33 // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
34 // ts - transfer size: 1, 2, 4, 16 bytes
35 // ar - auto request if 1, else dreq signal
36 // ie - irq enable
37 // te - transfer end
38 // de - dma enable
39 #define DMA_AR (1 << 9)
40 #define DMA_IE (1 << 2)
41 #define DMA_TE (1 << 1)
42 #define DMA_DE (1 << 0)
43};
44
45struct dmac {
46 struct dma_chan chan[2];
47 unsigned int vcrdma0;
48 unsigned int unknown0;
49 unsigned int vcrdma1;
50 unsigned int unknown1;
51 unsigned int dmaor;
52 // -- pr ae nmif dme
53 // pr - priority: chan0 > chan1 or round-robin
54 // ae - address error
55 // nmif - nmi occurred
56 // dme - DMA master enable
57 #define DMA_DME (1 << 0)
58};
59
60static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
61{
f81107f5 62 char *regs = (void *)sh2->peri_regs;
045a4c52 63 struct dmac *dmac = (void *)(regs + 0x180);
64 int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
65 int vector = (chan == &dmac->chan[0]) ?
66 dmac->vcrdma0 : dmac->vcrdma1;
67
68 elprintf(EL_32XP, "dmac irq %d %d", level, vector);
69 sh2_internal_irq(sh2, level, vector & 0x7f);
70}
71
72static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
73{
74 chan->chcr |= DMA_TE; // DMA has ended normally
75
76 p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
77 if (chan->chcr & DMA_IE)
78 dmac_te_irq(sh2, chan);
79}
80
81static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
82{
83 u32 size, d;
84
85 size = (chan->chcr >> 10) & 3;
86 switch (size) {
87 case 0:
88 d = p32x_sh2_read8(chan->sar, sh2);
89 p32x_sh2_write8(chan->dar, d, sh2);
90 case 1:
91 d = p32x_sh2_read16(chan->sar, sh2);
92 p32x_sh2_write16(chan->dar, d, sh2);
93 break;
94 case 2:
95 d = p32x_sh2_read32(chan->sar, sh2);
96 p32x_sh2_write32(chan->dar, d, sh2);
97 break;
98 case 3:
99 d = p32x_sh2_read32(chan->sar + 0x00, sh2);
100 p32x_sh2_write32(chan->dar + 0x00, d, sh2);
101 d = p32x_sh2_read32(chan->sar + 0x04, sh2);
102 p32x_sh2_write32(chan->dar + 0x04, d, sh2);
103 d = p32x_sh2_read32(chan->sar + 0x08, sh2);
104 p32x_sh2_write32(chan->dar + 0x08, d, sh2);
105 d = p32x_sh2_read32(chan->sar + 0x0c, sh2);
106 p32x_sh2_write32(chan->dar + 0x0c, d, sh2);
107 chan->sar += 16; // always?
108 if (chan->chcr & (1 << 15))
109 chan->dar -= 16;
110 if (chan->chcr & (1 << 14))
111 chan->dar += 16;
112 chan->tcr -= 4;
113 return;
114 }
115 chan->tcr--;
116
117 size = 1 << size;
118 if (chan->chcr & (1 << 15))
119 chan->dar -= size;
120 if (chan->chcr & (1 << 14))
121 chan->dar += size;
122 if (chan->chcr & (1 << 13))
123 chan->sar -= size;
124 if (chan->chcr & (1 << 12))
125 chan->sar += size;
126}
127
128// DMA trigger by SH2 register write
129static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
130{
131 elprintf(EL_32XP, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
132 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
133 chan->tcr &= 0xffffff;
134
135 if (chan->chcr & DMA_AR) {
136 // auto-request transfer
137 while ((int)chan->tcr > 0)
138 dmac_transfer_one(sh2, chan);
139 dmac_transfer_complete(sh2, chan);
140 return;
141 }
142
143 // DREQ0 is only sent after first 4 words are written.
144 // we do multiple of 4 words to avoid messing up alignment
61801d5b 145 if ((chan->sar & ~0x20000000) == 0x00004012) {
045a4c52 146 if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
147 elprintf(EL_32XP, "68k -> sh2 DMA");
148 p32x_dreq0_trigger();
149 }
150 return;
151 }
152
153 elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
154 "%08x->%08x, cnt %d, chcr %04x @%06x",
155 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
156}
157
158// timer state - FIXME
159static int timer_cycles[2];
160static int timer_tick_cycles[2];
161
162// timers
163void p32x_timers_recalc(void)
164{
165 int cycles;
166 int tmp, i;
167
168 // SH2 timer step
169 for (i = 0; i < 2; i++) {
f81107f5 170 tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
045a4c52 171 // Sclk cycles per timer tick
172 if (tmp)
173 cycles = 0x20 << tmp;
174 else
175 cycles = 2;
176 timer_tick_cycles[i] = cycles;
177 timer_cycles[i] = 0;
178 elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles);
179 }
180}
181
182void p32x_timers_do(unsigned int m68k_slice)
183{
184 unsigned int cycles = m68k_slice * 3;
185 int cnt, i;
186
187 // WDT timers
188 for (i = 0; i < 2; i++) {
f81107f5 189 void *pregs = sh2s[i].peri_regs;
045a4c52 190 if (PREG8(pregs, 0x80) & 0x20) { // TME
191 timer_cycles[i] += cycles;
192 cnt = PREG8(pregs, 0x81);
193 while (timer_cycles[i] >= timer_tick_cycles[i]) {
194 timer_cycles[i] -= timer_tick_cycles[i];
195 cnt++;
196 }
197 if (cnt >= 0x100) {
198 int level = PREG8(pregs, 0xe3) >> 4;
199 int vector = PREG8(pregs, 0xe4) & 0x7f;
200 elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)",
201 i ? 's' : 'm', level, vector);
202 sh2_internal_irq(&sh2s[i], level, vector);
203 cnt &= 0xff;
204 }
205 PREG8(pregs, 0x81) = cnt;
206 }
207 }
208}
209
cd0ace28 210void sh2_peripheral_reset(SH2 *sh2)
211{
212 memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
61801d5b 213 PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
214 PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
215 PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
216 PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
217 PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
cd0ace28 218}
219
045a4c52 220// ------------------------------------------------------------------
221// SH2 internal peripheral memhandlers
222// we keep them in little endian format
223
f81107f5 224u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
045a4c52 225{
f81107f5 226 u8 *r = (void *)sh2->peri_regs;
045a4c52 227 u32 d;
228
229 a &= 0x1ff;
230 d = PREG8(r, a);
231
61801d5b 232 elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
233 a | ~0x1ff, d, sh2_pc(sh2));
045a4c52 234 return d;
235}
236
f81107f5 237u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
045a4c52 238{
f81107f5 239 u16 *r = (void *)sh2->peri_regs;
045a4c52 240 u32 d;
241
242 a &= 0x1ff;
243 d = r[(a / 2) ^ 1];
244
61801d5b 245 elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
246 a | ~0x1ff, d, sh2_pc(sh2));
045a4c52 247 return d;
248}
249
f81107f5 250u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
045a4c52 251{
252 u32 d;
253 a &= 0x1fc;
f81107f5 254 d = sh2->peri_regs[a / 4];
045a4c52 255
61801d5b 256 elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
257 a | ~0x1ff, d, sh2_pc(sh2));
045a4c52 258 return d;
259}
260
61801d5b 261static void sci_trigger(SH2 *sh2, u8 *r)
262{
263 u8 *oregs;
264
265 if (!(PREG8(r, 2) & 0x20))
266 return; // transmitter not enabled
267 if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
268 return;
269
270 oregs = (u8 *)sh2->other_sh2->peri_regs;
271 if (!(PREG8(oregs, 2) & 0x10))
272 return; // receiver not enabled
273
274 PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
275 PREG8(r, 4) |= 0x80; // TDRE - TDR empty
276 PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
277
278 // might need to delay these a bit..
279 if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
280 int level = PREG8(oregs, 0x60) >> 4;
281 int vector = PREG8(oregs, 0x64) & 0x7f;
282 elprintf(EL_32XP, "SCI tx irq (%d, %d)",
283 level, vector);
284 sh2_internal_irq(sh2, level, vector);
285 }
286 // TODO: TEIE
287 if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
288 int level = PREG8(oregs, 0x60) >> 4;
289 int vector = PREG8(oregs, 0x63) & 0x7f;
290 elprintf(EL_32XP, "SCI rx irq (%d, %d)",
291 level, vector);
292 sh2_internal_irq(sh2->other_sh2, level, vector);
293 }
294}
295
f81107f5 296void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
045a4c52 297{
f81107f5 298 u8 *r = (void *)sh2->peri_regs;
61801d5b 299 u8 old;
300
f81107f5 301 elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x",
302 sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
045a4c52 303
304 a &= 0x1ff;
61801d5b 305 old = PREG8(r, a);
045a4c52 306
61801d5b 307 switch (a) {
308 case 0x002: // SCR - serial control
309 if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set
310 PREG8(r, a) = d;
311 sci_trigger(sh2, r);
045a4c52 312 }
61801d5b 313 break;
314 case 0x003: // TDR - transmit data
315 break;
316 case 0x004: // SSR - serial status
317 d = (old & (d | 0x06)) | (d & 1);
318 PREG8(r, a) = d;
319 sci_trigger(sh2, r);
320 return;
321 case 0x005: // RDR - receive data
322 break;
323 case 0x010: // TIER
324 if (d & 0x8e)
325 elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
326 d = (d & 0x8e) | 1;
327 break;
328 case 0x017: // TOCR
329 d |= 0xe0;
330 break;
045a4c52 331 }
61801d5b 332 PREG8(r, a) = d;
045a4c52 333}
334
f81107f5 335void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
045a4c52 336{
f81107f5 337 u16 *r = (void *)sh2->peri_regs;
61801d5b 338 elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
339 a, d, sh2_pc(sh2));
045a4c52 340
341 a &= 0x1ff;
342
343 // evil WDT
344 if (a == 0x80) {
345 if ((d & 0xff00) == 0xa500) { // WTCSR
346 PREG8(r, 0x80) = d;
347 p32x_timers_recalc();
348 }
349 if ((d & 0xff00) == 0x5a00) // WTCNT
350 PREG8(r, 0x81) = d;
f81107f5 351 return;
045a4c52 352 }
353
354 r[(a / 2) ^ 1] = d;
045a4c52 355}
356
f81107f5 357void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
045a4c52 358{
f81107f5 359 u32 *r = sh2->peri_regs;
61801d5b 360 u32 old;
361
362 elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
363 a, d, sh2_pc(sh2));
045a4c52 364
365 a &= 0x1fc;
61801d5b 366 old = r[a / 4];
045a4c52 367 r[a / 4] = d;
368
369 switch (a) {
370 // division unit (TODO: verify):
371 case 0x104: // DVDNT: divident L, starts divide
61801d5b 372 elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
373 d, r[0x100 / 4]);
045a4c52 374 if (r[0x100 / 4]) {
375 signed int divisor = r[0x100 / 4];
376 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
377 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
378 }
379 else
380 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
381 break;
382 case 0x114:
61801d5b 383 elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
384 r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
045a4c52 385 if (r[0x100 / 4]) {
386 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
387 signed int divisor = r[0x100 / 4];
388 // XXX: undocumented mirroring to 0x118,0x11c?
389 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
390 divident /= divisor;
391 r[0x11c / 4] = r[0x114 / 4] = divident;
392 divident >>= 31;
393 if ((unsigned long long)divident + 1 > 1) {
61801d5b 394 //elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
045a4c52 395 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
396 }
397 }
398 else
399 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
400 break;
401 }
402
403 // perhaps starting a DMA?
404 if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
f81107f5 405 struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4];
61801d5b 406 if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
407 return;
045a4c52 408 if (!(dmac->dmaor & DMA_DME))
409 return;
410
411 if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
f81107f5 412 dmac_trigger(sh2, &dmac->chan[0]);
045a4c52 413 if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
f81107f5 414 dmac_trigger(sh2, &dmac->chan[1]);
045a4c52 415 }
416}
417
418/* 32X specific */
419static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
420{
7eaa3812 421 unsigned short dreqlen = Pico32x.regs[0x10 / 2];
045a4c52 422 int i;
423
424 // debug/sanity checks
7eaa3812 425 if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
426 elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
427 chan->tcr, dreqlen);
045a4c52 428 // note: DACK is not connected, single addr mode should not be used
429 if ((chan->chcr & 0x3f08) != 0x0400)
430 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
61801d5b 431 if ((chan->sar & ~0x20000000) != 0x00004012)
432 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
045a4c52 433
434 // HACK: assume bus is busy and SH2 is halted
435 sh2->state |= SH2_STATE_SLEEP;
436
437 for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
7eaa3812 438 elprintf(EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
439 chan->dar, Pico32x.dmac_fifo[i], dreqlen);
045a4c52 440 p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
441 chan->dar += 2;
442 chan->tcr--;
045a4c52 443 }
444
445 if (Pico32x.dmac0_fifo_ptr != i)
446 memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
447 (Pico32x.dmac0_fifo_ptr - i) * 2);
448 Pico32x.dmac0_fifo_ptr -= i;
449
450 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
045a4c52 451 if (chan->tcr == 0)
452 dmac_transfer_complete(sh2, chan);
453 else
454 sh2_end_run(sh2, 16);
455}
456
457static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
458{
459 // debug/sanity checks
460 if ((chan->chcr & 0xc308) != 0x0000)
461 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
462 if ((chan->dar & ~0xf) != 0x20004030)
463 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
464
465 dmac_transfer_one(sh2, chan);
466 if (chan->tcr == 0)
467 dmac_transfer_complete(sh2, chan);
468}
469
470void p32x_dreq0_trigger(void)
471{
f81107f5 472 struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
473 struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
045a4c52 474
475 elprintf(EL_32XP, "dreq0_trigger");
476 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
477 dreq0_do(&msh2, &mdmac->chan[0]);
478 }
479 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
480 dreq0_do(&ssh2, &sdmac->chan[0]);
481 }
482}
483
484void p32x_dreq1_trigger(void)
485{
f81107f5 486 struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
487 struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
045a4c52 488 int hit = 0;
489
490 elprintf(EL_32XP, "dreq1_trigger");
491 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
492 dreq1_do(&msh2, &mdmac->chan[1]);
493 hit = 1;
494 }
495 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
496 dreq1_do(&ssh2, &sdmac->chan[1]);
497 hit = 1;
498 }
499
500 if (!hit)
501 elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
502}
503
504// vim:shiftwidth=2:ts=2:expandtab
fast MegaDrive/MegaCD/32X emulator