notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drc: svp: fix cache sync (end ptr)
[picodrive.git] / pico / carthw / svp / compiler.c
CommitLineData
cff531af 1/*
2 * SSP1601 to ARM recompiler
3 * (C) notaz, 2008,2009,2010
4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 */
726bbb3e 8
efcba75f 9#include "../../pico_int.h"
41397701 10#include "../../../cpu/drc/cmn.h"
e807ac75 11#include "compiler.h"
726bbb3e 12
679af8a3 13// FIXME: asm has these hardcoded
14#define SSP_BLOCKTAB_ENTS (0x5090/2)
15#define SSP_BLOCKTAB_IRAM_ONE (0x800/2) // table entries
16#define SSP_BLOCKTAB_IRAM_ENTS (15*SSP_BLOCKTAB_IRAM_ONE)
17
18static u32 **ssp_block_table; // [0x5090/2];
19static u32 **ssp_block_table_iram; // [15][0x800/2];
71bb1b7b 20
71bb1b7b 21static u32 *tcache_ptr = NULL;
726bbb3e 22
726bbb3e 23static int nblocks = 0;
71bb1b7b 24static int n_in_ops = 0;
25
26extern ssp1601_t *ssp;
27
28#define rPC ssp->gr[SSP_PC].h
29#define rPMC ssp->gr[SSP_PMC]
30
31#define SSP_FLAG_Z (1<<0xd)
32#define SSP_FLAG_N (1<<0xf)
726bbb3e 33
d4d62665 34#ifndef __arm__
679af8a3 35//#define DUMP_BLOCK 0x0c9a
45883918 36void ssp_drc_next(void){}
37void ssp_drc_next_patch(void){}
38void ssp_drc_end(void){}
5d817c91 39#endif
40
553c3eaa 41#define COUNT_OP
65c75cb0 42#include "../../../cpu/drc/emit_arm.c"
726bbb3e 43
44// -----------------------------------------------------
45
71bb1b7b 46static int get_inc(int mode)
892b1dd2 47{
71bb1b7b 48 int inc = (mode >> 11) & 7;
49 if (inc != 0) {
50 if (inc != 7) inc--;
51 inc = 1 << inc; // 0 1 2 4 8 16 32 128
52 if (mode & 0x8000) inc = -inc; // decrement mode
892b1dd2 53 }
71bb1b7b 54 return inc;
892b1dd2 55}
56
ee9ee9fd 57u32 ssp_pm_read(int reg)
d5276282 58{
59 u32 d = 0, mode;
60
61 if (ssp->emu_status & SSP_PMC_SET)
62 {
63 ssp->pmac_read[reg] = rPMC.v;
64 ssp->emu_status &= ~SSP_PMC_SET;
d5276282 65 return 0;
66 }
67
d5276282 68 // just in case
69 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
70
71 mode = ssp->pmac_read[reg]>>16;
72 if ((mode & 0xfff0) == 0x0800) // ROM
73 {
74 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
75 ssp->pmac_read[reg] += 1;
76 }
77 else if ((mode & 0x47ff) == 0x0018) // DRAM
78 {
79 unsigned short *dram = (unsigned short *)svp->dram;
80 int inc = get_inc(mode);
81 d = dram[ssp->pmac_read[reg]&0xffff];
82 ssp->pmac_read[reg] += inc;
83 }
84
85 // PMC value corresponds to last PMR accessed
86 rPMC.v = ssp->pmac_read[reg];
87
88 return d;
89}
90
71bb1b7b 91#define overwrite_write(dst, d) \
92{ \
93 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
94 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
95 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
96 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
97}
98
ee9ee9fd 99void ssp_pm_write(u32 d, int reg)
d5276282 100{
101 unsigned short *dram;
102 int mode, addr;
103
104 if (ssp->emu_status & SSP_PMC_SET)
105 {
106 ssp->pmac_write[reg] = rPMC.v;
107 ssp->emu_status &= ~SSP_PMC_SET;
108 return;
109 }
110
111 // just in case
112 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
113
114 dram = (unsigned short *)svp->dram;
115 mode = ssp->pmac_write[reg]>>16;
116 addr = ssp->pmac_write[reg]&0xffff;
117 if ((mode & 0x43ff) == 0x0018) // DRAM
118 {
119 int inc = get_inc(mode);
120 if (mode & 0x0400) {
121 overwrite_write(dram[addr], d);
122 } else dram[addr] = d;
123 ssp->pmac_write[reg] += inc;
124 }
125 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
126 {
127 if (mode & 0x0400) {
128 overwrite_write(dram[addr], d);
129 } else dram[addr] = d;
34e243f1 130 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
d5276282 131 }
132 else if ((mode & 0x47ff) == 0x001c) // IRAM
133 {
134 int inc = get_inc(mode);
135 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
136 ssp->pmac_write[reg] += inc;
e122fae6 137 ssp->drc.iram_dirty = 1;
d5276282 138 }
139
140 rPMC.v = ssp->pmac_write[reg];
141}
142
143
892b1dd2 144// -----------------------------------------------------
145
0b5e8296 146// 14 IRAM blocks
df143b36 147static unsigned char iram_context_map[] =
148{
149 0, 0, 0, 0, 1, 0, 0, 0, // 04
150 0, 0, 0, 0, 0, 0, 2, 0, // 0e
151 0, 0, 0, 0, 0, 3, 0, 4, // 15 17
152 5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
153 8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
154 0, 0, 0, 0, 0, 0, 0, 0,
155 0, 0,11, 0, 0,12, 0, 0, // 32 35
156 13,14, 0, 0, 0, 0, 0, 0 // 38 39
157};
158
71bb1b7b 159int ssp_get_iram_context(void)
df143b36 160{
161 unsigned char *ir = (unsigned char *)svp->iram_rom;
162 int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
df143b36 163 val1 = iram_context_map[(val>>1)&0x3f];
164
5c129565 165 if (val1 == 0) {
2d2247c2 166 elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
df143b36 167 //debug_dump2file(name, svp->iram_rom, 0x800);
2d2247c2 168 //exit(1);
df143b36 169 }
df143b36 170 return val1;
171}
172
5d817c91 173// -----------------------------------------------------
0b5e8296 174
5d817c91 175/* regs with known values */
176static struct
177{
178 ssp_reg_t gr[8];
179 unsigned char r[8];
ede7220f 180 unsigned int pmac_read[5];
181 unsigned int pmac_write[5];
d5276282 182 ssp_reg_t pmc;
ede7220f 183 unsigned int emu_status;
bad5731d 184} known_regs;
185
186#define KRREG_X (1 << SSP_X)
187#define KRREG_Y (1 << SSP_Y)
188#define KRREG_A (1 << SSP_A) /* AH only */
189#define KRREG_ST (1 << SSP_ST)
190#define KRREG_STACK (1 << SSP_STACK)
191#define KRREG_PC (1 << SSP_PC)
192#define KRREG_P (1 << SSP_P)
193#define KRREG_PR0 (1 << 8)
194#define KRREG_PR4 (1 << 12)
195#define KRREG_AL (1 << 16)
d5276282 196#define KRREG_PMCM (1 << 18) /* only mode word of PMC */
197#define KRREG_PMC (1 << 19)
ede7220f 198#define KRREG_PM0R (1 << 20)
199#define KRREG_PM1R (1 << 21)
200#define KRREG_PM2R (1 << 22)
201#define KRREG_PM3R (1 << 23)
202#define KRREG_PM4R (1 << 24)
203#define KRREG_PM0W (1 << 25)
204#define KRREG_PM1W (1 << 26)
205#define KRREG_PM2W (1 << 27)
206#define KRREG_PM3W (1 << 28)
207#define KRREG_PM4W (1 << 29)
bad5731d 208
209/* bitfield of known register values */
210static u32 known_regb = 0;
211
212/* known vals, which need to be flushed
d5276282 213 * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
bad5731d 214 * ST means flags are being held in ARM PSR
89fea1e9 215 * P means that it needs to be recalculated
bad5731d 216 */
217static u32 dirty_regb = 0;
5d817c91 218
219/* known values of host regs.
d274c33b 220 * -1 - unknown
221 * 000000-00ffff - 16bit value
222 * 100000-10ffff - base reg (r7) + 16bit val
6e39239f 223 * 0r0000 - means reg (low) eq gr[r].h, r != AL
5d817c91 224 */
225static int hostreg_r[4];
226
227static void hostreg_clear(void)
228{
229 int i;
230 for (i = 0; i < 4; i++)
231 hostreg_r[i] = -1;
232}
233
6e39239f 234static void hostreg_sspreg_changed(int sspreg)
5d817c91 235{
236 int i;
237 for (i = 0; i < 4; i++)
6e39239f 238 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
5d817c91 239}
240
726bbb3e 241
ede7220f 242#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
243#define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
726bbb3e 244
ee9ee9fd 245void tr_unhandled(void)
6e39239f 246{
2d2247c2 247 //FILE *f = fopen("tcache.bin", "wb");
248 //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
249 //fclose(f);
250 elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
251 //exit(1);
6e39239f 252}
253
0e4d7ba5 254/* update P, if needed. Trashes r0 */
d274c33b 255static void tr_flush_dirty_P(void)
256{
257 // TODO: const regs
bad5731d 258 if (!(dirty_regb & KRREG_P)) return;
d274c33b 259 EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
0e4d7ba5 260 EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
261 EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
262 EOP_MUL(10, 0, 10); // mul r10, r0, r10
bad5731d 263 dirty_regb &= ~KRREG_P;
0e4d7ba5 264 hostreg_r[0] = -1;
d274c33b 265}
266
89fea1e9 267/* write dirty pr to host reg. Nothing is trashed */
268static void tr_flush_dirty_pr(int r)
269{
270 int ror = 0, reg;
6e39239f 271
89fea1e9 272 if (!(dirty_regb & (1 << (r+8)))) return;
273
274 switch (r&3) {
275 case 0: ror = 0; break;
276 case 1: ror = 24/2; break;
277 case 2: ror = 16/2; break;
278 }
279 reg = (r < 4) ? 8 : 9;
280 EOP_BIC_IMM(reg,reg,ror,0xff);
281 if (known_regs.r[r] != 0)
282 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
283 dirty_regb &= ~(1 << (r+8));
284}
285
286/* write all dirty pr0-pr7 to host regs. Nothing is trashed */
287static void tr_flush_dirty_prs(void)
5d817c91 288{
289 int i, ror = 0, reg;
bad5731d 290 int dirty = dirty_regb >> 8;
2385f273 291 if ((dirty&7) == 7) {
65c75cb0 292 emith_move_r_imm(8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
2385f273 293 dirty &= ~7;
294 }
295 if ((dirty&0x70) == 0x70) {
65c75cb0 296 emith_move_r_imm(9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
2385f273 297 dirty &= ~0x70;
298 }
5d817c91 299 /* r0-r7 */
bad5731d 300 for (i = 0; dirty && i < 8; i++, dirty >>= 1)
5d817c91 301 {
bad5731d 302 if (!(dirty&1)) continue;
5d817c91 303 switch (i&3) {
304 case 0: ror = 0; break;
305 case 1: ror = 24/2; break;
306 case 2: ror = 16/2; break;
307 }
308 reg = (i < 4) ? 8 : 9;
309 EOP_BIC_IMM(reg,reg,ror,0xff);
bad5731d 310 if (known_regs.r[i] != 0)
311 EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
5d817c91 312 }
bad5731d 313 dirty_regb &= ~0xff00;
314}
315
89fea1e9 316/* write dirty pr and "forget" it. Nothing is trashed. */
317static void tr_release_pr(int r)
318{
319 tr_flush_dirty_pr(r);
320 known_regb &= ~(1 << (r+8));
321}
322
6e39239f 323/* fush ARM PSR to r6. Trashes r1 */
bad5731d 324static void tr_flush_dirty_ST(void)
325{
326 if (!(dirty_regb & KRREG_ST)) return;
327 EOP_BIC_IMM(6,6,0,0x0f);
6e39239f 328 EOP_MRS(1);
329 EOP_ORR_REG_LSR(6,6,1,28);
bad5731d 330 dirty_regb &= ~KRREG_ST;
6e39239f 331 hostreg_r[1] = -1;
332}
333
334/* inverse of above. Trashes r1 */
335static void tr_make_dirty_ST(void)
336{
337 if (dirty_regb & KRREG_ST) return;
338 if (known_regb & KRREG_ST) {
339 int flags = 0;
340 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
341 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
342 EOP_MSR_IMM(4/2, flags);
343 } else {
344 EOP_MOV_REG_LSL(1, 6, 28);
345 EOP_MSR_REG(1);
346 hostreg_r[1] = -1;
347 }
348 dirty_regb |= KRREG_ST;
bad5731d 349}
350
351/* load 16bit val into host reg r0-r3. Nothing is trashed */
352static void tr_mov16(int r, int val)
353{
354 if (hostreg_r[r] != val) {
65c75cb0 355 emith_move_r_imm(r, val);
bad5731d 356 hostreg_r[r] = val;
357 }
358}
359
360static void tr_mov16_cond(int cond, int r, int val)
361{
80599a42 362 emith_op_imm(cond, 0, A_OP_MOV, r, val);
a6fb500b 363 hostreg_r[r] = -1;
5d817c91 364}
365
45883918 366/* trashes r1 */
ede7220f 367static void tr_flush_dirty_pmcrs(void)
368{
369 u32 i, val = (u32)-1;
d5276282 370 if (!(dirty_regb & 0x3ff80000)) return;
ede7220f 371
d5276282 372 if (dirty_regb & KRREG_PMC) {
373 val = known_regs.pmc.v;
65c75cb0 374 emith_move_r_imm(1, val);
e122fae6 375 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
ede7220f 376
d5276282 377 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
2d2247c2 378 elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
d5276282 379 tr_unhandled();
380 }
ede7220f 381 }
382 for (i = 0; i < 5; i++)
383 {
d5276282 384 if (dirty_regb & (1 << (20+i))) {
ede7220f 385 if (val != known_regs.pmac_read[i]) {
386 val = known_regs.pmac_read[i];
65c75cb0 387 emith_move_r_imm(1, val);
ede7220f 388 }
e122fae6 389 EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
ede7220f 390 }
d5276282 391 if (dirty_regb & (1 << (25+i))) {
ede7220f 392 if (val != known_regs.pmac_write[i]) {
393 val = known_regs.pmac_write[i];
65c75cb0 394 emith_move_r_imm(1, val);
ede7220f 395 }
e122fae6 396 EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
ede7220f 397 }
398 }
d5276282 399 dirty_regb &= ~0x3ff80000;
e122fae6 400 hostreg_r[1] = -1;
ede7220f 401}
402
0e4d7ba5 403/* read bank word to r0 (upper bits zero). Thrashes r1. */
5d817c91 404static void tr_bank_read(int addr) /* word addr 0-0x1ff */
405{
bad5731d 406 int breg = 7;
407 if (addr > 0x7f) {
408 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
409 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
410 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
5d817c91 411 }
bad5731d 412 breg = 1;
5d817c91 413 }
bad5731d 414 EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
5d817c91 415 hostreg_r[0] = -1;
416}
417
418/* write r0 to bank. Trashes r1. */
419static void tr_bank_write(int addr)
420{
421 int breg = 7;
422 if (addr > 0x7f) {
d274c33b 423 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
5d817c91 424 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
d274c33b 425 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
5d817c91 426 }
427 breg = 1;
428 }
b9c1d012 429 EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
5d817c91 430}
431
89fea1e9 432/* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
433static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
5d817c91 434{
a6fb500b 435 int modulo_shift = -1; /* unknown */
5d817c91 436
437 if (mod == 0) return;
438
439 if (!need_modulo || mod == 1) // +!
440 modulo_shift = 8;
bad5731d 441 else if (need_modulo && (known_regb & KRREG_ST)) {
442 modulo_shift = known_regs.gr[SSP_ST].h & 7;
5d817c91 443 if (modulo_shift == 0) modulo_shift = 8;
444 }
445
89fea1e9 446 if (modulo_shift == -1)
447 {
a6fb500b 448 int reg = (r < 4) ? 8 : 9;
89fea1e9 449 tr_release_pr(r);
0e4d7ba5 450 if (dirty_regb & KRREG_ST) {
451 // avoid flushing ARM flags
452 EOP_AND_IMM(1, 6, 0, 0x70);
453 EOP_SUB_IMM(1, 1, 0, 0x10);
454 EOP_AND_IMM(1, 1, 0, 0x70);
455 EOP_ADD_IMM(1, 1, 0, 0x10);
456 } else {
457 EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
458 EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
459 }
89fea1e9 460 EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
461 EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
462 EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
463 if (r&3)
464 EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
465 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
466 if (mod == 2)
467 EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
468 else EOP_ADD_REG2_LSL(reg,reg,3,2);
469 EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
470 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
471 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
a6fb500b 472 }
473 else if (known_regb & (1 << (r + 8)))
474 {
475 int modulo = (1 << modulo_shift) - 1;
5d817c91 476 if (mod == 2)
89fea1e9 477 known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
478 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
a6fb500b 479 }
480 else
481 {
5d817c91 482 int reg = (r < 4) ? 8 : 9;
483 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
484 EOP_MOV_REG_ROR(reg,reg,ror);
485 // {add|sub} reg, reg, #1<<shift
89fea1e9 486 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
5d817c91 487 EOP_MOV_REG_ROR(reg,reg,32-ror);
488 }
489}
490
bad5731d 491/* handle writes r0 to (rX). Trashes r1.
492 * fortunately we can ignore modulo increment modes for writes. */
0e4d7ba5 493static void tr_rX_write(int op)
bad5731d 494{
495 if ((op&3) == 3)
496 {
497 int mod = (op>>2) & 3; // direct addressing
498 tr_bank_write((op & 0x100) + mod);
499 }
500 else
501 {
502 int r = (op&3) | ((op>>6)&4);
503 if (known_regb & (1 << (r + 8))) {
504 tr_bank_write((op&0x100) | known_regs.r[r]);
505 } else {
506 int reg = (r < 4) ? 8 : 9;
507 int ror = ((4 - (r&3))*8) & 0x1f;
508 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
509 if (r >= 4)
510 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
511 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
512 else EOP_ADD_REG_LSL(1,7,1,1);
513 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
514 hostreg_r[1] = -1;
515 }
89fea1e9 516 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
517 }
518}
519
520/* read (rX) to r0. Trashes r1-r3. */
521static void tr_rX_read(int r, int mod)
522{
523 if ((r&3) == 3)
524 {
525 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
526 }
527 else
528 {
529 if (known_regb & (1 << (r + 8))) {
6e39239f 530 tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
89fea1e9 531 } else {
532 int reg = (r < 4) ? 8 : 9;
533 int ror = ((4 - (r&3))*8) & 0x1f;
534 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
535 if (r >= 4)
536 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
537 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
538 else EOP_ADD_REG_LSL(1,7,1,1);
539 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
0e4d7ba5 540 hostreg_r[0] = hostreg_r[1] = -1;
89fea1e9 541 }
542 tr_ptrr_mod(r, mod, 1, 1);
bad5731d 543 }
544}
545
0e4d7ba5 546/* read ((rX)) to r0. Trashes r1,r2. */
547static void tr_rX_read2(int op)
548{
549 int r = (op&3) | ((op>>6)&4); // src
550
551 if ((r&3) == 3) {
552 tr_bank_read((op&0x100) | ((op>>2)&3));
553 } else if (known_regb & (1 << (r+8))) {
554 tr_bank_read((op&0x100) | known_regs.r[r]);
555 } else {
556 int reg = (r < 4) ? 8 : 9;
557 int ror = ((4 - (r&3))*8) & 0x1f;
558 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
559 if (r >= 4)
560 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
561 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
562 else EOP_ADD_REG_LSL(1,7,1,1);
563 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
564 }
565 EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
566 EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
567 EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
568 if ((r&3) == 3) {
569 tr_bank_write((op&0x100) | ((op>>2)&3));
570 } else if (known_regb & (1 << (r+8))) {
571 tr_bank_write((op&0x100) | known_regs.r[r]);
572 } else {
573 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
574 hostreg_r[1] = -1;
575 }
576 EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
577 hostreg_r[0] = hostreg_r[2] = -1;
578}
89fea1e9 579
2385f273 580// check if AL is going to be used later in block
581static int tr_predict_al_need(void)
582{
583 int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
584
585 while (1)
586 {
587 op = PROGRAM(pc);
588 switch (op >> 9)
589 {
590 // ld d, s
591 case 0x00:
592 tmpv2 = (op >> 4) & 0xf; // dst
593 tmpv = op & 0xf; // src
594 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
595 return 0;
596 break;
597
598 // ld (ri), s
599 case 0x02:
600 // ld ri, s
601 case 0x0a:
602 // OP a, s
603 case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
604 tmpv = op & 0xf; // src
605 if (tmpv == SSP_AL) // OP *, AL
606 return 1;
607 break;
608
609 case 0x04:
610 case 0x06:
611 case 0x14:
612 case 0x34:
613 case 0x44:
614 case 0x64:
615 case 0x74: pc++; break;
616
617 // call cond, addr
618 case 0x24:
619 // bra cond, addr
620 case 0x26:
621 // mod cond, op
622 case 0x48:
623 // mpys?
624 case 0x1b:
625 // mpya (rj), (ri), b
626 case 0x4b: return 1;
627
628 // mld (rj), (ri), b
629 case 0x5b: return 0; // cleared anyway
630
631 // and A, *
632 case 0x50:
633 tmpv = op & 0xf; // src
634 if (tmpv == SSP_AL) return 1;
635 case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
636 return 0;
637 }
638 pc++;
639 }
640}
641
642
bad5731d 643/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
644static int tr_cond_check(int op)
645{
6e39239f 646 int f = (op & 0x100) >> 8;
bad5731d 647 switch (op&0xf0) {
648 case 0x00: return A_COND_AL; /* always true */
649 case 0x50: /* Z matches f(?) bit */
650 if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
651 EOP_TST_IMM(6, 0, 4);
652 return f ? A_COND_NE : A_COND_EQ;
653 case 0x70: /* N matches f(?) bit */
654 if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
655 EOP_TST_IMM(6, 0, 8);
656 return f ? A_COND_NE : A_COND_EQ;
657 default:
2d2247c2 658 elprintf(EL_ANOMALY, "unimplemented cond?\n");
6e39239f 659 tr_unhandled();
bad5731d 660 return 0;
661 }
662}
663
664static int tr_neg_cond(int cond)
665{
666 switch (cond) {
2d2247c2 667 case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
bad5731d 668 case A_COND_EQ: return A_COND_NE;
669 case A_COND_NE: return A_COND_EQ;
670 case A_COND_MI: return A_COND_PL;
671 case A_COND_PL: return A_COND_MI;
2d2247c2 672 default: elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
bad5731d 673 }
674 return 0;
675}
676
ede7220f 677static int tr_aop_ssp2arm(int op)
678{
679 switch (op) {
680 case 1: return A_OP_SUB;
681 case 3: return A_OP_CMP;
682 case 4: return A_OP_ADD;
683 case 5: return A_OP_AND;
684 case 6: return A_OP_ORR;
685 case 7: return A_OP_EOR;
686 }
687
688 tr_unhandled();
689 return 0;
690}
691
692// -----------------------------------------------------
693
b9c1d012 694//@ r4: XXYY
695//@ r5: A
696//@ r6: STACK and emu flags
697//@ r7: SSP context
698//@ r10: P
699
bad5731d 700// read general reg to r0. Trashes r1
d5276282 701static void tr_GR0_to_r0(int op)
d274c33b 702{
703 tr_mov16(0, 0xffff);
704}
705
d5276282 706static void tr_X_to_r0(int op)
d274c33b 707{
708 if (hostreg_r[0] != (SSP_X<<16)) {
709 EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
710 hostreg_r[0] = SSP_X<<16;
711 }
712}
713
d5276282 714static void tr_Y_to_r0(int op)
d274c33b 715{
d274c33b 716 if (hostreg_r[0] != (SSP_Y<<16)) {
717 EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
718 hostreg_r[0] = SSP_Y<<16;
719 }
720}
721
d5276282 722static void tr_A_to_r0(int op)
d274c33b 723{
724 if (hostreg_r[0] != (SSP_A<<16)) {
725 EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
726 hostreg_r[0] = SSP_A<<16;
727 }
728}
729
d5276282 730static void tr_ST_to_r0(int op)
d274c33b 731{
732 // VR doesn't need much accuracy here..
733 EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
734 EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
735 hostreg_r[0] = -1;
736}
737
d5276282 738static void tr_STACK_to_r0(int op)
d274c33b 739{
740 // 448
741 EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
742 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
743 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
744 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
745 EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
746 hostreg_r[0] = hostreg_r[1] = -1;
747}
748
d5276282 749static void tr_PC_to_r0(int op)
d274c33b 750{
bad5731d 751 tr_mov16(0, known_regs.gr[SSP_PC].h);
d274c33b 752}
753
d5276282 754static void tr_P_to_r0(int op)
d274c33b 755{
756 tr_flush_dirty_P();
757 EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
758 hostreg_r[0] = -1;
759}
d5276282 760
761static void tr_AL_to_r0(int op)
ede7220f 762{
d5276282 763 if (op == 0x000f) {
764 if (known_regb & KRREG_PMC) {
765 known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
766 } else {
767 EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status
768 EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
769 EOP_STR_IMM(0,7,0x484);
770 }
771 }
772
773 if (hostreg_r[0] != (SSP_AL<<16)) {
774 EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5
775 hostreg_r[0] = SSP_AL<<16;
776 }
ede7220f 777}
ede7220f 778
d5276282 779static void tr_PMX_to_r0(int reg)
ede7220f 780{
ede7220f 781 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
782 {
d5276282 783 known_regs.pmac_read[reg] = known_regs.pmc.v;
ede7220f 784 known_regs.emu_status &= ~SSP_PMC_SET;
0336d643 785 known_regb |= 1 << (20+reg);
d5276282 786 dirty_regb |= 1 << (20+reg);
787 return;
ede7220f 788 }
789
d5276282 790 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
ede7220f 791 {
d5276282 792 u32 pmcv = known_regs.pmac_read[reg];
793 int mode = pmcv>>16;
794 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
795
ede7220f 796 if ((mode & 0xfff0) == 0x0800)
797 {
ede7220f 798 EOP_LDR_IMM(1,7,0x488); // rom_ptr
65c75cb0 799 emith_move_r_imm(0, (pmcv&0xfffff)<<1);
ede7220f 800 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
d5276282 801 known_regs.pmac_read[reg] += 1;
ede7220f 802 }
803 else if ((mode & 0x47ff) == 0x0018) // DRAM
804 {
805 int inc = get_inc(mode);
ede7220f 806 EOP_LDR_IMM(1,7,0x490); // dram_ptr
65c75cb0 807 emith_move_r_imm(0, (pmcv&0xffff)<<1);
ede7220f 808 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
d5276282 809 if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
ede7220f 810 {
811 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
812 tr_flush_dirty_ST();
813 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
814 EOP_TST_REG_SIMPLE(0,0);
71bb1b7b 815 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024
d5276282 816 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
ede7220f 817 EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
818 }
d5276282 819 known_regs.pmac_read[reg] += inc;
ede7220f 820 }
821 else
822 {
823 tr_unhandled();
824 }
d5276282 825 known_regs.pmc.v = known_regs.pmac_read[reg];
826 //known_regb |= KRREG_PMC;
827 dirty_regb |= KRREG_PMC;
828 dirty_regb |= 1 << (20+reg);
829 hostreg_r[0] = hostreg_r[1] = -1;
830 return;
831 }
ede7220f 832
d5276282 833 known_regb &= ~KRREG_PMC;
834 dirty_regb &= ~KRREG_PMC;
835 known_regb &= ~(1 << (20+reg));
836 dirty_regb &= ~(1 << (20+reg));
837
838 // call the C code to handle this
839 tr_flush_dirty_ST();
840 //tr_flush_dirty_pmcrs();
841 tr_mov16(0, reg);
65c75cb0 842 emith_call(ssp_pm_read);
d5276282 843 hostreg_clear();
844}
845
846static void tr_PM0_to_r0(int op)
847{
848 tr_PMX_to_r0(0);
849}
850
851static void tr_PM1_to_r0(int op)
852{
853 tr_PMX_to_r0(1);
854}
855
856static void tr_PM2_to_r0(int op)
857{
858 tr_PMX_to_r0(2);
859}
860
861static void tr_XST_to_r0(int op)
862{
863 EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400
864 EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
865}
866
867static void tr_PM4_to_r0(int op)
868{
869 tr_PMX_to_r0(4);
870}
871
872static void tr_PMC_to_r0(int op)
873{
874 if (known_regb & KRREG_PMC)
875 {
876 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
877 known_regs.emu_status |= SSP_PMC_SET;
878 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
879 // do nothing - this is handled elsewhere
880 } else {
881 tr_mov16(0, known_regs.pmc.l);
882 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
883 }
884 }
885 else
886 {
887 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
888 tr_flush_dirty_ST();
889 if (op != 0x000e)
890 EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
891 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
892 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
893 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
894 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
895 EOP_STR_IMM(1,7,0x484);
896 hostreg_r[0] = hostreg_r[1] = -1;
ede7220f 897 }
ede7220f 898}
899
d274c33b 900
d5276282 901typedef void (tr_read_func)(int op);
d274c33b 902
d5276282 903static tr_read_func *tr_read_funcs[16] =
d274c33b 904{
905 tr_GR0_to_r0,
906 tr_X_to_r0,
907 tr_Y_to_r0,
908 tr_A_to_r0,
909 tr_ST_to_r0,
910 tr_STACK_to_r0,
911 tr_PC_to_r0,
d5276282 912 tr_P_to_r0,
913 tr_PM0_to_r0,
914 tr_PM1_to_r0,
915 tr_PM2_to_r0,
916 tr_XST_to_r0,
917 tr_PM4_to_r0,
918 (tr_read_func *)tr_unhandled,
919 tr_PMC_to_r0,
920 tr_AL_to_r0
d274c33b 921};
922
923
b9c1d012 924// write r0 to general reg handlers. Trashes r1
6e39239f 925#define TR_WRITE_R0_TO_REG(reg) \
926{ \
927 hostreg_sspreg_changed(reg); \
928 hostreg_r[0] = (reg)<<16; \
929 if (const_val != -1) { \
930 known_regs.gr[reg].h = const_val; \
931 known_regb |= 1 << (reg); \
932 } else { \
933 known_regb &= ~(1 << (reg)); \
934 } \
b9c1d012 935}
936
6e39239f 937static void tr_r0_to_GR0(int const_val)
b9c1d012 938{
939 // do nothing
940}
941
6e39239f 942static void tr_r0_to_X(int const_val)
b9c1d012 943{
944 EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
945 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
946 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
6e39239f 947 dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
948 TR_WRITE_R0_TO_REG(SSP_X);
b9c1d012 949}
950
6e39239f 951static void tr_r0_to_Y(int const_val)
b9c1d012 952{
953 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
954 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
955 EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
bad5731d 956 dirty_regb |= KRREG_P;
6e39239f 957 TR_WRITE_R0_TO_REG(SSP_Y);
b9c1d012 958}
959
6e39239f 960static void tr_r0_to_A(int const_val)
b9c1d012 961{
2385f273 962 if (tr_predict_al_need()) {
963 EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
964 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
965 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
966 }
967 else
968 EOP_MOV_REG_LSL(5, 0, 16);
6e39239f 969 TR_WRITE_R0_TO_REG(SSP_A);
b9c1d012 970}
971
6e39239f 972static void tr_r0_to_ST(int const_val)
b9c1d012 973{
974 // VR doesn't need much accuracy here..
975 EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
976 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
977 EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
6e39239f 978 TR_WRITE_R0_TO_REG(SSP_ST);
b9c1d012 979 hostreg_r[1] = -1;
6e39239f 980 dirty_regb &= ~KRREG_ST;
b9c1d012 981}
982
6e39239f 983static void tr_r0_to_STACK(int const_val)
b9c1d012 984{
985 // 448
986 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
987 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
d274c33b 988 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
b9c1d012 989 EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
d274c33b 990 EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
b9c1d012 991 hostreg_r[1] = -1;
992}
993
6e39239f 994static void tr_r0_to_PC(int const_val)
b9c1d012 995{
45883918 996/*
997 * do nothing - dispatcher will take care of this
b9c1d012 998 EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
d274c33b 999 EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
b9c1d012 1000 hostreg_r[1] = -1;
45883918 1001*/
b9c1d012 1002}
1003
d5276282 1004static void tr_r0_to_AL(int const_val)
1005{
1006 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16
1007 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
1008 EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16
1009 hostreg_sspreg_changed(SSP_AL);
1010 if (const_val != -1) {
1011 known_regs.gr[SSP_A].l = const_val;
1012 known_regb |= 1 << SSP_AL;
1013 } else
1014 known_regb &= ~(1 << SSP_AL);
1015}
1016
1017static void tr_r0_to_PMX(int reg)
1018{
d5276282 1019 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1020 {
1021 known_regs.pmac_write[reg] = known_regs.pmc.v;
1022 known_regs.emu_status &= ~SSP_PMC_SET;
1023 known_regb |= 1 << (25+reg);
1024 dirty_regb |= 1 << (25+reg);
1025 return;
1026 }
0b5e8296 1027
d5276282 1028 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1029 {
1030 int mode, addr;
1031
1032 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1033
1034 mode = known_regs.pmac_write[reg]>>16;
1035 addr = known_regs.pmac_write[reg]&0xffff;
1036 if ((mode & 0x43ff) == 0x0018) // DRAM
1037 {
1038 int inc = get_inc(mode);
1039 if (mode & 0x0400) tr_unhandled();
1040 EOP_LDR_IMM(1,7,0x490); // dram_ptr
65c75cb0 1041 emith_move_r_imm(2, addr << 1);
d5276282 1042 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1043 known_regs.pmac_write[reg] += inc;
1044 }
1045 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1046 {
1047 if (mode & 0x0400) tr_unhandled();
1048 EOP_LDR_IMM(1,7,0x490); // dram_ptr
65c75cb0 1049 emith_move_r_imm(2, addr << 1);
d5276282 1050 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1051 known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1052 }
1053 else if ((mode & 0x47ff) == 0x001c) // IRAM
1054 {
1055 int inc = get_inc(mode);
1056 EOP_LDR_IMM(1,7,0x48c); // iram_ptr
65c75cb0 1057 emith_move_r_imm(2, (addr&0x3ff) << 1);
d5276282 1058 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
e122fae6 1059 EOP_MOV_IMM(1,0,1);
1060 EOP_STR_IMM(1,7,0x494); // iram_dirty
d5276282 1061 known_regs.pmac_write[reg] += inc;
1062 }
1063 else
1064 tr_unhandled();
1065
1066 known_regs.pmc.v = known_regs.pmac_write[reg];
1067 //known_regb |= KRREG_PMC;
1068 dirty_regb |= KRREG_PMC;
1069 dirty_regb |= 1 << (25+reg);
1070 hostreg_r[1] = hostreg_r[2] = -1;
e122fae6 1071 return;
d5276282 1072 }
1073
1074 known_regb &= ~KRREG_PMC;
1075 dirty_regb &= ~KRREG_PMC;
1076 known_regb &= ~(1 << (25+reg));
1077 dirty_regb &= ~(1 << (25+reg));
d5276282 1078
1079 // call the C code to handle this
1080 tr_flush_dirty_ST();
1081 //tr_flush_dirty_pmcrs();
1082 tr_mov16(1, reg);
65c75cb0 1083 emith_call(ssp_pm_write);
d5276282 1084 hostreg_clear();
1085}
1086
1087static void tr_r0_to_PM0(int const_val)
1088{
1089 tr_r0_to_PMX(0);
1090}
1091
1092static void tr_r0_to_PM1(int const_val)
1093{
1094 tr_r0_to_PMX(1);
1095}
1096
1097static void tr_r0_to_PM2(int const_val)
1098{
1099 tr_r0_to_PMX(2);
1100}
1101
1102static void tr_r0_to_PM4(int const_val)
1103{
1104 tr_r0_to_PMX(4);
1105}
1106
1107static void tr_r0_to_PMC(int const_val)
1108{
1109 if ((known_regb & KRREG_PMC) && const_val != -1)
1110 {
1111 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1112 known_regs.emu_status |= SSP_PMC_SET;
1113 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1114 known_regs.pmc.h = const_val;
1115 } else {
1116 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1117 known_regs.pmc.l = const_val;
1118 }
1119 }
1120 else
1121 {
1122 tr_flush_dirty_ST();
1123 if (known_regb & KRREG_PMC) {
65c75cb0 1124 emith_move_r_imm(1, known_regs.pmc.v);
d5276282 1125 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1126 known_regb &= ~KRREG_PMC;
1127 dirty_regb &= ~KRREG_PMC;
1128 }
1129 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
1130 EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400
1131 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1132 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC]
1133 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1134 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1135 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1136 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
1137 EOP_STR_IMM(1,7,0x484);
1138 hostreg_r[1] = hostreg_r[2] = -1;
1139 }
1140}
1141
6e39239f 1142typedef void (tr_write_func)(int const_val);
b9c1d012 1143
d5276282 1144static tr_write_func *tr_write_funcs[16] =
b9c1d012 1145{
1146 tr_r0_to_GR0,
1147 tr_r0_to_X,
1148 tr_r0_to_Y,
1149 tr_r0_to_A,
1150 tr_r0_to_ST,
1151 tr_r0_to_STACK,
1152 tr_r0_to_PC,
d5276282 1153 (tr_write_func *)tr_unhandled,
1154 tr_r0_to_PM0,
1155 tr_r0_to_PM1,
1156 tr_r0_to_PM2,
1157 (tr_write_func *)tr_unhandled,
1158 tr_r0_to_PM4,
1159 (tr_write_func *)tr_unhandled,
1160 tr_r0_to_PMC,
1161 tr_r0_to_AL
b9c1d012 1162};
1163
0e4d7ba5 1164static void tr_mac_load_XY(int op)
1165{
1166 tr_rX_read(op&3, (op>>2)&3); // X
1167 EOP_MOV_REG_LSL(4, 0, 16);
1168 tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1169 EOP_ORR_REG_SIMPLE(4, 0);
1170 dirty_regb |= KRREG_P;
1171 hostreg_sspreg_changed(SSP_X);
1172 hostreg_sspreg_changed(SSP_Y);
1173 known_regb &= ~KRREG_X;
1174 known_regb &= ~KRREG_Y;
1175}
1176
ede7220f 1177// -----------------------------------------------------
1178
ede7220f 1179static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
0e4d7ba5 1180{
ede7220f 1181 u32 pmcv, tmpv;
1182 if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1183
1184 // programming PMC:
1185 // ldi PMC, imm1
1186 // ldi PMC, imm2
1187 (*pc)++;
1188 pmcv = imm | (PROGRAM((*pc)++) << 16);
d5276282 1189 known_regs.pmc.v = pmcv;
ede7220f 1190 known_regb |= KRREG_PMC;
d5276282 1191 dirty_regb |= KRREG_PMC;
ede7220f 1192 known_regs.emu_status |= SSP_PMC_SET;
71bb1b7b 1193 n_in_ops++;
ede7220f 1194
1195 // check for possible reg programming
1196 tmpv = PROGRAM(*pc);
1197 if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1198 {
1199 int is_write = (tmpv & 0xff8f) == 0x80;
1200 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1201 if (reg > 4) tr_unhandled();
d5276282 1202 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
b8a1c09a 1203 if (is_write)
1204 known_regs.pmac_write[reg] = pmcv;
1205 else
1206 known_regs.pmac_read[reg] = pmcv;
ede7220f 1207 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
d5276282 1208 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
ede7220f 1209 known_regs.emu_status &= ~SSP_PMC_SET;
1210 (*pc)++;
71bb1b7b 1211 n_in_ops++;
ede7220f 1212 return 5;
0e4d7ba5 1213 }
1214
d5276282 1215 tr_unhandled();
ede7220f 1216 return 4;
1217}
1218
1219static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1220
1221static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1222{
1223 // ldi ST, 0
1224 // ldi PM0, 0
1225 // ldi PM0, 0
1226 // ldi ST, 60h
1227 unsigned short *pp;
1228 if (op != 0x0840 || imm != 0) return 0;
1229 pp = PROGRAM_P(*pc);
1230 if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1231
1232 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
1233 EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
1234 hostreg_sspreg_changed(SSP_ST);
1235 known_regs.gr[SSP_ST].h = 0x60;
1236 known_regb |= 1 << SSP_ST;
1237 dirty_regb &= ~KRREG_ST;
1238 (*pc) += 3*2;
71bb1b7b 1239 n_in_ops += 3;
ede7220f 1240 return 4*2;
0e4d7ba5 1241}
5d817c91 1242
d5276282 1243static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1244{
1245 // @ 3DA2 and 426A
1246 // ld PMC, (r3|00)
1247 // ld (r3|00), PMC
1248 // ld -, AL
1249 if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1250
1251 tr_bank_read(0);
1252 EOP_MOV_REG_LSL(0, 0, 4);
1253 EOP_ORR_REG_LSR(0, 0, 0, 16);
1254 tr_bank_write(0);
1255 (*pc) += 2;
71bb1b7b 1256 n_in_ops += 2;
d5276282 1257 return 3;
1258}
1259
ede7220f 1260// -----------------------------------------------------
1261
45883918 1262static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
5d817c91 1263{
0e4d7ba5 1264 u32 tmpv, tmpv2, tmpv3;
5d817c91 1265 int ret = 0;
bad5731d 1266 known_regs.gr[SSP_PC].h = *pc;
5d817c91 1267
e807ac75 1268 switch (op >> 9)
1269 {
1270 // ld d, s
f48f5e3b 1271 case 0x00:
5d817c91 1272 if (op == 0) { ret++; break; } // nop
d274c33b 1273 tmpv = op & 0xf; // src
1274 tmpv2 = (op >> 4) & 0xf; // dst
d274c33b 1275 if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1276 tr_flush_dirty_P();
1277 EOP_MOV_REG_SIMPLE(5, 10);
d5276282 1278 hostreg_sspreg_changed(SSP_A);
bad5731d 1279 known_regb &= ~(KRREG_A|KRREG_AL);
d274c33b 1280 ret++; break;
1281 }
d5276282 1282 tr_read_funcs[tmpv](op);
6e39239f 1283 tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
45883918 1284 if (tmpv2 == SSP_PC) {
1285 ret |= 0x10000;
1286 *end_cond = -A_COND_AL;
1287 }
bad5731d 1288 ret++; break;
1289
1290 // ld d, (ri)
89fea1e9 1291 case 0x01: {
89fea1e9 1292 int r = (op&3) | ((op>>6)&4);
1293 int mod = (op>>2)&3;
1294 tmpv = (op >> 4) & 0xf; // dst
d5276282 1295 ret = tr_detect_rotate(op, pc, imm);
1296 if (ret > 0) break;
89fea1e9 1297 if (tmpv != 0)
2385f273 1298 tr_rX_read(r, mod);
1299 else {
1300 int cnt = 1;
1301 while (PROGRAM(*pc) == op) {
1302 (*pc)++; cnt++; ret++;
1303 n_in_ops++;
1304 }
1305 tr_ptrr_mod(r, mod, 1, cnt); // skip
1306 }
6e39239f 1307 tr_write_funcs[tmpv](-1);
45883918 1308 if (tmpv == SSP_PC) {
1309 ret |= 0x10000;
1310 *end_cond = -A_COND_AL;
1311 }
89fea1e9 1312 ret++; break;
1313 }
bad5731d 1314
1315 // ld (ri), s
1316 case 0x02:
1317 tmpv = (op >> 4) & 0xf; // src
d5276282 1318 tr_read_funcs[tmpv](op);
0e4d7ba5 1319 tr_rX_write(op);
d274c33b 1320 ret++; break;
f48f5e3b 1321
1322 // ld a, adr
1323 case 0x03:
5d817c91 1324 tr_bank_read(op&0x1ff);
6e39239f 1325 tr_r0_to_A(-1);
5d817c91 1326 ret++; break;
1327
b9c1d012 1328 // ldi d, imm
1329 case 0x04:
ede7220f 1330 tmpv = (op & 0xf0) >> 4; // dst
1331 ret = tr_detect_pm0_block(op, pc, imm);
1332 if (ret > 0) break;
ede7220f 1333 ret = tr_detect_set_pm(op, pc, imm);
1334 if (ret > 0) break;
0b5e8296 1335 tr_mov16(0, imm);
1336 tr_write_funcs[tmpv](imm);
45883918 1337 if (tmpv == SSP_PC) {
1338 ret |= 0x10000;
1339 *jump_pc = imm;
1340 }
0b5e8296 1341 ret += 2; break;
b9c1d012 1342
bad5731d 1343 // ld d, ((ri))
0e4d7ba5 1344 case 0x05:
bad5731d 1345 tmpv2 = (op >> 4) & 0xf; // dst
0e4d7ba5 1346 tr_rX_read2(op);
6e39239f 1347 tr_write_funcs[tmpv2](-1);
45883918 1348 if (tmpv2 == SSP_PC) {
1349 ret |= 0x10000;
1350 *end_cond = -A_COND_AL;
1351 }
0e4d7ba5 1352 ret += 3; break;
b9c1d012 1353
5d817c91 1354 // ldi (ri), imm
1355 case 0x06:
5d817c91 1356 tr_mov16(0, imm);
0e4d7ba5 1357 tr_rX_write(op);
a6fb500b 1358 ret += 2; break;
f48f5e3b 1359
1360 // ld adr, a
1361 case 0x07:
d5276282 1362 tr_A_to_r0(op);
5d817c91 1363 tr_bank_write(op&0x1ff);
1364 ret++; break;
1365
d274c33b 1366 // ld d, ri
1367 case 0x09: {
bad5731d 1368 int r;
d274c33b 1369 r = (op&3) | ((op>>6)&4); // src
bad5731d 1370 tmpv2 = (op >> 4) & 0xf; // dst
bad5731d 1371 if ((r&3) == 3) tr_unhandled();
d274c33b 1372
bad5731d 1373 if (known_regb & (1 << (r+8))) {
1374 tr_mov16(0, known_regs.r[r]);
6e39239f 1375 tr_write_funcs[tmpv2](known_regs.r[r]);
d274c33b 1376 } else {
bad5731d 1377 int reg = (r < 4) ? 8 : 9;
d274c33b 1378 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1379 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1380 hostreg_r[0] = -1;
6e39239f 1381 tr_write_funcs[tmpv2](-1);
d274c33b 1382 }
d274c33b 1383 ret++; break;
1384 }
1385
bad5731d 1386 // ld ri, s
1387 case 0x0a: {
1388 int r;
1389 r = (op&3) | ((op>>6)&4); // dst
1390 tmpv = (op >> 4) & 0xf; // src
bad5731d 1391 if ((r&3) == 3) tr_unhandled();
1392
1393 if (known_regb & (1 << tmpv)) {
1394 known_regs.r[r] = known_regs.gr[tmpv].h;
1395 known_regb |= 1 << (r + 8);
1396 dirty_regb |= 1 << (r + 8);
1397 } else {
1398 int reg = (r < 4) ? 8 : 9;
1399 int ror = ((4 - (r&3))*8) & 0x1f;
d5276282 1400 tr_read_funcs[tmpv](op);
bad5731d 1401 EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask>
1402 EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff
1403 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl
1404 hostreg_r[0] = -1;
1405 known_regb &= ~(1 << (r+8));
1406 dirty_regb &= ~(1 << (r+8));
1407 }
1408 ret++; break;
1409 }
1410
5d817c91 1411 // ldi ri, simm
67c81ee2 1412 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
5d817c91 1413 tmpv = (op>>8)&7;
bad5731d 1414 known_regs.r[tmpv] = op;
1415 known_regb |= 1 << (tmpv + 8);
5d817c91 1416 dirty_regb |= 1 << (tmpv + 8);
1417 ret++; break;
bad5731d 1418
a6fb500b 1419 // call cond, addr
6e39239f 1420 case 0x24: {
1421 u32 *jump_op = NULL;
a6fb500b 1422 tmpv = tr_cond_check(op);
6e39239f 1423 if (tmpv != A_COND_AL) {
1424 jump_op = tcache_ptr;
1425 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1426 }
1427 tr_mov16(0, *pc);
1428 tr_r0_to_STACK(*pc);
1429 if (tmpv != A_COND_AL) {
1430 u32 *real_ptr = tcache_ptr;
1431 tcache_ptr = jump_op;
1432 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1433 tcache_ptr = real_ptr;
1434 }
a6fb500b 1435 tr_mov16_cond(tmpv, 0, imm);
45883918 1436 if (tmpv != A_COND_AL)
a6fb500b 1437 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
6e39239f 1438 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ede7220f 1439 ret |= 0x10000;
45883918 1440 *end_cond = tmpv;
1441 *jump_pc = imm;
a6fb500b 1442 ret += 2; break;
6e39239f 1443 }
a6fb500b 1444
bad5731d 1445 // ld d, (a)
1446 case 0x25:
bad5731d 1447 tmpv2 = (op >> 4) & 0xf; // dst
d5276282 1448 tr_A_to_r0(op);
bad5731d 1449 EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
1450 EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
1451 EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
1452 hostreg_r[0] = hostreg_r[1] = -1;
6e39239f 1453 tr_write_funcs[tmpv2](-1);
45883918 1454 if (tmpv2 == SSP_PC) {
1455 ret |= 0x10000;
1456 *end_cond = -A_COND_AL;
1457 }
a6fb500b 1458 ret += 3; break;
bad5731d 1459
1460 // bra cond, addr
a6fb500b 1461 case 0x26:
bad5731d 1462 tmpv = tr_cond_check(op);
1463 tr_mov16_cond(tmpv, 0, imm);
45883918 1464 if (tmpv != A_COND_AL)
bad5731d 1465 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
6e39239f 1466 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ede7220f 1467 ret |= 0x10000;
45883918 1468 *end_cond = tmpv;
1469 *jump_pc = imm;
a6fb500b 1470 ret += 2; break;
bad5731d 1471
89fea1e9 1472 // mod cond, op
89fea1e9 1473 case 0x48: {
1474 // check for repeats of this op
1475 tmpv = 1; // count
1476 while (PROGRAM(*pc) == op && (op & 7) != 6) {
1477 (*pc)++; tmpv++;
71bb1b7b 1478 n_in_ops++;
89fea1e9 1479 }
6e39239f 1480 if ((op&0xf0) != 0) // !always
1481 tr_make_dirty_ST();
1482
89fea1e9 1483 tmpv2 = tr_cond_check(op);
1484 switch (op & 7) {
1485 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1486 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1487 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
6e39239f 1488 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
1489 EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
89fea1e9 1490 hostreg_r[1] = -1; break; // abs
1491 default: tr_unhandled();
1492 }
6e39239f 1493
1494 hostreg_sspreg_changed(SSP_A);
1495 dirty_regb |= KRREG_ST;
1496 known_regb &= ~KRREG_ST;
1497 known_regb &= ~(KRREG_A|KRREG_AL);
89fea1e9 1498 ret += tmpv; break;
1499 }
0e4d7ba5 1500
bad5731d 1501 // mpys?
1502 case 0x1b:
0e4d7ba5 1503 tr_flush_dirty_P();
1504 tr_mac_load_XY(op);
1505 tr_make_dirty_ST();
1506 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1507 hostreg_sspreg_changed(SSP_A);
1508 known_regb &= ~(KRREG_A|KRREG_AL);
1509 dirty_regb |= KRREG_ST;
1510 ret++; break;
bad5731d 1511
1512 // mpya (rj), (ri), b
1513 case 0x4b:
0e4d7ba5 1514 tr_flush_dirty_P();
1515 tr_mac_load_XY(op);
1516 tr_make_dirty_ST();
1517 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1518 hostreg_sspreg_changed(SSP_A);
1519 known_regb &= ~(KRREG_A|KRREG_AL);
1520 dirty_regb |= KRREG_ST;
1521 ret++; break;
bad5731d 1522
1523 // mld (rj), (ri), b
1524 case 0x5b:
0e4d7ba5 1525 EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1526 hostreg_sspreg_changed(SSP_A);
1527 known_regs.gr[SSP_A].v = 0;
bad5731d 1528 known_regb |= (KRREG_A|KRREG_AL);
0e4d7ba5 1529 dirty_regb |= KRREG_ST;
1530 tr_mac_load_XY(op);
1531 ret++; break;
1532
1533 // OP a, s
1534 case 0x10:
1535 case 0x30:
1536 case 0x40:
1537 case 0x50:
1538 case 0x60:
1539 case 0x70:
1540 tmpv = op & 0xf; // src
1541 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1542 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
0e4d7ba5 1543 if (tmpv == SSP_P) {
1544 tr_flush_dirty_P();
1545 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1546 } else if (tmpv == SSP_A) {
1547 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1548 } else {
d5276282 1549 tr_read_funcs[tmpv](op);
0e4d7ba5 1550 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1551 }
1552 hostreg_sspreg_changed(SSP_A);
1553 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1554 dirty_regb |= KRREG_ST;
1555 ret++; break;
1556
1557 // OP a, (ri)
1558 case 0x11:
1559 case 0x31:
1560 case 0x41:
1561 case 0x51:
1562 case 0x61:
1563 case 0x71:
1564 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1565 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1566 tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1567 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1568 hostreg_sspreg_changed(SSP_A);
1569 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1570 dirty_regb |= KRREG_ST;
1571 ret++; break;
1572
1573 // OP a, adr
1574 case 0x13:
1575 case 0x33:
1576 case 0x43:
1577 case 0x53:
1578 case 0x63:
1579 case 0x73:
1580 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1581 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1582 tr_bank_read(op&0x1ff);
1583 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1584 hostreg_sspreg_changed(SSP_A);
1585 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1586 dirty_regb |= KRREG_ST;
1587 ret++; break;
1588
1589 // OP a, imm
1590 case 0x14:
1591 case 0x34:
1592 case 0x44:
1593 case 0x54:
1594 case 0x64:
1595 case 0x74:
1596 tmpv = (op & 0xf0) >> 4;
1597 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1598 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1599 tr_mov16(0, imm);
1600 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1601 hostreg_sspreg_changed(SSP_A);
1602 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1603 dirty_regb |= KRREG_ST;
1604 ret += 2; break;
1605
1606 // OP a, ((ri))
1607 case 0x15:
1608 case 0x35:
1609 case 0x45:
1610 case 0x55:
1611 case 0x65:
1612 case 0x75:
1613 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1614 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1615 tr_rX_read2(op);
1616 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1617 hostreg_sspreg_changed(SSP_A);
1618 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1619 dirty_regb |= KRREG_ST;
1620 ret += 3; break;
1621
1622 // OP a, ri
1623 case 0x19:
1624 case 0x39:
1625 case 0x49:
1626 case 0x59:
1627 case 0x69:
1628 case 0x79: {
1629 int r;
1630 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1631 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1632 r = (op&3) | ((op>>6)&4); // src
1633 if ((r&3) == 3) tr_unhandled();
1634
1635 if (known_regb & (1 << (r+8))) {
1636 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
1637 } else {
1638 int reg = (r < 4) ? 8 : 9;
1639 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1640 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1641 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1642 hostreg_r[0] = -1;
1643 }
1644 hostreg_sspreg_changed(SSP_A);
1645 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1646 dirty_regb |= KRREG_ST;
1647 ret++; break;
1648 }
1649
1650 // OP simm
1651 case 0x1c:
1652 case 0x3c:
1653 case 0x4c:
1654 case 0x5c:
1655 case 0x6c:
1656 case 0x7c:
1657 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1658 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1659 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
1660 hostreg_sspreg_changed(SSP_A);
1661 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1662 dirty_regb |= KRREG_ST;
bad5731d 1663 ret++; break;
e807ac75 1664 }
1665
71bb1b7b 1666 n_in_ops++;
1667
5d817c91 1668 return ret;
e807ac75 1669}
1670
45883918 1671static void emit_block_prologue(void)
1672{
1673 // check if there are enough cycles..
1674 // note: r0 must contain PC of current block
1675 EOP_CMP_IMM(11,0,0); // cmp r11, #0
65c75cb0 1676 emith_jump_cond(A_COND_LE, ssp_drc_end);
45883918 1677}
1678
1679/* cond:
1680 * >0: direct (un)conditional jump
1681 * <0: indirect jump
1682 */
3b708898 1683static void *emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
45883918 1684{
3b708898 1685 void *end_ptr = NULL;
1686
1687 if (cycles > 0xff) {
1688 elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles);
1689 cycles = 0xff;
1690 }
45883918 1691 EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles
1692
1693 if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1694 // indirect jump, or rom -> iram jump, must use dispatcher
65c75cb0 1695 emith_jump(ssp_drc_next);
45883918 1696 }
1697 else if (cond == A_COND_AL) {
679af8a3 1698 u32 *target = (pc < 0x400) ?
1699 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
1700 ssp_block_table[pc];
45883918 1701 if (target != NULL)
65c75cb0 1702 emith_jump(target);
45883918 1703 else {
65c75cb0 1704 int ops = emith_jump(ssp_drc_next);
3b708898 1705 end_ptr = tcache_ptr;
f8af9634 1706 // cause the next block to be emitted over jump instruction
1707 tcache_ptr -= ops;
45883918 1708 }
1709 }
1710 else {
679af8a3 1711 u32 *target1 = (pc < 0x400) ?
1712 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
1713 ssp_block_table[pc];
1714 u32 *target2 = (end_pc < 0x400) ?
1715 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + end_pc] :
1716 ssp_block_table[end_pc];
45883918 1717 if (target1 != NULL)
65c75cb0 1718 emith_jump_cond(cond, target1);
45883918 1719 if (target2 != NULL)
65c75cb0 1720 emith_jump_cond(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
f8af9634 1721#ifndef __EPOC32__
1722 // emit patchable branches
1723 if (target1 == NULL)
65c75cb0 1724 emith_call_cond(cond, ssp_drc_next_patch);
f8af9634 1725 if (target2 == NULL)
65c75cb0 1726 emith_call_cond(tr_neg_cond(cond), ssp_drc_next_patch);
f8af9634 1727#else
1728 // won't patch indirect jumps
1729 if (target1 == NULL || target2 == NULL)
65c75cb0 1730 emith_jump(ssp_drc_next);
f8af9634 1731#endif
45883918 1732 }
3b708898 1733
1734 if (end_ptr == NULL)
1735 end_ptr = tcache_ptr;
1736
1737 return end_ptr;
45883918 1738}
1739
71bb1b7b 1740void *ssp_translate_block(int pc)
726bbb3e 1741{
e807ac75 1742 unsigned int op, op1, imm, ccount = 0;
3b708898 1743 unsigned int *block_start, *block_end;
45883918 1744 int ret, end_cond = A_COND_AL, jump_pc = -1;
5c129565 1745
2d2247c2 1746 //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
f8af9634 1747
5c129565 1748 block_start = tcache_ptr;
bad5731d 1749 known_regb = 0;
1750 dirty_regb = KRREG_P;
d5276282 1751 known_regs.emu_status = 0;
5d817c91 1752 hostreg_clear();
5c129565 1753
1754 emit_block_prologue();
726bbb3e 1755
e807ac75 1756 for (; ccount < 100;)
726bbb3e 1757 {
1758 op = PROGRAM(pc++);
1759 op1 = op >> 9;
e807ac75 1760 imm = (u32)-1;
5c129565 1761
e807ac75 1762 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1763 imm = PROGRAM(pc++); // immediate
5c129565 1764
45883918 1765 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
e807ac75 1766 if (ret <= 0)
1767 {
2d2247c2 1768 elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
1769 //exit(1);
892b1dd2 1770 }
ede7220f 1771
45883918 1772 ccount += ret & 0xffff;
1773 if (ret & 0x10000) break;
726bbb3e 1774 }
5c129565 1775
45883918 1776 if (ccount >= 100) {
1777 end_cond = A_COND_AL;
1778 jump_pc = pc;
65c75cb0 1779 emith_move_r_imm(0, pc);
45883918 1780 }
0b5e8296 1781
89fea1e9 1782 tr_flush_dirty_prs();
1783 tr_flush_dirty_ST();
ede7220f 1784 tr_flush_dirty_pmcrs();
3b708898 1785 block_end = emit_block_epilogue(ccount, end_cond, jump_pc, pc);
726bbb3e 1786
f4bb5d6b 1787 if (tcache_ptr - (u32 *)tcache > DRC_TCACHE_SIZE/4) {
f8af9634 1788 elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n");
726bbb3e 1789 fflush(stdout);
1790 exit(1);
1791 }
1792
1793 // stats
1794 nblocks++;
2d2247c2 1795 //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1796 // (double)(tcache_ptr - tcache) / (double)n_in_ops);
df143b36 1797
5d817c91 1798#ifdef DUMP_BLOCK
5c129565 1799 {
1800 FILE *f = fopen("tcache.bin", "wb");
1801 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1802 fclose(f);
1803 }
43e6eaad 1804 printf("dumped tcache.bin\n");
5c129565 1805 exit(0);
1806#endif
259ed0ea 1807
d4d62665 1808#ifdef __arm__
3b708898 1809 cache_flush_d_inval_i(block_start, block_end);
553c3eaa 1810#endif
259ed0ea 1811
5c129565 1812 return block_start;
726bbb3e 1813}
1814
1815
1816
1817// -----------------------------------------------------
1818
fad24893 1819static void ssp1601_state_load(void)
1820{
1821 ssp->drc.iram_dirty = 1;
1822 ssp->drc.iram_context = 0;
1823}
1824
679af8a3 1825void ssp1601_dyn_exit(void)
1826{
1827 free(ssp_block_table);
1828 free(ssp_block_table_iram);
1829 ssp_block_table = ssp_block_table_iram = NULL;
1830
1831 drc_cmn_cleanup();
1832}
1833
e807ac75 1834int ssp1601_dyn_startup(void)
726bbb3e 1835{
41397701 1836 drc_cmn_init();
1837
679af8a3 1838 ssp_block_table = calloc(sizeof(ssp_block_table[0]), SSP_BLOCKTAB_ENTS);
1839 if (ssp_block_table == NULL)
1840 return -1;
1841 ssp_block_table_iram = calloc(sizeof(ssp_block_table_iram[0]), SSP_BLOCKTAB_IRAM_ENTS);
1842 if (ssp_block_table_iram == NULL) {
1843 free(ssp_block_table);
1844 return -1;
1845 }
1846
1847 memset(tcache, 0, DRC_TCACHE_SIZE);
f4bb5d6b 1848 tcache_ptr = (void *)tcache;
726bbb3e 1849
fad24893 1850 PicoLoadStateHook = ssp1601_state_load;
1851
f5d1115f 1852 n_in_ops = 0;
d4d62665 1853#ifdef __arm__
d5276282 1854 // hle'd blocks
1ca2ea4f 1855 ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1856 ssp_block_table[0x902/2] = (void *) ssp_hle_902;
72f63cf0 1857 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x030/2] = (void *) ssp_hle_07_030;
1858 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x036/2] = (void *) ssp_hle_07_036;
1859 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x6d6/2] = (void *) ssp_hle_07_6d6;
1860 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x12c/2] = (void *) ssp_hle_11_12c;
1861 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x384/2] = (void *) ssp_hle_11_384;
1862 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x38a/2] = (void *) ssp_hle_11_38a;
d5276282 1863#endif
1864
726bbb3e 1865 return 0;
1866}
1867
1868
1869void ssp1601_dyn_reset(ssp1601_t *ssp)
1870{
71bb1b7b 1871 ssp1601_reset(ssp);
1872 ssp->drc.iram_dirty = 1;
1873 ssp->drc.iram_context = 0;
1874 // must do this here because ssp is not available @ startup()
1875 ssp->drc.ptr_rom = (u32) Pico.rom;
1876 ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1877 ssp->drc.ptr_dram = (u32) svp->dram;
1ca2ea4f 1878 ssp->drc.ptr_btable = (u32) ssp_block_table;
1879 ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
45883918 1880
1881 // prevent new versions of IRAM from appearing
1882 memset(svp->iram_rom, 0, 0x800);
726bbb3e 1883}
1884
f8af9634 1885
726bbb3e 1886void ssp1601_dyn_run(int cycles)
1887{
b9c1d012 1888 if (ssp->emu_status & SSP_WAIT_MASK) return;
b9c1d012 1889
fad24893 1890#ifdef DUMP_BLOCK
1891 ssp_translate_block(DUMP_BLOCK >> 1);
1892#endif
d4d62665 1893#ifdef __arm__
f3fe3e5b 1894 ssp_drc_entry(ssp, cycles);
fad24893 1895#endif
726bbb3e 1896}
1897
fast MegaDrive/MegaCD/32X emulator