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32x: interpreter-wrap drc works (demos only). SVP drc refactoring.
[picodrive.git] / pico / carthw / svp / compiler.c
CommitLineData
65ca3034 1// SSP1601 to ARM recompiler
2
3// (c) Copyright 2008, Grazvydas "notaz" Ignotas
4// Free for non-commercial use.
726bbb3e 5
efcba75f 6#include "../../pico_int.h"
41397701 7#include "../../../cpu/drc/cmn.h"
e807ac75 8#include "compiler.h"
726bbb3e 9
679af8a3 10// FIXME: asm has these hardcoded
11#define SSP_BLOCKTAB_ENTS (0x5090/2)
12#define SSP_BLOCKTAB_IRAM_ONE (0x800/2) // table entries
13#define SSP_BLOCKTAB_IRAM_ENTS (15*SSP_BLOCKTAB_IRAM_ONE)
14
15static u32 **ssp_block_table; // [0x5090/2];
16static u32 **ssp_block_table_iram; // [15][0x800/2];
71bb1b7b 17
71bb1b7b 18static u32 *tcache_ptr = NULL;
726bbb3e 19
726bbb3e 20static int nblocks = 0;
71bb1b7b 21static int n_in_ops = 0;
22
23extern ssp1601_t *ssp;
24
25#define rPC ssp->gr[SSP_PC].h
26#define rPMC ssp->gr[SSP_PMC]
27
28#define SSP_FLAG_Z (1<<0xd)
29#define SSP_FLAG_N (1<<0xf)
726bbb3e 30
5d817c91 31#ifndef ARM
679af8a3 32//#define DUMP_BLOCK 0x0c9a
45883918 33void ssp_drc_next(void){}
34void ssp_drc_next_patch(void){}
35void ssp_drc_end(void){}
5d817c91 36#endif
37
5c129565 38#include "gen_arm.c"
726bbb3e 39
40// -----------------------------------------------------
41
71bb1b7b 42static int get_inc(int mode)
892b1dd2 43{
71bb1b7b 44 int inc = (mode >> 11) & 7;
45 if (inc != 0) {
46 if (inc != 7) inc--;
47 inc = 1 << inc; // 0 1 2 4 8 16 32 128
48 if (mode & 0x8000) inc = -inc; // decrement mode
892b1dd2 49 }
71bb1b7b 50 return inc;
892b1dd2 51}
52
ee9ee9fd 53u32 ssp_pm_read(int reg)
d5276282 54{
55 u32 d = 0, mode;
56
57 if (ssp->emu_status & SSP_PMC_SET)
58 {
59 ssp->pmac_read[reg] = rPMC.v;
60 ssp->emu_status &= ~SSP_PMC_SET;
d5276282 61 return 0;
62 }
63
d5276282 64 // just in case
65 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
66
67 mode = ssp->pmac_read[reg]>>16;
68 if ((mode & 0xfff0) == 0x0800) // ROM
69 {
70 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
71 ssp->pmac_read[reg] += 1;
72 }
73 else if ((mode & 0x47ff) == 0x0018) // DRAM
74 {
75 unsigned short *dram = (unsigned short *)svp->dram;
76 int inc = get_inc(mode);
77 d = dram[ssp->pmac_read[reg]&0xffff];
78 ssp->pmac_read[reg] += inc;
79 }
80
81 // PMC value corresponds to last PMR accessed
82 rPMC.v = ssp->pmac_read[reg];
83
84 return d;
85}
86
71bb1b7b 87#define overwrite_write(dst, d) \
88{ \
89 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
90 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
91 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
92 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
93}
94
ee9ee9fd 95void ssp_pm_write(u32 d, int reg)
d5276282 96{
97 unsigned short *dram;
98 int mode, addr;
99
100 if (ssp->emu_status & SSP_PMC_SET)
101 {
102 ssp->pmac_write[reg] = rPMC.v;
103 ssp->emu_status &= ~SSP_PMC_SET;
104 return;
105 }
106
107 // just in case
108 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
109
110 dram = (unsigned short *)svp->dram;
111 mode = ssp->pmac_write[reg]>>16;
112 addr = ssp->pmac_write[reg]&0xffff;
113 if ((mode & 0x43ff) == 0x0018) // DRAM
114 {
115 int inc = get_inc(mode);
116 if (mode & 0x0400) {
117 overwrite_write(dram[addr], d);
118 } else dram[addr] = d;
119 ssp->pmac_write[reg] += inc;
120 }
121 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
122 {
123 if (mode & 0x0400) {
124 overwrite_write(dram[addr], d);
125 } else dram[addr] = d;
34e243f1 126 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
d5276282 127 }
128 else if ((mode & 0x47ff) == 0x001c) // IRAM
129 {
130 int inc = get_inc(mode);
131 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
132 ssp->pmac_write[reg] += inc;
e122fae6 133 ssp->drc.iram_dirty = 1;
d5276282 134 }
135
136 rPMC.v = ssp->pmac_write[reg];
137}
138
139
892b1dd2 140// -----------------------------------------------------
141
0b5e8296 142// 14 IRAM blocks
df143b36 143static unsigned char iram_context_map[] =
144{
145 0, 0, 0, 0, 1, 0, 0, 0, // 04
146 0, 0, 0, 0, 0, 0, 2, 0, // 0e
147 0, 0, 0, 0, 0, 3, 0, 4, // 15 17
148 5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
149 8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
150 0, 0, 0, 0, 0, 0, 0, 0,
151 0, 0,11, 0, 0,12, 0, 0, // 32 35
152 13,14, 0, 0, 0, 0, 0, 0 // 38 39
153};
154
71bb1b7b 155int ssp_get_iram_context(void)
df143b36 156{
157 unsigned char *ir = (unsigned char *)svp->iram_rom;
158 int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
df143b36 159 val1 = iram_context_map[(val>>1)&0x3f];
160
5c129565 161 if (val1 == 0) {
2d2247c2 162 elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
df143b36 163 //debug_dump2file(name, svp->iram_rom, 0x800);
2d2247c2 164 //exit(1);
df143b36 165 }
df143b36 166 return val1;
167}
168
5d817c91 169// -----------------------------------------------------
0b5e8296 170
5d817c91 171/* regs with known values */
172static struct
173{
174 ssp_reg_t gr[8];
175 unsigned char r[8];
ede7220f 176 unsigned int pmac_read[5];
177 unsigned int pmac_write[5];
d5276282 178 ssp_reg_t pmc;
ede7220f 179 unsigned int emu_status;
bad5731d 180} known_regs;
181
182#define KRREG_X (1 << SSP_X)
183#define KRREG_Y (1 << SSP_Y)
184#define KRREG_A (1 << SSP_A) /* AH only */
185#define KRREG_ST (1 << SSP_ST)
186#define KRREG_STACK (1 << SSP_STACK)
187#define KRREG_PC (1 << SSP_PC)
188#define KRREG_P (1 << SSP_P)
189#define KRREG_PR0 (1 << 8)
190#define KRREG_PR4 (1 << 12)
191#define KRREG_AL (1 << 16)
d5276282 192#define KRREG_PMCM (1 << 18) /* only mode word of PMC */
193#define KRREG_PMC (1 << 19)
ede7220f 194#define KRREG_PM0R (1 << 20)
195#define KRREG_PM1R (1 << 21)
196#define KRREG_PM2R (1 << 22)
197#define KRREG_PM3R (1 << 23)
198#define KRREG_PM4R (1 << 24)
199#define KRREG_PM0W (1 << 25)
200#define KRREG_PM1W (1 << 26)
201#define KRREG_PM2W (1 << 27)
202#define KRREG_PM3W (1 << 28)
203#define KRREG_PM4W (1 << 29)
bad5731d 204
205/* bitfield of known register values */
206static u32 known_regb = 0;
207
208/* known vals, which need to be flushed
d5276282 209 * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
bad5731d 210 * ST means flags are being held in ARM PSR
89fea1e9 211 * P means that it needs to be recalculated
bad5731d 212 */
213static u32 dirty_regb = 0;
5d817c91 214
215/* known values of host regs.
d274c33b 216 * -1 - unknown
217 * 000000-00ffff - 16bit value
218 * 100000-10ffff - base reg (r7) + 16bit val
6e39239f 219 * 0r0000 - means reg (low) eq gr[r].h, r != AL
5d817c91 220 */
221static int hostreg_r[4];
222
223static void hostreg_clear(void)
224{
225 int i;
226 for (i = 0; i < 4; i++)
227 hostreg_r[i] = -1;
228}
229
6e39239f 230static void hostreg_sspreg_changed(int sspreg)
5d817c91 231{
232 int i;
233 for (i = 0; i < 4; i++)
6e39239f 234 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
5d817c91 235}
236
726bbb3e 237
ede7220f 238#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
239#define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
726bbb3e 240
ee9ee9fd 241void tr_unhandled(void)
6e39239f 242{
2d2247c2 243 //FILE *f = fopen("tcache.bin", "wb");
244 //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
245 //fclose(f);
246 elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
247 //exit(1);
6e39239f 248}
249
0e4d7ba5 250/* update P, if needed. Trashes r0 */
d274c33b 251static void tr_flush_dirty_P(void)
252{
253 // TODO: const regs
bad5731d 254 if (!(dirty_regb & KRREG_P)) return;
d274c33b 255 EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
0e4d7ba5 256 EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
257 EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
258 EOP_MUL(10, 0, 10); // mul r10, r0, r10
bad5731d 259 dirty_regb &= ~KRREG_P;
0e4d7ba5 260 hostreg_r[0] = -1;
d274c33b 261}
262
89fea1e9 263/* write dirty pr to host reg. Nothing is trashed */
264static void tr_flush_dirty_pr(int r)
265{
266 int ror = 0, reg;
6e39239f 267
89fea1e9 268 if (!(dirty_regb & (1 << (r+8)))) return;
269
270 switch (r&3) {
271 case 0: ror = 0; break;
272 case 1: ror = 24/2; break;
273 case 2: ror = 16/2; break;
274 }
275 reg = (r < 4) ? 8 : 9;
276 EOP_BIC_IMM(reg,reg,ror,0xff);
277 if (known_regs.r[r] != 0)
278 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
279 dirty_regb &= ~(1 << (r+8));
280}
281
282/* write all dirty pr0-pr7 to host regs. Nothing is trashed */
283static void tr_flush_dirty_prs(void)
5d817c91 284{
285 int i, ror = 0, reg;
bad5731d 286 int dirty = dirty_regb >> 8;
2385f273 287 if ((dirty&7) == 7) {
288 emit_mov_const(A_COND_AL, 8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
289 dirty &= ~7;
290 }
291 if ((dirty&0x70) == 0x70) {
292 emit_mov_const(A_COND_AL, 9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
293 dirty &= ~0x70;
294 }
5d817c91 295 /* r0-r7 */
bad5731d 296 for (i = 0; dirty && i < 8; i++, dirty >>= 1)
5d817c91 297 {
bad5731d 298 if (!(dirty&1)) continue;
5d817c91 299 switch (i&3) {
300 case 0: ror = 0; break;
301 case 1: ror = 24/2; break;
302 case 2: ror = 16/2; break;
303 }
304 reg = (i < 4) ? 8 : 9;
305 EOP_BIC_IMM(reg,reg,ror,0xff);
bad5731d 306 if (known_regs.r[i] != 0)
307 EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
5d817c91 308 }
bad5731d 309 dirty_regb &= ~0xff00;
310}
311
89fea1e9 312/* write dirty pr and "forget" it. Nothing is trashed. */
313static void tr_release_pr(int r)
314{
315 tr_flush_dirty_pr(r);
316 known_regb &= ~(1 << (r+8));
317}
318
6e39239f 319/* fush ARM PSR to r6. Trashes r1 */
bad5731d 320static void tr_flush_dirty_ST(void)
321{
322 if (!(dirty_regb & KRREG_ST)) return;
323 EOP_BIC_IMM(6,6,0,0x0f);
6e39239f 324 EOP_MRS(1);
325 EOP_ORR_REG_LSR(6,6,1,28);
bad5731d 326 dirty_regb &= ~KRREG_ST;
6e39239f 327 hostreg_r[1] = -1;
328}
329
330/* inverse of above. Trashes r1 */
331static void tr_make_dirty_ST(void)
332{
333 if (dirty_regb & KRREG_ST) return;
334 if (known_regb & KRREG_ST) {
335 int flags = 0;
336 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
337 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
338 EOP_MSR_IMM(4/2, flags);
339 } else {
340 EOP_MOV_REG_LSL(1, 6, 28);
341 EOP_MSR_REG(1);
342 hostreg_r[1] = -1;
343 }
344 dirty_regb |= KRREG_ST;
bad5731d 345}
346
347/* load 16bit val into host reg r0-r3. Nothing is trashed */
348static void tr_mov16(int r, int val)
349{
350 if (hostreg_r[r] != val) {
351 emit_mov_const(A_COND_AL, r, val);
352 hostreg_r[r] = val;
353 }
354}
355
356static void tr_mov16_cond(int cond, int r, int val)
357{
358 emit_mov_const(cond, r, val);
a6fb500b 359 hostreg_r[r] = -1;
5d817c91 360}
361
45883918 362/* trashes r1 */
ede7220f 363static void tr_flush_dirty_pmcrs(void)
364{
365 u32 i, val = (u32)-1;
d5276282 366 if (!(dirty_regb & 0x3ff80000)) return;
ede7220f 367
d5276282 368 if (dirty_regb & KRREG_PMC) {
369 val = known_regs.pmc.v;
e122fae6 370 emit_mov_const(A_COND_AL, 1, val);
371 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
ede7220f 372
d5276282 373 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
2d2247c2 374 elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
d5276282 375 tr_unhandled();
376 }
ede7220f 377 }
378 for (i = 0; i < 5; i++)
379 {
d5276282 380 if (dirty_regb & (1 << (20+i))) {
ede7220f 381 if (val != known_regs.pmac_read[i]) {
382 val = known_regs.pmac_read[i];
e122fae6 383 emit_mov_const(A_COND_AL, 1, val);
ede7220f 384 }
e122fae6 385 EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
ede7220f 386 }
d5276282 387 if (dirty_regb & (1 << (25+i))) {
ede7220f 388 if (val != known_regs.pmac_write[i]) {
389 val = known_regs.pmac_write[i];
e122fae6 390 emit_mov_const(A_COND_AL, 1, val);
ede7220f 391 }
e122fae6 392 EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
ede7220f 393 }
394 }
d5276282 395 dirty_regb &= ~0x3ff80000;
e122fae6 396 hostreg_r[1] = -1;
ede7220f 397}
398
0e4d7ba5 399/* read bank word to r0 (upper bits zero). Thrashes r1. */
5d817c91 400static void tr_bank_read(int addr) /* word addr 0-0x1ff */
401{
bad5731d 402 int breg = 7;
403 if (addr > 0x7f) {
404 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
405 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
406 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
5d817c91 407 }
bad5731d 408 breg = 1;
5d817c91 409 }
bad5731d 410 EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
5d817c91 411 hostreg_r[0] = -1;
412}
413
414/* write r0 to bank. Trashes r1. */
415static void tr_bank_write(int addr)
416{
417 int breg = 7;
418 if (addr > 0x7f) {
d274c33b 419 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
5d817c91 420 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
d274c33b 421 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
5d817c91 422 }
423 breg = 1;
424 }
b9c1d012 425 EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
5d817c91 426}
427
89fea1e9 428/* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
429static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
5d817c91 430{
a6fb500b 431 int modulo_shift = -1; /* unknown */
5d817c91 432
433 if (mod == 0) return;
434
435 if (!need_modulo || mod == 1) // +!
436 modulo_shift = 8;
bad5731d 437 else if (need_modulo && (known_regb & KRREG_ST)) {
438 modulo_shift = known_regs.gr[SSP_ST].h & 7;
5d817c91 439 if (modulo_shift == 0) modulo_shift = 8;
440 }
441
89fea1e9 442 if (modulo_shift == -1)
443 {
a6fb500b 444 int reg = (r < 4) ? 8 : 9;
89fea1e9 445 tr_release_pr(r);
0e4d7ba5 446 if (dirty_regb & KRREG_ST) {
447 // avoid flushing ARM flags
448 EOP_AND_IMM(1, 6, 0, 0x70);
449 EOP_SUB_IMM(1, 1, 0, 0x10);
450 EOP_AND_IMM(1, 1, 0, 0x70);
451 EOP_ADD_IMM(1, 1, 0, 0x10);
452 } else {
453 EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
454 EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
455 }
89fea1e9 456 EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
457 EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
458 EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
459 if (r&3)
460 EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
461 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
462 if (mod == 2)
463 EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
464 else EOP_ADD_REG2_LSL(reg,reg,3,2);
465 EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
466 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
467 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
a6fb500b 468 }
469 else if (known_regb & (1 << (r + 8)))
470 {
471 int modulo = (1 << modulo_shift) - 1;
5d817c91 472 if (mod == 2)
89fea1e9 473 known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
474 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
a6fb500b 475 }
476 else
477 {
5d817c91 478 int reg = (r < 4) ? 8 : 9;
479 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
480 EOP_MOV_REG_ROR(reg,reg,ror);
481 // {add|sub} reg, reg, #1<<shift
89fea1e9 482 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
5d817c91 483 EOP_MOV_REG_ROR(reg,reg,32-ror);
484 }
485}
486
bad5731d 487/* handle writes r0 to (rX). Trashes r1.
488 * fortunately we can ignore modulo increment modes for writes. */
0e4d7ba5 489static void tr_rX_write(int op)
bad5731d 490{
491 if ((op&3) == 3)
492 {
493 int mod = (op>>2) & 3; // direct addressing
494 tr_bank_write((op & 0x100) + mod);
495 }
496 else
497 {
498 int r = (op&3) | ((op>>6)&4);
499 if (known_regb & (1 << (r + 8))) {
500 tr_bank_write((op&0x100) | known_regs.r[r]);
501 } else {
502 int reg = (r < 4) ? 8 : 9;
503 int ror = ((4 - (r&3))*8) & 0x1f;
504 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
505 if (r >= 4)
506 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
507 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
508 else EOP_ADD_REG_LSL(1,7,1,1);
509 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
510 hostreg_r[1] = -1;
511 }
89fea1e9 512 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
513 }
514}
515
516/* read (rX) to r0. Trashes r1-r3. */
517static void tr_rX_read(int r, int mod)
518{
519 if ((r&3) == 3)
520 {
521 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
522 }
523 else
524 {
525 if (known_regb & (1 << (r + 8))) {
6e39239f 526 tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
89fea1e9 527 } else {
528 int reg = (r < 4) ? 8 : 9;
529 int ror = ((4 - (r&3))*8) & 0x1f;
530 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
531 if (r >= 4)
532 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
533 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
534 else EOP_ADD_REG_LSL(1,7,1,1);
535 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
0e4d7ba5 536 hostreg_r[0] = hostreg_r[1] = -1;
89fea1e9 537 }
538 tr_ptrr_mod(r, mod, 1, 1);
bad5731d 539 }
540}
541
0e4d7ba5 542/* read ((rX)) to r0. Trashes r1,r2. */
543static void tr_rX_read2(int op)
544{
545 int r = (op&3) | ((op>>6)&4); // src
546
547 if ((r&3) == 3) {
548 tr_bank_read((op&0x100) | ((op>>2)&3));
549 } else if (known_regb & (1 << (r+8))) {
550 tr_bank_read((op&0x100) | known_regs.r[r]);
551 } else {
552 int reg = (r < 4) ? 8 : 9;
553 int ror = ((4 - (r&3))*8) & 0x1f;
554 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
555 if (r >= 4)
556 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
557 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
558 else EOP_ADD_REG_LSL(1,7,1,1);
559 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
560 }
561 EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
562 EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
563 EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
564 if ((r&3) == 3) {
565 tr_bank_write((op&0x100) | ((op>>2)&3));
566 } else if (known_regb & (1 << (r+8))) {
567 tr_bank_write((op&0x100) | known_regs.r[r]);
568 } else {
569 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
570 hostreg_r[1] = -1;
571 }
572 EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
573 hostreg_r[0] = hostreg_r[2] = -1;
574}
89fea1e9 575
2385f273 576// check if AL is going to be used later in block
577static int tr_predict_al_need(void)
578{
579 int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
580
581 while (1)
582 {
583 op = PROGRAM(pc);
584 switch (op >> 9)
585 {
586 // ld d, s
587 case 0x00:
588 tmpv2 = (op >> 4) & 0xf; // dst
589 tmpv = op & 0xf; // src
590 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
591 return 0;
592 break;
593
594 // ld (ri), s
595 case 0x02:
596 // ld ri, s
597 case 0x0a:
598 // OP a, s
599 case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
600 tmpv = op & 0xf; // src
601 if (tmpv == SSP_AL) // OP *, AL
602 return 1;
603 break;
604
605 case 0x04:
606 case 0x06:
607 case 0x14:
608 case 0x34:
609 case 0x44:
610 case 0x64:
611 case 0x74: pc++; break;
612
613 // call cond, addr
614 case 0x24:
615 // bra cond, addr
616 case 0x26:
617 // mod cond, op
618 case 0x48:
619 // mpys?
620 case 0x1b:
621 // mpya (rj), (ri), b
622 case 0x4b: return 1;
623
624 // mld (rj), (ri), b
625 case 0x5b: return 0; // cleared anyway
626
627 // and A, *
628 case 0x50:
629 tmpv = op & 0xf; // src
630 if (tmpv == SSP_AL) return 1;
631 case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
632 return 0;
633 }
634 pc++;
635 }
636}
637
638
bad5731d 639/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
640static int tr_cond_check(int op)
641{
6e39239f 642 int f = (op & 0x100) >> 8;
bad5731d 643 switch (op&0xf0) {
644 case 0x00: return A_COND_AL; /* always true */
645 case 0x50: /* Z matches f(?) bit */
646 if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
647 EOP_TST_IMM(6, 0, 4);
648 return f ? A_COND_NE : A_COND_EQ;
649 case 0x70: /* N matches f(?) bit */
650 if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
651 EOP_TST_IMM(6, 0, 8);
652 return f ? A_COND_NE : A_COND_EQ;
653 default:
2d2247c2 654 elprintf(EL_ANOMALY, "unimplemented cond?\n");
6e39239f 655 tr_unhandled();
bad5731d 656 return 0;
657 }
658}
659
660static int tr_neg_cond(int cond)
661{
662 switch (cond) {
2d2247c2 663 case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
bad5731d 664 case A_COND_EQ: return A_COND_NE;
665 case A_COND_NE: return A_COND_EQ;
666 case A_COND_MI: return A_COND_PL;
667 case A_COND_PL: return A_COND_MI;
2d2247c2 668 default: elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
bad5731d 669 }
670 return 0;
671}
672
ede7220f 673static int tr_aop_ssp2arm(int op)
674{
675 switch (op) {
676 case 1: return A_OP_SUB;
677 case 3: return A_OP_CMP;
678 case 4: return A_OP_ADD;
679 case 5: return A_OP_AND;
680 case 6: return A_OP_ORR;
681 case 7: return A_OP_EOR;
682 }
683
684 tr_unhandled();
685 return 0;
686}
687
688// -----------------------------------------------------
689
b9c1d012 690//@ r4: XXYY
691//@ r5: A
692//@ r6: STACK and emu flags
693//@ r7: SSP context
694//@ r10: P
695
bad5731d 696// read general reg to r0. Trashes r1
d5276282 697static void tr_GR0_to_r0(int op)
d274c33b 698{
699 tr_mov16(0, 0xffff);
700}
701
d5276282 702static void tr_X_to_r0(int op)
d274c33b 703{
704 if (hostreg_r[0] != (SSP_X<<16)) {
705 EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
706 hostreg_r[0] = SSP_X<<16;
707 }
708}
709
d5276282 710static void tr_Y_to_r0(int op)
d274c33b 711{
d274c33b 712 if (hostreg_r[0] != (SSP_Y<<16)) {
713 EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
714 hostreg_r[0] = SSP_Y<<16;
715 }
716}
717
d5276282 718static void tr_A_to_r0(int op)
d274c33b 719{
720 if (hostreg_r[0] != (SSP_A<<16)) {
721 EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
722 hostreg_r[0] = SSP_A<<16;
723 }
724}
725
d5276282 726static void tr_ST_to_r0(int op)
d274c33b 727{
728 // VR doesn't need much accuracy here..
729 EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
730 EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
731 hostreg_r[0] = -1;
732}
733
d5276282 734static void tr_STACK_to_r0(int op)
d274c33b 735{
736 // 448
737 EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
738 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
739 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
740 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
741 EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
742 hostreg_r[0] = hostreg_r[1] = -1;
743}
744
d5276282 745static void tr_PC_to_r0(int op)
d274c33b 746{
bad5731d 747 tr_mov16(0, known_regs.gr[SSP_PC].h);
d274c33b 748}
749
d5276282 750static void tr_P_to_r0(int op)
d274c33b 751{
752 tr_flush_dirty_P();
753 EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
754 hostreg_r[0] = -1;
755}
d5276282 756
757static void tr_AL_to_r0(int op)
ede7220f 758{
d5276282 759 if (op == 0x000f) {
760 if (known_regb & KRREG_PMC) {
761 known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
762 } else {
763 EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status
764 EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
765 EOP_STR_IMM(0,7,0x484);
766 }
767 }
768
769 if (hostreg_r[0] != (SSP_AL<<16)) {
770 EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5
771 hostreg_r[0] = SSP_AL<<16;
772 }
ede7220f 773}
ede7220f 774
d5276282 775static void tr_PMX_to_r0(int reg)
ede7220f 776{
ede7220f 777 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
778 {
d5276282 779 known_regs.pmac_read[reg] = known_regs.pmc.v;
ede7220f 780 known_regs.emu_status &= ~SSP_PMC_SET;
0336d643 781 known_regb |= 1 << (20+reg);
d5276282 782 dirty_regb |= 1 << (20+reg);
783 return;
ede7220f 784 }
785
d5276282 786 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
ede7220f 787 {
d5276282 788 u32 pmcv = known_regs.pmac_read[reg];
789 int mode = pmcv>>16;
790 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
791
ede7220f 792 if ((mode & 0xfff0) == 0x0800)
793 {
ede7220f 794 EOP_LDR_IMM(1,7,0x488); // rom_ptr
795 emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
796 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
d5276282 797 known_regs.pmac_read[reg] += 1;
ede7220f 798 }
799 else if ((mode & 0x47ff) == 0x0018) // DRAM
800 {
801 int inc = get_inc(mode);
ede7220f 802 EOP_LDR_IMM(1,7,0x490); // dram_ptr
803 emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
804 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
d5276282 805 if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
ede7220f 806 {
807 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
808 tr_flush_dirty_ST();
809 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
810 EOP_TST_REG_SIMPLE(0,0);
71bb1b7b 811 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024
d5276282 812 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
ede7220f 813 EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
814 }
d5276282 815 known_regs.pmac_read[reg] += inc;
ede7220f 816 }
817 else
818 {
819 tr_unhandled();
820 }
d5276282 821 known_regs.pmc.v = known_regs.pmac_read[reg];
822 //known_regb |= KRREG_PMC;
823 dirty_regb |= KRREG_PMC;
824 dirty_regb |= 1 << (20+reg);
825 hostreg_r[0] = hostreg_r[1] = -1;
826 return;
827 }
ede7220f 828
d5276282 829 known_regb &= ~KRREG_PMC;
830 dirty_regb &= ~KRREG_PMC;
831 known_regb &= ~(1 << (20+reg));
832 dirty_regb &= ~(1 << (20+reg));
833
834 // call the C code to handle this
835 tr_flush_dirty_ST();
836 //tr_flush_dirty_pmcrs();
837 tr_mov16(0, reg);
45883918 838 emit_call(A_COND_AL, ssp_pm_read);
d5276282 839 hostreg_clear();
840}
841
842static void tr_PM0_to_r0(int op)
843{
844 tr_PMX_to_r0(0);
845}
846
847static void tr_PM1_to_r0(int op)
848{
849 tr_PMX_to_r0(1);
850}
851
852static void tr_PM2_to_r0(int op)
853{
854 tr_PMX_to_r0(2);
855}
856
857static void tr_XST_to_r0(int op)
858{
859 EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400
860 EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
861}
862
863static void tr_PM4_to_r0(int op)
864{
865 tr_PMX_to_r0(4);
866}
867
868static void tr_PMC_to_r0(int op)
869{
870 if (known_regb & KRREG_PMC)
871 {
872 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
873 known_regs.emu_status |= SSP_PMC_SET;
874 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
875 // do nothing - this is handled elsewhere
876 } else {
877 tr_mov16(0, known_regs.pmc.l);
878 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
879 }
880 }
881 else
882 {
883 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
884 tr_flush_dirty_ST();
885 if (op != 0x000e)
886 EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
887 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
888 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
889 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
890 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
891 EOP_STR_IMM(1,7,0x484);
892 hostreg_r[0] = hostreg_r[1] = -1;
ede7220f 893 }
ede7220f 894}
895
d274c33b 896
d5276282 897typedef void (tr_read_func)(int op);
d274c33b 898
d5276282 899static tr_read_func *tr_read_funcs[16] =
d274c33b 900{
901 tr_GR0_to_r0,
902 tr_X_to_r0,
903 tr_Y_to_r0,
904 tr_A_to_r0,
905 tr_ST_to_r0,
906 tr_STACK_to_r0,
907 tr_PC_to_r0,
d5276282 908 tr_P_to_r0,
909 tr_PM0_to_r0,
910 tr_PM1_to_r0,
911 tr_PM2_to_r0,
912 tr_XST_to_r0,
913 tr_PM4_to_r0,
914 (tr_read_func *)tr_unhandled,
915 tr_PMC_to_r0,
916 tr_AL_to_r0
d274c33b 917};
918
919
b9c1d012 920// write r0 to general reg handlers. Trashes r1
6e39239f 921#define TR_WRITE_R0_TO_REG(reg) \
922{ \
923 hostreg_sspreg_changed(reg); \
924 hostreg_r[0] = (reg)<<16; \
925 if (const_val != -1) { \
926 known_regs.gr[reg].h = const_val; \
927 known_regb |= 1 << (reg); \
928 } else { \
929 known_regb &= ~(1 << (reg)); \
930 } \
b9c1d012 931}
932
6e39239f 933static void tr_r0_to_GR0(int const_val)
b9c1d012 934{
935 // do nothing
936}
937
6e39239f 938static void tr_r0_to_X(int const_val)
b9c1d012 939{
940 EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
941 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
942 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
6e39239f 943 dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
944 TR_WRITE_R0_TO_REG(SSP_X);
b9c1d012 945}
946
6e39239f 947static void tr_r0_to_Y(int const_val)
b9c1d012 948{
949 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
950 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
951 EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
bad5731d 952 dirty_regb |= KRREG_P;
6e39239f 953 TR_WRITE_R0_TO_REG(SSP_Y);
b9c1d012 954}
955
6e39239f 956static void tr_r0_to_A(int const_val)
b9c1d012 957{
2385f273 958 if (tr_predict_al_need()) {
959 EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
960 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
961 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
962 }
963 else
964 EOP_MOV_REG_LSL(5, 0, 16);
6e39239f 965 TR_WRITE_R0_TO_REG(SSP_A);
b9c1d012 966}
967
6e39239f 968static void tr_r0_to_ST(int const_val)
b9c1d012 969{
970 // VR doesn't need much accuracy here..
971 EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
972 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
973 EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
6e39239f 974 TR_WRITE_R0_TO_REG(SSP_ST);
b9c1d012 975 hostreg_r[1] = -1;
6e39239f 976 dirty_regb &= ~KRREG_ST;
b9c1d012 977}
978
6e39239f 979static void tr_r0_to_STACK(int const_val)
b9c1d012 980{
981 // 448
982 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
983 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
d274c33b 984 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
b9c1d012 985 EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
d274c33b 986 EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
b9c1d012 987 hostreg_r[1] = -1;
988}
989
6e39239f 990static void tr_r0_to_PC(int const_val)
b9c1d012 991{
45883918 992/*
993 * do nothing - dispatcher will take care of this
b9c1d012 994 EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
d274c33b 995 EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
b9c1d012 996 hostreg_r[1] = -1;
45883918 997*/
b9c1d012 998}
999
d5276282 1000static void tr_r0_to_AL(int const_val)
1001{
1002 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16
1003 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
1004 EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16
1005 hostreg_sspreg_changed(SSP_AL);
1006 if (const_val != -1) {
1007 known_regs.gr[SSP_A].l = const_val;
1008 known_regb |= 1 << SSP_AL;
1009 } else
1010 known_regb &= ~(1 << SSP_AL);
1011}
1012
1013static void tr_r0_to_PMX(int reg)
1014{
d5276282 1015 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1016 {
1017 known_regs.pmac_write[reg] = known_regs.pmc.v;
1018 known_regs.emu_status &= ~SSP_PMC_SET;
1019 known_regb |= 1 << (25+reg);
1020 dirty_regb |= 1 << (25+reg);
1021 return;
1022 }
0b5e8296 1023
d5276282 1024 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1025 {
1026 int mode, addr;
1027
1028 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1029
1030 mode = known_regs.pmac_write[reg]>>16;
1031 addr = known_regs.pmac_write[reg]&0xffff;
1032 if ((mode & 0x43ff) == 0x0018) // DRAM
1033 {
1034 int inc = get_inc(mode);
1035 if (mode & 0x0400) tr_unhandled();
1036 EOP_LDR_IMM(1,7,0x490); // dram_ptr
1037 emit_mov_const(A_COND_AL, 2, addr<<1);
1038 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1039 known_regs.pmac_write[reg] += inc;
1040 }
1041 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1042 {
1043 if (mode & 0x0400) tr_unhandled();
1044 EOP_LDR_IMM(1,7,0x490); // dram_ptr
1045 emit_mov_const(A_COND_AL, 2, addr<<1);
1046 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1047 known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1048 }
1049 else if ((mode & 0x47ff) == 0x001c) // IRAM
1050 {
1051 int inc = get_inc(mode);
1052 EOP_LDR_IMM(1,7,0x48c); // iram_ptr
1053 emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
1054 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
e122fae6 1055 EOP_MOV_IMM(1,0,1);
1056 EOP_STR_IMM(1,7,0x494); // iram_dirty
d5276282 1057 known_regs.pmac_write[reg] += inc;
1058 }
1059 else
1060 tr_unhandled();
1061
1062 known_regs.pmc.v = known_regs.pmac_write[reg];
1063 //known_regb |= KRREG_PMC;
1064 dirty_regb |= KRREG_PMC;
1065 dirty_regb |= 1 << (25+reg);
1066 hostreg_r[1] = hostreg_r[2] = -1;
e122fae6 1067 return;
d5276282 1068 }
1069
1070 known_regb &= ~KRREG_PMC;
1071 dirty_regb &= ~KRREG_PMC;
1072 known_regb &= ~(1 << (25+reg));
1073 dirty_regb &= ~(1 << (25+reg));
d5276282 1074
1075 // call the C code to handle this
1076 tr_flush_dirty_ST();
1077 //tr_flush_dirty_pmcrs();
1078 tr_mov16(1, reg);
45883918 1079 emit_call(A_COND_AL, ssp_pm_write);
d5276282 1080 hostreg_clear();
1081}
1082
1083static void tr_r0_to_PM0(int const_val)
1084{
1085 tr_r0_to_PMX(0);
1086}
1087
1088static void tr_r0_to_PM1(int const_val)
1089{
1090 tr_r0_to_PMX(1);
1091}
1092
1093static void tr_r0_to_PM2(int const_val)
1094{
1095 tr_r0_to_PMX(2);
1096}
1097
1098static void tr_r0_to_PM4(int const_val)
1099{
1100 tr_r0_to_PMX(4);
1101}
1102
1103static void tr_r0_to_PMC(int const_val)
1104{
1105 if ((known_regb & KRREG_PMC) && const_val != -1)
1106 {
1107 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1108 known_regs.emu_status |= SSP_PMC_SET;
1109 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1110 known_regs.pmc.h = const_val;
1111 } else {
1112 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1113 known_regs.pmc.l = const_val;
1114 }
1115 }
1116 else
1117 {
1118 tr_flush_dirty_ST();
1119 if (known_regb & KRREG_PMC) {
1120 emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
1121 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1122 known_regb &= ~KRREG_PMC;
1123 dirty_regb &= ~KRREG_PMC;
1124 }
1125 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
1126 EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400
1127 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1128 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC]
1129 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1130 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1131 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1132 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
1133 EOP_STR_IMM(1,7,0x484);
1134 hostreg_r[1] = hostreg_r[2] = -1;
1135 }
1136}
1137
6e39239f 1138typedef void (tr_write_func)(int const_val);
b9c1d012 1139
d5276282 1140static tr_write_func *tr_write_funcs[16] =
b9c1d012 1141{
1142 tr_r0_to_GR0,
1143 tr_r0_to_X,
1144 tr_r0_to_Y,
1145 tr_r0_to_A,
1146 tr_r0_to_ST,
1147 tr_r0_to_STACK,
1148 tr_r0_to_PC,
d5276282 1149 (tr_write_func *)tr_unhandled,
1150 tr_r0_to_PM0,
1151 tr_r0_to_PM1,
1152 tr_r0_to_PM2,
1153 (tr_write_func *)tr_unhandled,
1154 tr_r0_to_PM4,
1155 (tr_write_func *)tr_unhandled,
1156 tr_r0_to_PMC,
1157 tr_r0_to_AL
b9c1d012 1158};
1159
0e4d7ba5 1160static void tr_mac_load_XY(int op)
1161{
1162 tr_rX_read(op&3, (op>>2)&3); // X
1163 EOP_MOV_REG_LSL(4, 0, 16);
1164 tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1165 EOP_ORR_REG_SIMPLE(4, 0);
1166 dirty_regb |= KRREG_P;
1167 hostreg_sspreg_changed(SSP_X);
1168 hostreg_sspreg_changed(SSP_Y);
1169 known_regb &= ~KRREG_X;
1170 known_regb &= ~KRREG_Y;
1171}
1172
ede7220f 1173// -----------------------------------------------------
1174
ede7220f 1175static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
0e4d7ba5 1176{
ede7220f 1177 u32 pmcv, tmpv;
1178 if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1179
1180 // programming PMC:
1181 // ldi PMC, imm1
1182 // ldi PMC, imm2
1183 (*pc)++;
1184 pmcv = imm | (PROGRAM((*pc)++) << 16);
d5276282 1185 known_regs.pmc.v = pmcv;
ede7220f 1186 known_regb |= KRREG_PMC;
d5276282 1187 dirty_regb |= KRREG_PMC;
ede7220f 1188 known_regs.emu_status |= SSP_PMC_SET;
71bb1b7b 1189 n_in_ops++;
ede7220f 1190
1191 // check for possible reg programming
1192 tmpv = PROGRAM(*pc);
1193 if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1194 {
1195 int is_write = (tmpv & 0xff8f) == 0x80;
1196 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1197 if (reg > 4) tr_unhandled();
d5276282 1198 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
ede7220f 1199 known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
1200 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
d5276282 1201 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
ede7220f 1202 known_regs.emu_status &= ~SSP_PMC_SET;
1203 (*pc)++;
71bb1b7b 1204 n_in_ops++;
ede7220f 1205 return 5;
0e4d7ba5 1206 }
1207
d5276282 1208 tr_unhandled();
ede7220f 1209 return 4;
1210}
1211
1212static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1213
1214static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1215{
1216 // ldi ST, 0
1217 // ldi PM0, 0
1218 // ldi PM0, 0
1219 // ldi ST, 60h
1220 unsigned short *pp;
1221 if (op != 0x0840 || imm != 0) return 0;
1222 pp = PROGRAM_P(*pc);
1223 if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1224
1225 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
1226 EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
1227 hostreg_sspreg_changed(SSP_ST);
1228 known_regs.gr[SSP_ST].h = 0x60;
1229 known_regb |= 1 << SSP_ST;
1230 dirty_regb &= ~KRREG_ST;
1231 (*pc) += 3*2;
71bb1b7b 1232 n_in_ops += 3;
ede7220f 1233 return 4*2;
0e4d7ba5 1234}
5d817c91 1235
d5276282 1236static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1237{
1238 // @ 3DA2 and 426A
1239 // ld PMC, (r3|00)
1240 // ld (r3|00), PMC
1241 // ld -, AL
1242 if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1243
1244 tr_bank_read(0);
1245 EOP_MOV_REG_LSL(0, 0, 4);
1246 EOP_ORR_REG_LSR(0, 0, 0, 16);
1247 tr_bank_write(0);
1248 (*pc) += 2;
71bb1b7b 1249 n_in_ops += 2;
d5276282 1250 return 3;
1251}
1252
ede7220f 1253// -----------------------------------------------------
1254
45883918 1255static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
5d817c91 1256{
0e4d7ba5 1257 u32 tmpv, tmpv2, tmpv3;
5d817c91 1258 int ret = 0;
bad5731d 1259 known_regs.gr[SSP_PC].h = *pc;
5d817c91 1260
e807ac75 1261 switch (op >> 9)
1262 {
1263 // ld d, s
f48f5e3b 1264 case 0x00:
5d817c91 1265 if (op == 0) { ret++; break; } // nop
d274c33b 1266 tmpv = op & 0xf; // src
1267 tmpv2 = (op >> 4) & 0xf; // dst
d274c33b 1268 if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1269 tr_flush_dirty_P();
1270 EOP_MOV_REG_SIMPLE(5, 10);
d5276282 1271 hostreg_sspreg_changed(SSP_A);
bad5731d 1272 known_regb &= ~(KRREG_A|KRREG_AL);
d274c33b 1273 ret++; break;
1274 }
d5276282 1275 tr_read_funcs[tmpv](op);
6e39239f 1276 tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
45883918 1277 if (tmpv2 == SSP_PC) {
1278 ret |= 0x10000;
1279 *end_cond = -A_COND_AL;
1280 }
bad5731d 1281 ret++; break;
1282
1283 // ld d, (ri)
89fea1e9 1284 case 0x01: {
89fea1e9 1285 int r = (op&3) | ((op>>6)&4);
1286 int mod = (op>>2)&3;
1287 tmpv = (op >> 4) & 0xf; // dst
d5276282 1288 ret = tr_detect_rotate(op, pc, imm);
1289 if (ret > 0) break;
89fea1e9 1290 if (tmpv != 0)
2385f273 1291 tr_rX_read(r, mod);
1292 else {
1293 int cnt = 1;
1294 while (PROGRAM(*pc) == op) {
1295 (*pc)++; cnt++; ret++;
1296 n_in_ops++;
1297 }
1298 tr_ptrr_mod(r, mod, 1, cnt); // skip
1299 }
6e39239f 1300 tr_write_funcs[tmpv](-1);
45883918 1301 if (tmpv == SSP_PC) {
1302 ret |= 0x10000;
1303 *end_cond = -A_COND_AL;
1304 }
89fea1e9 1305 ret++; break;
1306 }
bad5731d 1307
1308 // ld (ri), s
1309 case 0x02:
1310 tmpv = (op >> 4) & 0xf; // src
d5276282 1311 tr_read_funcs[tmpv](op);
0e4d7ba5 1312 tr_rX_write(op);
d274c33b 1313 ret++; break;
f48f5e3b 1314
1315 // ld a, adr
1316 case 0x03:
5d817c91 1317 tr_bank_read(op&0x1ff);
6e39239f 1318 tr_r0_to_A(-1);
5d817c91 1319 ret++; break;
1320
b9c1d012 1321 // ldi d, imm
1322 case 0x04:
ede7220f 1323 tmpv = (op & 0xf0) >> 4; // dst
1324 ret = tr_detect_pm0_block(op, pc, imm);
1325 if (ret > 0) break;
ede7220f 1326 ret = tr_detect_set_pm(op, pc, imm);
1327 if (ret > 0) break;
0b5e8296 1328 tr_mov16(0, imm);
1329 tr_write_funcs[tmpv](imm);
45883918 1330 if (tmpv == SSP_PC) {
1331 ret |= 0x10000;
1332 *jump_pc = imm;
1333 }
0b5e8296 1334 ret += 2; break;
b9c1d012 1335
bad5731d 1336 // ld d, ((ri))
0e4d7ba5 1337 case 0x05:
bad5731d 1338 tmpv2 = (op >> 4) & 0xf; // dst
0e4d7ba5 1339 tr_rX_read2(op);
6e39239f 1340 tr_write_funcs[tmpv2](-1);
45883918 1341 if (tmpv2 == SSP_PC) {
1342 ret |= 0x10000;
1343 *end_cond = -A_COND_AL;
1344 }
0e4d7ba5 1345 ret += 3; break;
b9c1d012 1346
5d817c91 1347 // ldi (ri), imm
1348 case 0x06:
5d817c91 1349 tr_mov16(0, imm);
0e4d7ba5 1350 tr_rX_write(op);
a6fb500b 1351 ret += 2; break;
f48f5e3b 1352
1353 // ld adr, a
1354 case 0x07:
d5276282 1355 tr_A_to_r0(op);
5d817c91 1356 tr_bank_write(op&0x1ff);
1357 ret++; break;
1358
d274c33b 1359 // ld d, ri
1360 case 0x09: {
bad5731d 1361 int r;
d274c33b 1362 r = (op&3) | ((op>>6)&4); // src
bad5731d 1363 tmpv2 = (op >> 4) & 0xf; // dst
bad5731d 1364 if ((r&3) == 3) tr_unhandled();
d274c33b 1365
bad5731d 1366 if (known_regb & (1 << (r+8))) {
1367 tr_mov16(0, known_regs.r[r]);
6e39239f 1368 tr_write_funcs[tmpv2](known_regs.r[r]);
d274c33b 1369 } else {
bad5731d 1370 int reg = (r < 4) ? 8 : 9;
d274c33b 1371 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1372 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1373 hostreg_r[0] = -1;
6e39239f 1374 tr_write_funcs[tmpv2](-1);
d274c33b 1375 }
d274c33b 1376 ret++; break;
1377 }
1378
bad5731d 1379 // ld ri, s
1380 case 0x0a: {
1381 int r;
1382 r = (op&3) | ((op>>6)&4); // dst
1383 tmpv = (op >> 4) & 0xf; // src
bad5731d 1384 if ((r&3) == 3) tr_unhandled();
1385
1386 if (known_regb & (1 << tmpv)) {
1387 known_regs.r[r] = known_regs.gr[tmpv].h;
1388 known_regb |= 1 << (r + 8);
1389 dirty_regb |= 1 << (r + 8);
1390 } else {
1391 int reg = (r < 4) ? 8 : 9;
1392 int ror = ((4 - (r&3))*8) & 0x1f;
d5276282 1393 tr_read_funcs[tmpv](op);
bad5731d 1394 EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask>
1395 EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff
1396 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl
1397 hostreg_r[0] = -1;
1398 known_regb &= ~(1 << (r+8));
1399 dirty_regb &= ~(1 << (r+8));
1400 }
1401 ret++; break;
1402 }
1403
5d817c91 1404 // ldi ri, simm
67c81ee2 1405 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
5d817c91 1406 tmpv = (op>>8)&7;
bad5731d 1407 known_regs.r[tmpv] = op;
1408 known_regb |= 1 << (tmpv + 8);
5d817c91 1409 dirty_regb |= 1 << (tmpv + 8);
1410 ret++; break;
bad5731d 1411
a6fb500b 1412 // call cond, addr
6e39239f 1413 case 0x24: {
1414 u32 *jump_op = NULL;
a6fb500b 1415 tmpv = tr_cond_check(op);
6e39239f 1416 if (tmpv != A_COND_AL) {
1417 jump_op = tcache_ptr;
1418 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1419 }
1420 tr_mov16(0, *pc);
1421 tr_r0_to_STACK(*pc);
1422 if (tmpv != A_COND_AL) {
1423 u32 *real_ptr = tcache_ptr;
1424 tcache_ptr = jump_op;
1425 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1426 tcache_ptr = real_ptr;
1427 }
a6fb500b 1428 tr_mov16_cond(tmpv, 0, imm);
45883918 1429 if (tmpv != A_COND_AL)
a6fb500b 1430 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
6e39239f 1431 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ede7220f 1432 ret |= 0x10000;
45883918 1433 *end_cond = tmpv;
1434 *jump_pc = imm;
a6fb500b 1435 ret += 2; break;
6e39239f 1436 }
a6fb500b 1437
bad5731d 1438 // ld d, (a)
1439 case 0x25:
bad5731d 1440 tmpv2 = (op >> 4) & 0xf; // dst
d5276282 1441 tr_A_to_r0(op);
bad5731d 1442 EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
1443 EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
1444 EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
1445 hostreg_r[0] = hostreg_r[1] = -1;
6e39239f 1446 tr_write_funcs[tmpv2](-1);
45883918 1447 if (tmpv2 == SSP_PC) {
1448 ret |= 0x10000;
1449 *end_cond = -A_COND_AL;
1450 }
a6fb500b 1451 ret += 3; break;
bad5731d 1452
1453 // bra cond, addr
a6fb500b 1454 case 0x26:
bad5731d 1455 tmpv = tr_cond_check(op);
1456 tr_mov16_cond(tmpv, 0, imm);
45883918 1457 if (tmpv != A_COND_AL)
bad5731d 1458 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
6e39239f 1459 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ede7220f 1460 ret |= 0x10000;
45883918 1461 *end_cond = tmpv;
1462 *jump_pc = imm;
a6fb500b 1463 ret += 2; break;
bad5731d 1464
89fea1e9 1465 // mod cond, op
89fea1e9 1466 case 0x48: {
1467 // check for repeats of this op
1468 tmpv = 1; // count
1469 while (PROGRAM(*pc) == op && (op & 7) != 6) {
1470 (*pc)++; tmpv++;
71bb1b7b 1471 n_in_ops++;
89fea1e9 1472 }
6e39239f 1473 if ((op&0xf0) != 0) // !always
1474 tr_make_dirty_ST();
1475
89fea1e9 1476 tmpv2 = tr_cond_check(op);
1477 switch (op & 7) {
1478 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1479 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1480 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
6e39239f 1481 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
1482 EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
89fea1e9 1483 hostreg_r[1] = -1; break; // abs
1484 default: tr_unhandled();
1485 }
6e39239f 1486
1487 hostreg_sspreg_changed(SSP_A);
1488 dirty_regb |= KRREG_ST;
1489 known_regb &= ~KRREG_ST;
1490 known_regb &= ~(KRREG_A|KRREG_AL);
89fea1e9 1491 ret += tmpv; break;
1492 }
0e4d7ba5 1493
bad5731d 1494 // mpys?
1495 case 0x1b:
0e4d7ba5 1496 tr_flush_dirty_P();
1497 tr_mac_load_XY(op);
1498 tr_make_dirty_ST();
1499 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1500 hostreg_sspreg_changed(SSP_A);
1501 known_regb &= ~(KRREG_A|KRREG_AL);
1502 dirty_regb |= KRREG_ST;
1503 ret++; break;
bad5731d 1504
1505 // mpya (rj), (ri), b
1506 case 0x4b:
0e4d7ba5 1507 tr_flush_dirty_P();
1508 tr_mac_load_XY(op);
1509 tr_make_dirty_ST();
1510 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1511 hostreg_sspreg_changed(SSP_A);
1512 known_regb &= ~(KRREG_A|KRREG_AL);
1513 dirty_regb |= KRREG_ST;
1514 ret++; break;
bad5731d 1515
1516 // mld (rj), (ri), b
1517 case 0x5b:
0e4d7ba5 1518 EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1519 hostreg_sspreg_changed(SSP_A);
1520 known_regs.gr[SSP_A].v = 0;
bad5731d 1521 known_regb |= (KRREG_A|KRREG_AL);
0e4d7ba5 1522 dirty_regb |= KRREG_ST;
1523 tr_mac_load_XY(op);
1524 ret++; break;
1525
1526 // OP a, s
1527 case 0x10:
1528 case 0x30:
1529 case 0x40:
1530 case 0x50:
1531 case 0x60:
1532 case 0x70:
1533 tmpv = op & 0xf; // src
1534 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1535 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
0e4d7ba5 1536 if (tmpv == SSP_P) {
1537 tr_flush_dirty_P();
1538 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1539 } else if (tmpv == SSP_A) {
1540 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1541 } else {
d5276282 1542 tr_read_funcs[tmpv](op);
0e4d7ba5 1543 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1544 }
1545 hostreg_sspreg_changed(SSP_A);
1546 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1547 dirty_regb |= KRREG_ST;
1548 ret++; break;
1549
1550 // OP a, (ri)
1551 case 0x11:
1552 case 0x31:
1553 case 0x41:
1554 case 0x51:
1555 case 0x61:
1556 case 0x71:
1557 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1558 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1559 tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1560 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1561 hostreg_sspreg_changed(SSP_A);
1562 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1563 dirty_regb |= KRREG_ST;
1564 ret++; break;
1565
1566 // OP a, adr
1567 case 0x13:
1568 case 0x33:
1569 case 0x43:
1570 case 0x53:
1571 case 0x63:
1572 case 0x73:
1573 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1574 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1575 tr_bank_read(op&0x1ff);
1576 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1577 hostreg_sspreg_changed(SSP_A);
1578 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1579 dirty_regb |= KRREG_ST;
1580 ret++; break;
1581
1582 // OP a, imm
1583 case 0x14:
1584 case 0x34:
1585 case 0x44:
1586 case 0x54:
1587 case 0x64:
1588 case 0x74:
1589 tmpv = (op & 0xf0) >> 4;
1590 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1591 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1592 tr_mov16(0, imm);
1593 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1594 hostreg_sspreg_changed(SSP_A);
1595 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1596 dirty_regb |= KRREG_ST;
1597 ret += 2; break;
1598
1599 // OP a, ((ri))
1600 case 0x15:
1601 case 0x35:
1602 case 0x45:
1603 case 0x55:
1604 case 0x65:
1605 case 0x75:
1606 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1607 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1608 tr_rX_read2(op);
1609 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1610 hostreg_sspreg_changed(SSP_A);
1611 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1612 dirty_regb |= KRREG_ST;
1613 ret += 3; break;
1614
1615 // OP a, ri
1616 case 0x19:
1617 case 0x39:
1618 case 0x49:
1619 case 0x59:
1620 case 0x69:
1621 case 0x79: {
1622 int r;
1623 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1624 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1625 r = (op&3) | ((op>>6)&4); // src
1626 if ((r&3) == 3) tr_unhandled();
1627
1628 if (known_regb & (1 << (r+8))) {
1629 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
1630 } else {
1631 int reg = (r < 4) ? 8 : 9;
1632 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1633 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1634 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1635 hostreg_r[0] = -1;
1636 }
1637 hostreg_sspreg_changed(SSP_A);
1638 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1639 dirty_regb |= KRREG_ST;
1640 ret++; break;
1641 }
1642
1643 // OP simm
1644 case 0x1c:
1645 case 0x3c:
1646 case 0x4c:
1647 case 0x5c:
1648 case 0x6c:
1649 case 0x7c:
1650 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1651 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1652 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
1653 hostreg_sspreg_changed(SSP_A);
1654 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1655 dirty_regb |= KRREG_ST;
bad5731d 1656 ret++; break;
e807ac75 1657 }
1658
71bb1b7b 1659 n_in_ops++;
1660
5d817c91 1661 return ret;
e807ac75 1662}
1663
45883918 1664static void emit_block_prologue(void)
1665{
1666 // check if there are enough cycles..
1667 // note: r0 must contain PC of current block
1668 EOP_CMP_IMM(11,0,0); // cmp r11, #0
f8af9634 1669 emit_jump(A_COND_LE, ssp_drc_end);
45883918 1670}
1671
1672/* cond:
1673 * >0: direct (un)conditional jump
1674 * <0: indirect jump
1675 */
1676static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
1677{
2d2247c2 1678 if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; }
45883918 1679 EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles
1680
1681 if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1682 // indirect jump, or rom -> iram jump, must use dispatcher
1683 emit_jump(A_COND_AL, ssp_drc_next);
1684 }
1685 else if (cond == A_COND_AL) {
679af8a3 1686 u32 *target = (pc < 0x400) ?
1687 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
1688 ssp_block_table[pc];
45883918 1689 if (target != NULL)
1690 emit_jump(A_COND_AL, target);
1691 else {
f8af9634 1692 int ops = emit_jump(A_COND_AL, ssp_drc_next);
1693 // cause the next block to be emitted over jump instruction
1694 tcache_ptr -= ops;
45883918 1695 }
1696 }
1697 else {
679af8a3 1698 u32 *target1 = (pc < 0x400) ?
1699 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
1700 ssp_block_table[pc];
1701 u32 *target2 = (end_pc < 0x400) ?
1702 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + end_pc] :
1703 ssp_block_table[end_pc];
45883918 1704 if (target1 != NULL)
1705 emit_jump(cond, target1);
45883918 1706 if (target2 != NULL)
1707 emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
f8af9634 1708#ifndef __EPOC32__
1709 // emit patchable branches
1710 if (target1 == NULL)
1711 emit_call(cond, ssp_drc_next_patch);
1712 if (target2 == NULL)
1713 emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
1714#else
1715 // won't patch indirect jumps
1716 if (target1 == NULL || target2 == NULL)
1717 emit_jump(A_COND_AL, ssp_drc_next);
1718#endif
45883918 1719 }
1720}
1721
71bb1b7b 1722void *ssp_translate_block(int pc)
726bbb3e 1723{
e807ac75 1724 unsigned int op, op1, imm, ccount = 0;
5c129565 1725 unsigned int *block_start;
45883918 1726 int ret, end_cond = A_COND_AL, jump_pc = -1;
5c129565 1727
2d2247c2 1728 //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
f8af9634 1729
5c129565 1730 block_start = tcache_ptr;
bad5731d 1731 known_regb = 0;
1732 dirty_regb = KRREG_P;
d5276282 1733 known_regs.emu_status = 0;
5d817c91 1734 hostreg_clear();
5c129565 1735
1736 emit_block_prologue();
726bbb3e 1737
e807ac75 1738 for (; ccount < 100;)
726bbb3e 1739 {
1740 op = PROGRAM(pc++);
1741 op1 = op >> 9;
e807ac75 1742 imm = (u32)-1;
5c129565 1743
e807ac75 1744 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1745 imm = PROGRAM(pc++); // immediate
5c129565 1746
45883918 1747 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
e807ac75 1748 if (ret <= 0)
1749 {
2d2247c2 1750 elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
1751 //exit(1);
892b1dd2 1752 }
ede7220f 1753
45883918 1754 ccount += ret & 0xffff;
1755 if (ret & 0x10000) break;
726bbb3e 1756 }
5c129565 1757
45883918 1758 if (ccount >= 100) {
1759 end_cond = A_COND_AL;
1760 jump_pc = pc;
1761 emit_mov_const(A_COND_AL, 0, pc);
1762 }
0b5e8296 1763
89fea1e9 1764 tr_flush_dirty_prs();
1765 tr_flush_dirty_ST();
ede7220f 1766 tr_flush_dirty_pmcrs();
45883918 1767 emit_block_epilogue(ccount, end_cond, jump_pc, pc);
726bbb3e 1768
679af8a3 1769 if (tcache_ptr - tcache > DRC_TCACHE_SIZE/4) {
f8af9634 1770 elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n");
726bbb3e 1771 fflush(stdout);
1772 exit(1);
1773 }
1774
1775 // stats
1776 nblocks++;
2d2247c2 1777 //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1778 // (double)(tcache_ptr - tcache) / (double)n_in_ops);
df143b36 1779
5d817c91 1780#ifdef DUMP_BLOCK
5c129565 1781 {
1782 FILE *f = fopen("tcache.bin", "wb");
1783 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1784 fclose(f);
1785 }
43e6eaad 1786 printf("dumped tcache.bin\n");
5c129565 1787 exit(0);
1788#endif
259ed0ea 1789
1790 handle_caches();
1791
5c129565 1792 return block_start;
726bbb3e 1793}
1794
1795
1796
1797// -----------------------------------------------------
1798
fad24893 1799static void ssp1601_state_load(void)
1800{
1801 ssp->drc.iram_dirty = 1;
1802 ssp->drc.iram_context = 0;
1803}
1804
679af8a3 1805void ssp1601_dyn_exit(void)
1806{
1807 free(ssp_block_table);
1808 free(ssp_block_table_iram);
1809 ssp_block_table = ssp_block_table_iram = NULL;
1810
1811 drc_cmn_cleanup();
1812}
1813
e807ac75 1814int ssp1601_dyn_startup(void)
726bbb3e 1815{
41397701 1816 drc_cmn_init();
1817
679af8a3 1818 ssp_block_table = calloc(sizeof(ssp_block_table[0]), SSP_BLOCKTAB_ENTS);
1819 if (ssp_block_table == NULL)
1820 return -1;
1821 ssp_block_table_iram = calloc(sizeof(ssp_block_table_iram[0]), SSP_BLOCKTAB_IRAM_ENTS);
1822 if (ssp_block_table_iram == NULL) {
1823 free(ssp_block_table);
1824 return -1;
1825 }
1826
1827 memset(tcache, 0, DRC_TCACHE_SIZE);
e807ac75 1828 tcache_ptr = tcache;
726bbb3e 1829
fad24893 1830 PicoLoadStateHook = ssp1601_state_load;
1831
f5d1115f 1832 n_in_ops = 0;
d5276282 1833#ifdef ARM
1834 // hle'd blocks
1ca2ea4f 1835 ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1836 ssp_block_table[0x902/2] = (void *) ssp_hle_902;
679af8a3 1837 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ENTS + 0x030/2] = (void *) ssp_hle_07_030;
1838 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ENTS + 0x036/2] = (void *) ssp_hle_07_036;
1839 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ENTS + 0x6d6/2] = (void *) ssp_hle_07_6d6;
1840 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ENTS + 0x12c/2] = (void *) ssp_hle_11_12c;
1841 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ENTS + 0x384/2] = (void *) ssp_hle_11_384;
1842 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ENTS + 0x38a/2] = (void *) ssp_hle_11_38a;
d5276282 1843#endif
1844
726bbb3e 1845 return 0;
1846}
1847
1848
1849void ssp1601_dyn_reset(ssp1601_t *ssp)
1850{
71bb1b7b 1851 ssp1601_reset(ssp);
1852 ssp->drc.iram_dirty = 1;
1853 ssp->drc.iram_context = 0;
1854 // must do this here because ssp is not available @ startup()
1855 ssp->drc.ptr_rom = (u32) Pico.rom;
1856 ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1857 ssp->drc.ptr_dram = (u32) svp->dram;
1ca2ea4f 1858 ssp->drc.ptr_btable = (u32) ssp_block_table;
1859 ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
45883918 1860
1861 // prevent new versions of IRAM from appearing
1862 memset(svp->iram_rom, 0, 0x800);
726bbb3e 1863}
1864
f8af9634 1865
726bbb3e 1866void ssp1601_dyn_run(int cycles)
1867{
b9c1d012 1868 if (ssp->emu_status & SSP_WAIT_MASK) return;
b9c1d012 1869
fad24893 1870#ifdef DUMP_BLOCK
1871 ssp_translate_block(DUMP_BLOCK >> 1);
1872#endif
1873#ifdef ARM
71bb1b7b 1874 ssp_drc_entry(cycles);
fad24893 1875#endif
726bbb3e 1876}
1877
fast MegaDrive/MegaCD/32X emulator