[picodrive.git] / pico / memory_arm.S

/*\r
 * PicoDrive\r
 * (C) notaz, 2006-2009\r
 *\r
 * This work is licensed under the terms of MAME license.\r
 * See COPYING file in the top-level directory.\r
 */\r
\r
#include "pico_int_o32.h"\r
\r
.equ SRR_MAPPED,    (1 <<  0)\r
.equ SRR_READONLY,  (1 <<  1)\r
.equ SRF_EEPROM,    (1 <<  1)\r
.equ POPT_EN_32X,   (1 << 20)\r
\r
.text\r
.align 4\r
\r
.global PicoRead8_sram\r
.global PicoRead8_io\r
.global PicoRead16_sram\r
.global PicoRead16_io\r
.global PicoWrite8_io\r
.global PicoWrite16_io\r
\r
PicoRead8_sram: @ u32 a\r
    ldr     r3, =Pico\r
    ldr     r1, [r3, #OFS_Pico_sv_end]\r
    cmp     r0, r1\r
    bgt     m_read8_nosram\r
    ldr     r2, [r3, #OFS_Pico_sv_start]\r
    cmp     r0, r2\r
    blt     m_read8_nosram\r
    ldrb    r1, [r3, #OFS_Pico_m_sram_reg]\r
    tst     r1, #SRR_MAPPED\r
    beq     m_read8_nosram\r
    ldr     r1, [r3, #OFS_Pico_sv_flags]\r
    tst     r1, #SRF_EEPROM\r
    bne     m_read8_eeprom\r
    ldr     r1, [r3, #OFS_Pico_sv_data]\r
    sub     r0, r0, r2\r
    ldrb    r0, [r0, r1]\r
    bx      lr\r
\r
m_read8_nosram:\r
    ldr     r1, [r3, #OFS_Pico_romsize]\r
    cmp     r0, r1\r
    movgt   r0, #0\r
    bxgt    lr              @ bad location\r
    @ XXX: banking unfriendly\r
    ldr     r1, [r3, #OFS_Pico_rom]\r
    eor     r0, r0, #1\r
    ldrb    r0, [r1, r0]\r
    bx      lr\r
\r
m_read8_eeprom:\r
    stmfd   sp!,{r0,lr}\r
    bl      EEPROM_read\r
    ldmfd   sp!,{r1,lr}\r
    tst     r1, #1\r
    moveq   r0, r0, lsr #8\r
    bx      lr\r
\r
\r
PicoRead8_io: @ u32 a\r
    bic     r2, r0, #0x001f   @ most commonly we get i/o port read,\r
    cmp     r2, #0xa10000     @ so check for it first\r
    beq     io_ports_read\r
\r
m_read8_not_io:\r
    and     r2, r0, #0xfc00\r
    cmp     r2, #0x1000\r
    bne     PicoRead8_32x\r
\r
    ldr     r3, =Pico\r
    mov     r1, r0\r
    ldr     r0, [r3, #OFS_Pico_m_rotate]\r
    add     r0, r0, #1\r
    strb    r0, [r3, #OFS_Pico_m_rotate]\r
    eor     r0, r0, r0, lsl #6\r
\r
    tst     r1, #1\r
    bxne    lr                @ odd addr -> open bus\r
    bic     r0, r0, #1        @ bit0 defined in this area\r
    and     r2, r1, #0xff00\r
    cmp     r2, #0x1100\r
    bxne    lr                @ not busreq\r
\r
    ldrb    r1, [r3, #OFS_Pico_m_z80Run]\r
    ldrb    r2, [r3, #OFS_Pico_m_z80_reset]\r
    orr     r0, r0, r1\r
    orr     r0, r0, r2\r
    bx      lr\r
\r
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
\r
PicoRead16_sram: @ u32 a, u32 d\r
    ldr     r3, =Pico\r
    ldr     r1, [r3, #OFS_Pico_sv_end]\r
    cmp     r0, r1\r
    bgt     m_read16_nosram\r
    ldr     r2, [r3, #OFS_Pico_sv_start]\r
    cmp     r0, r2\r
    blt     m_read16_nosram\r
    ldrb    r1, [r3, #OFS_Pico_m_sram_reg]\r
    tst     r1, #SRR_MAPPED\r
    beq     m_read16_nosram\r
    ldr     r1, [r3, #OFS_Pico_sv_flags]\r
    tst     r1, #SRF_EEPROM\r
    bne     EEPROM_read\r
    ldr     r1, [r3, #OFS_Pico_sv_data]\r
    sub     r0, r0, r2\r
    ldrb    r1, [r0, r1]!\r
    ldrb    r0, [r0, #1]\r
    orr     r0, r0, r1, lsl #8\r
    bx      lr\r
\r
m_read16_nosram:\r
    ldr     r1, [r3, #OFS_Pico_romsize]\r
    cmp     r0, r1\r
    movgt   r0, #0\r
    bxgt    lr              @ bad location\r
    @ XXX: banking unfriendly\r
    ldr     r1, [r3, #OFS_Pico_rom]\r
    ldrh    r0, [r1, r0]\r
    bx      lr\r
\r
\r
PicoRead16_io: @ u32 a, u32 d\r
    bic     r2, r0, #0x001f   @ most commonly we get i/o port read,\r
    cmp     r2, #0xa10000     @ so check for it first\r
    bne     m_read16_not_io\r
    stmfd   sp!,{lr}\r
    bl      io_ports_read     @ same as read8\r
    orr     r0, r0, r0, lsl #8 @ only has bytes mirrored\r
    ldmfd   sp!,{pc}\r
\r
m_read16_not_io:\r
    and     r2, r0, #0xfc00\r
    cmp     r2, #0x1000\r
    bne     PicoRead16_32x\r
\r
    ldr     r3, =Pico\r
    and     r2, r0, #0xff00\r
    ldr     r0, [r3, #OFS_Pico_m_rotate]\r
    add     r0, r0, #1\r
    strb    r0, [r3, #OFS_Pico_m_rotate]\r
    eor     r0, r0, r0, lsl #5\r
    eor     r0, r0, r0, lsl #8\r
    bic     r0, r0, #0x100    @ bit8 defined in this area\r
    cmp     r2, #0x1100\r
    bxne    lr                @ not busreq\r
\r
    ldrb    r1, [r3, #OFS_Pico_m_z80Run]\r
    ldrb    r2, [r3, #OFS_Pico_m_z80_reset]\r
    orr     r0, r0, r1, lsl #8\r
    orr     r0, r0, r2, lsl #8\r
    bx      lr\r
\r
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
\r
PicoWrite8_io: @ u32 a, u32 d\r
    bic     r2, r0, #0x1e       @ most commonly we get i/o port write,\r
    eor     r2, r2, #0xa10000   @ so check for it first\r
    eors    r2, r2, #1\r
    beq     io_ports_write\r
\r
m_write8_not_io:\r
    tst     r0, #1\r
    bne     m_write8_not_z80ctl @ even addrs only\r
    and     r2, r0, #0xff00\r
    cmp     r2, #0x1100\r
    moveq   r0, r1\r
    beq     ctl_write_z80busreq\r
    cmp     r2, #0x1200\r
    moveq   r0, r1\r
    beq     ctl_write_z80reset\r
\r
m_write8_not_z80ctl:\r
    @ unlikely\r
    eor     r2, r0, #0xa10000\r
    eor     r2, r2, #0x003000\r
    eors    r2, r2, #0x0000f1\r
    bne     PicoWrite8_32x\r
    ldr     r3, =Pico\r
    ldrb    r2, [r3, #OFS_Pico_m_sram_reg]\r
    and     r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
    bic     r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
    orr     r2, r2, r1\r
    strb    r2, [r3, #OFS_Pico_m_sram_reg]\r
    bx      lr\r
\r
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
\r
PicoWrite16_io: @ u32 a, u32 d\r
    bic     r2, r0, #0x1f    @ most commonly we get i/o port write,\r
    cmp     r2, #0xa10000    @ so check for it first\r
    beq     io_ports_write\r
\r
m_write16_not_io:\r
    and     r2, r0, #0xff00\r
    cmp     r2, #0x1100\r
    moveq   r0, r1, lsr #8\r
    beq     ctl_write_z80busreq\r
    cmp     r2, #0x1200\r
    moveq   r0, r1, lsr #8\r
    beq     ctl_write_z80reset\r
\r
m_write16_not_z80ctl:\r
    @ unlikely\r
    eor     r2, r0, #0xa10000\r
    eor     r2, r2, #0x003000\r
    eors    r2, r2, #0x0000f0\r
    bne     PicoWrite16_32x\r
    ldr     r3, =Pico\r
    ldrb    r2, [r3, #OFS_Pico_m_sram_reg]\r
    and     r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
    bic     r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
    orr     r2, r2, r1\r
    strb    r2, [r3, #OFS_Pico_m_sram_reg]\r
    bx      lr\r
\r
.pool\r
\r
@ vim:filetype=armasm\r
Commit	Line	Data
cff531af	1	/*\r
	2	* PicoDrive\r
	3	* (C) notaz, 2006-2009\r
	4	*\r
	5	* This work is licensed under the terms of MAME license.\r
	6	* See COPYING file in the top-level directory.\r
	7	*/\r
cc68a136	8	\r
88fd63ad	9	#include "pico_int_o32.h"\r
88fd63ad	10	\r
0ace9b9a	11	.equ SRR_MAPPED, (1 << 0)\r
	12	.equ SRR_READONLY, (1 << 1)\r
	13	.equ SRF_EEPROM, (1 << 1)\r
db1d3564	14	.equ POPT_EN_32X, (1 << 20)\r
cc68a136	15	\r
cc68a136	16	.text\r
3ec29f01	17	.align 4\r
cc68a136	18	\r
0ace9b9a	19	.global PicoRead8_sram\r
	20	.global PicoRead8_io\r
	21	.global PicoRead16_sram\r
	22	.global PicoRead16_io\r
	23	.global PicoWrite8_io\r
	24	.global PicoWrite16_io\r
cc68a136	25	\r
88fd63ad	26	PicoRead8_sram: @ u32 a\r
	27	ldr r3, =Pico\r
	28	ldr r1, [r3, #OFS_Pico_sv_end]\r
cc68a136	29	cmp r0, r1\r
b4db550e	30	bgt m_read8_nosram\r
88fd63ad	31	ldr r2, [r3, #OFS_Pico_sv_start]\r
88fd63ad	32	cmp r0, r2\r
cc68a136	33	blt m_read8_nosram\r
88fd63ad	34	ldrb r1, [r3, #OFS_Pico_m_sram_reg]\r
0ace9b9a	35	tst r1, #SRR_MAPPED\r
0ace9b9a	36	beq m_read8_nosram\r
88fd63ad	37	ldr r1, [r3, #OFS_Pico_sv_flags]\r
0ace9b9a	38	tst r1, #SRF_EEPROM\r
0ace9b9a	39	bne m_read8_eeprom\r
88fd63ad	40	ldr r1, [r3, #OFS_Pico_sv_data]\r
	41	sub r0, r0, r2\r
	42	ldrb r0, [r0, r1]\r
0ace9b9a	43	bx lr\r
0ace9b9a	44	\r
cc68a136	45	m_read8_nosram:\r
88fd63ad	46	ldr r1, [r3, #OFS_Pico_romsize]\r
cc68a136	47	cmp r0, r1\r
	48	movgt r0, #0\r
	49	bxgt lr @ bad location\r
0ace9b9a	50	@ XXX: banking unfriendly\r
88fd63ad	51	ldr r1, [r3, #OFS_Pico_rom]\r
cc68a136	52	eor r0, r0, #1\r
	53	ldrb r0, [r1, r0]\r
	54	bx lr\r
	55	\r
0ace9b9a	56	m_read8_eeprom:\r
	57	stmfd sp!,{r0,lr}\r
	58	bl EEPROM_read\r
b4db550e	59	ldmfd sp!,{r1,lr}\r
b4db550e	60	tst r1, #1\r
0ace9b9a	61	moveq r0, r0, lsr #8\r
0ace9b9a	62	bx lr\r
29a95187	63	\r
29a95187	64	\r
88fd63ad	65	PicoRead8_io: @ u32 a\r
0ace9b9a	66	bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
0ace9b9a	67	cmp r2, #0xa10000 @ so check for it first\r
531a8f38	68	beq io_ports_read\r
e5503e2f	69	\r
0ace9b9a	70	m_read8_not_io:\r
	71	and r2, r0, #0xfc00\r
	72	cmp r2, #0x1000\r
93f9619e	73	bne PicoRead8_32x\r
0ace9b9a	74	\r
88fd63ad	75	ldr r3, =Pico\r
0ace9b9a	76	mov r1, r0\r
88fd63ad	77	ldr r0, [r3, #OFS_Pico_m_rotate]\r
0ace9b9a	78	add r0, r0, #1\r
88fd63ad	79	strb r0, [r3, #OFS_Pico_m_rotate]\r
0ace9b9a	80	eor r0, r0, r0, lsl #6\r
e5503e2f	81	\r
cc68a136	82	tst r1, #1\r
0ace9b9a	83	bxne lr @ odd addr -> open bus\r
	84	bic r0, r0, #1 @ bit0 defined in this area\r
	85	and r2, r1, #0xff00\r
	86	cmp r2, #0x1100\r
	87	bxne lr @ not busreq\r
	88	\r
88fd63ad	89	ldrb r1, [r3, #OFS_Pico_m_z80Run]\r
88fd63ad	90	ldrb r2, [r3, #OFS_Pico_m_z80_reset]\r
0ace9b9a	91	orr r0, r0, r1\r
0ace9b9a	92	orr r0, r0, r2\r
cc68a136	93	bx lr\r
cc68a136	94	\r
cc68a136	95	@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
cc68a136	96	\r
0ace9b9a	97	PicoRead16_sram: @ u32 a, u32 d\r
88fd63ad	98	ldr r3, =Pico\r
88fd63ad	99	ldr r1, [r3, #OFS_Pico_sv_end]\r
cc68a136	100	cmp r0, r1\r
b4db550e	101	bgt m_read16_nosram\r
88fd63ad	102	ldr r2, [r3, #OFS_Pico_sv_start]\r
88fd63ad	103	cmp r0, r2\r
cc68a136	104	blt m_read16_nosram\r
88fd63ad	105	ldrb r1, [r3, #OFS_Pico_m_sram_reg]\r
0ace9b9a	106	tst r1, #SRR_MAPPED\r
7969166e	107	beq m_read16_nosram\r
88fd63ad	108	ldr r1, [r3, #OFS_Pico_sv_flags]\r
0ace9b9a	109	tst r1, #SRF_EEPROM\r
0ace9b9a	110	bne EEPROM_read\r
88fd63ad	111	ldr r1, [r3, #OFS_Pico_sv_data]\r
	112	sub r0, r0, r2\r
	113	ldrb r1, [r0, r1]!\r
	114	ldrb r0, [r0, #1]\r
0ace9b9a	115	orr r0, r0, r1, lsl #8\r
	116	bx lr\r
	117	\r
cc68a136	118	m_read16_nosram:\r
88fd63ad	119	ldr r1, [r3, #OFS_Pico_romsize]\r
cc68a136	120	cmp r0, r1\r
	121	movgt r0, #0\r
	122	bxgt lr @ bad location\r
0ace9b9a	123	@ XXX: banking unfriendly\r
88fd63ad	124	ldr r1, [r3, #OFS_Pico_rom]\r
cc68a136	125	ldrh r0, [r1, r0]\r
	126	bx lr\r
	127	\r
cc68a136	128	\r
0ace9b9a	129	PicoRead16_io: @ u32 a, u32 d\r
	130	bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
	131	cmp r2, #0xa10000 @ so check for it first\r
	132	bne m_read16_not_io\r
1dceadae	133	stmfd sp!,{lr}\r
531a8f38	134	bl io_ports_read @ same as read8\r
0ace9b9a	135	orr r0, r0, r0, lsl #8 @ only has bytes mirrored\r
1dceadae	136	ldmfd sp!,{pc}\r
cc68a136	137	\r
0ace9b9a	138	m_read16_not_io:\r
	139	and r2, r0, #0xfc00\r
	140	cmp r2, #0x1000\r
93f9619e	141	bne PicoRead16_32x\r
cc68a136	142	\r
88fd63ad	143	ldr r3, =Pico\r
0ace9b9a	144	and r2, r0, #0xff00\r
88fd63ad	145	ldr r0, [r3, #OFS_Pico_m_rotate]\r
0ace9b9a	146	add r0, r0, #1\r
88fd63ad	147	strb r0, [r3, #OFS_Pico_m_rotate]\r
0ace9b9a	148	eor r0, r0, r0, lsl #5\r
	149	eor r0, r0, r0, lsl #8\r
	150	bic r0, r0, #0x100 @ bit8 defined in this area\r
	151	cmp r2, #0x1100\r
	152	bxne lr @ not busreq\r
	153	\r
88fd63ad	154	ldrb r1, [r3, #OFS_Pico_m_z80Run]\r
88fd63ad	155	ldrb r2, [r3, #OFS_Pico_m_z80_reset]\r
0ace9b9a	156	orr r0, r0, r1, lsl #8\r
0ace9b9a	157	orr r0, r0, r2, lsl #8\r
cc68a136	158	bx lr\r
cc68a136	159	\r
e5503e2f	160	@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
e5503e2f	161	\r
0ace9b9a	162	PicoWrite8_io: @ u32 a, u32 d\r
	163	bic r2, r0, #0x1e @ most commonly we get i/o port write,\r
	164	eor r2, r2, #0xa10000 @ so check for it first\r
	165	eors r2, r2, #1\r
531a8f38	166	beq io_ports_write\r
e5503e2f	167	\r
0ace9b9a	168	m_write8_not_io:\r
	169	tst r0, #1\r
	170	bne m_write8_not_z80ctl @ even addrs only\r
	171	and r2, r0, #0xff00\r
	172	cmp r2, #0x1100\r
	173	moveq r0, r1\r
	174	beq ctl_write_z80busreq\r
	175	cmp r2, #0x1200\r
	176	moveq r0, r1\r
	177	beq ctl_write_z80reset\r
	178	\r
	179	m_write8_not_z80ctl:\r
	180	@ unlikely\r
	181	eor r2, r0, #0xa10000\r
	182	eor r2, r2, #0x003000\r
	183	eors r2, r2, #0x0000f1\r
93f9619e	184	bne PicoWrite8_32x\r
88fd63ad	185	ldr r3, =Pico\r
88fd63ad	186	ldrb r2, [r3, #OFS_Pico_m_sram_reg]\r
0ace9b9a	187	and r1, r1, #(SRR_MAPPED\|SRR_READONLY)\r
	188	bic r2, r2, #(SRR_MAPPED\|SRR_READONLY)\r
	189	orr r2, r2, r1\r
88fd63ad	190	strb r2, [r3, #OFS_Pico_m_sram_reg]\r
e5503e2f	191	bx lr\r
e5503e2f	192	\r
0ace9b9a	193	@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
e5503e2f	194	\r
0ace9b9a	195	PicoWrite16_io: @ u32 a, u32 d\r
	196	bic r2, r0, #0x1f @ most commonly we get i/o port write,\r
	197	cmp r2, #0xa10000 @ so check for it first\r
531a8f38	198	beq io_ports_write\r
0ace9b9a	199	\r
	200	m_write16_not_io:\r
	201	and r2, r0, #0xff00\r
	202	cmp r2, #0x1100\r
	203	moveq r0, r1, lsr #8\r
	204	beq ctl_write_z80busreq\r
	205	cmp r2, #0x1200\r
	206	moveq r0, r1, lsr #8\r
	207	beq ctl_write_z80reset\r
	208	\r
	209	m_write16_not_z80ctl:\r
	210	@ unlikely\r
	211	eor r2, r0, #0xa10000\r
	212	eor r2, r2, #0x003000\r
	213	eors r2, r2, #0x0000f0\r
93f9619e	214	bne PicoWrite16_32x\r
88fd63ad	215	ldr r3, =Pico\r
88fd63ad	216	ldrb r2, [r3, #OFS_Pico_m_sram_reg]\r
0ace9b9a	217	and r1, r1, #(SRR_MAPPED\|SRR_READONLY)\r
	218	bic r2, r2, #(SRR_MAPPED\|SRR_READONLY)\r
	219	orr r2, r2, r1\r
88fd63ad	220	strb r2, [r3, #OFS_Pico_m_sram_reg]\r
0ace9b9a	221	bx lr\r
e5503e2f	222	\r
0ace9b9a	223	.pool\r
e5503e2f	224	\r
cff531af	225	@ vim:filetype=armasm\r