recognize the MED ssf2 header
[picodrive.git] / pico / memory_arm.s
CommitLineData
cff531af 1/*\r
2 * PicoDrive\r
3 * (C) notaz, 2006-2009\r
4 *\r
5 * This work is licensed under the terms of MAME license.\r
6 * See COPYING file in the top-level directory.\r
7 */\r
cc68a136 8\r
0ace9b9a 9.equ SRR_MAPPED, (1 << 0)\r
10.equ SRR_READONLY, (1 << 1)\r
11.equ SRF_EEPROM, (1 << 1)\r
db1d3564 12.equ POPT_EN_32X, (1 << 20)\r
cc68a136 13\r
14.text\r
3ec29f01 15.align 4\r
cc68a136 16\r
0ace9b9a 17.global PicoRead8_sram\r
18.global PicoRead8_io\r
19.global PicoRead16_sram\r
20.global PicoRead16_io\r
21.global PicoWrite8_io\r
22.global PicoWrite16_io\r
cc68a136 23\r
0ace9b9a 24PicoRead8_sram: @ u32 a, u32 d\r
cc68a136 25 ldr r2, =(SRam)\r
26 ldr r3, =(Pico+0x22200)\r
27 ldr r1, [r2, #8] @ SRam.end\r
cc68a136 28 cmp r0, r1\r
b4db550e 29 bgt m_read8_nosram\r
7969166e 30 ldr r1, [r2, #4] @ SRam.start\r
cc68a136 31 cmp r0, r1\r
32 blt m_read8_nosram\r
7969166e 33 ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
0ace9b9a 34 tst r1, #SRR_MAPPED\r
35 beq m_read8_nosram\r
36 ldr r1, [r2, #0x0c]\r
37 tst r1, #SRF_EEPROM\r
38 bne m_read8_eeprom\r
39 ldr r1, [r2, #4] @ SRam.start\r
40 ldr r2, [r2] @ SRam.data\r
41 sub r0, r0, r1\r
42 add r0, r0, r2\r
43 ldrb r0, [r0]\r
44 bx lr\r
45\r
cc68a136 46m_read8_nosram:\r
7969166e 47 ldr r1, [r3, #4] @ romsize\r
cc68a136 48 cmp r0, r1\r
49 movgt r0, #0\r
50 bxgt lr @ bad location\r
0ace9b9a 51 @ XXX: banking unfriendly\r
cc68a136 52 ldr r1, [r3]\r
53 eor r0, r0, #1\r
54 ldrb r0, [r1, r0]\r
55 bx lr\r
56\r
0ace9b9a 57m_read8_eeprom:\r
58 stmfd sp!,{r0,lr}\r
59 bl EEPROM_read\r
b4db550e 60 ldmfd sp!,{r1,lr}\r
61 tst r1, #1\r
0ace9b9a 62 moveq r0, r0, lsr #8\r
63 bx lr\r
29a95187 64\r
29a95187 65\r
0ace9b9a 66PicoRead8_io: @ u32 a, u32 d\r
67 bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
68 cmp r2, #0xa10000 @ so check for it first\r
531a8f38 69 beq io_ports_read\r
e5503e2f 70\r
0ace9b9a 71m_read8_not_io:\r
72 and r2, r0, #0xfc00\r
73 cmp r2, #0x1000\r
74 bne m_read8_not_brq\r
75\r
e5503e2f 76 ldr r3, =(Pico+0x22200)\r
0ace9b9a 77 mov r1, r0\r
78 ldr r0, [r3, #8] @ Pico.m.rotate\r
79 add r0, r0, #1\r
80 strb r0, [r3, #8]\r
81 eor r0, r0, r0, lsl #6\r
e5503e2f 82\r
cc68a136 83 tst r1, #1\r
0ace9b9a 84 bxne lr @ odd addr -> open bus\r
85 bic r0, r0, #1 @ bit0 defined in this area\r
86 and r2, r1, #0xff00\r
87 cmp r2, #0x1100\r
88 bxne lr @ not busreq\r
89\r
90 ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r
91 ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r
92 orr r0, r0, r1\r
93 orr r0, r0, r2\r
cc68a136 94 bx lr\r
95\r
0ace9b9a 96m_read8_not_brq:\r
97 ldr r2, =PicoOpt\r
0ffefdb8 98 ldr r2, [r2]\r
db1d3564 99 tst r2, #POPT_EN_32X\r
100 bne PicoRead8_32x\r
0ace9b9a 101 mov r0, #0\r
cc68a136 102 bx lr\r
103\r
cc68a136 104@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
105\r
0ace9b9a 106PicoRead16_sram: @ u32 a, u32 d\r
cc68a136 107 ldr r2, =(SRam)\r
108 ldr r3, =(Pico+0x22200)\r
109 ldr r1, [r2, #8] @ SRam.end\r
cc68a136 110 cmp r0, r1\r
b4db550e 111 bgt m_read16_nosram\r
7969166e 112 ldr r1, [r2, #4] @ SRam.start\r
cc68a136 113 cmp r0, r1\r
114 blt m_read16_nosram\r
7969166e 115 ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
0ace9b9a 116 tst r1, #SRR_MAPPED\r
7969166e 117 beq m_read16_nosram\r
0ace9b9a 118 ldr r1, [r2, #0x0c]\r
119 tst r1, #SRF_EEPROM\r
120 bne EEPROM_read\r
121 ldr r1, [r2, #4] @ SRam.start\r
122 ldr r2, [r2] @ SRam.data\r
123 sub r0, r0, r1\r
124 add r0, r0, r2\r
125 ldrb r1, [r0], #1\r
126 ldrb r0, [r0]\r
127 orr r0, r0, r1, lsl #8\r
128 bx lr\r
129\r
cc68a136 130m_read16_nosram:\r
7969166e 131 ldr r1, [r3, #4] @ romsize\r
cc68a136 132 cmp r0, r1\r
133 movgt r0, #0\r
134 bxgt lr @ bad location\r
0ace9b9a 135 @ XXX: banking unfriendly\r
136 ldr r1, [r3]\r
cc68a136 137 ldrh r0, [r1, r0]\r
138 bx lr\r
139\r
cc68a136 140\r
0ace9b9a 141PicoRead16_io: @ u32 a, u32 d\r
142 bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
143 cmp r2, #0xa10000 @ so check for it first\r
144 bne m_read16_not_io\r
1dceadae 145 stmfd sp!,{lr}\r
531a8f38 146 bl io_ports_read @ same as read8\r
0ace9b9a 147 orr r0, r0, r0, lsl #8 @ only has bytes mirrored\r
1dceadae 148 ldmfd sp!,{pc}\r
cc68a136 149\r
0ace9b9a 150m_read16_not_io:\r
151 and r2, r0, #0xfc00\r
152 cmp r2, #0x1000\r
153 bne m_read16_not_brq\r
cc68a136 154\r
cc68a136 155 ldr r3, =(Pico+0x22200)\r
0ace9b9a 156 and r2, r0, #0xff00\r
157 ldr r0, [r3, #8] @ Pico.m.rotate\r
158 add r0, r0, #1\r
159 strb r0, [r3, #8]\r
160 eor r0, r0, r0, lsl #5\r
161 eor r0, r0, r0, lsl #8\r
162 bic r0, r0, #0x100 @ bit8 defined in this area\r
163 cmp r2, #0x1100\r
164 bxne lr @ not busreq\r
165\r
166 ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r
167 ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r
168 orr r0, r0, r1, lsl #8\r
169 orr r0, r0, r2, lsl #8\r
cc68a136 170 bx lr\r
171\r
0ace9b9a 172m_read16_not_brq:\r
173 ldr r2, =PicoOpt\r
0ffefdb8 174 ldr r2, [r2]\r
db1d3564 175 tst r2, #POPT_EN_32X\r
176 bne PicoRead16_32x\r
0ace9b9a 177 mov r0, #0\r
cc68a136 178 bx lr\r
721cd396 179\r
e5503e2f 180@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
181\r
0ace9b9a 182PicoWrite8_io: @ u32 a, u32 d\r
183 bic r2, r0, #0x1e @ most commonly we get i/o port write,\r
184 eor r2, r2, #0xa10000 @ so check for it first\r
185 eors r2, r2, #1\r
531a8f38 186 beq io_ports_write\r
e5503e2f 187\r
0ace9b9a 188m_write8_not_io:\r
189 tst r0, #1\r
190 bne m_write8_not_z80ctl @ even addrs only\r
191 and r2, r0, #0xff00\r
192 cmp r2, #0x1100\r
193 moveq r0, r1\r
194 beq ctl_write_z80busreq\r
195 cmp r2, #0x1200\r
196 moveq r0, r1\r
197 beq ctl_write_z80reset\r
198\r
199m_write8_not_z80ctl:\r
200 @ unlikely\r
201 eor r2, r0, #0xa10000\r
202 eor r2, r2, #0x003000\r
203 eors r2, r2, #0x0000f1\r
204 bne m_write8_not_sreg\r
205 ldr r3, =(Pico+0x22200)\r
206 ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r
207 and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
208 bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
209 orr r2, r2, r1\r
210 strb r2, [r3, #(8+9)]\r
e5503e2f 211 bx lr\r
212\r
0ace9b9a 213m_write8_not_sreg:\r
214 ldr r2, =PicoOpt\r
215 ldr r2, [r2]\r
db1d3564 216 tst r2, #POPT_EN_32X\r
217 bne PicoWrite8_32x\r
e5503e2f 218 bx lr\r
219\r
0ace9b9a 220@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
e5503e2f 221\r
0ace9b9a 222PicoWrite16_io: @ u32 a, u32 d\r
223 bic r2, r0, #0x1f @ most commonly we get i/o port write,\r
224 cmp r2, #0xa10000 @ so check for it first\r
531a8f38 225 beq io_ports_write\r
0ace9b9a 226\r
227m_write16_not_io:\r
228 and r2, r0, #0xff00\r
229 cmp r2, #0x1100\r
230 moveq r0, r1, lsr #8\r
231 beq ctl_write_z80busreq\r
232 cmp r2, #0x1200\r
233 moveq r0, r1, lsr #8\r
234 beq ctl_write_z80reset\r
235\r
236m_write16_not_z80ctl:\r
237 @ unlikely\r
238 eor r2, r0, #0xa10000\r
239 eor r2, r2, #0x003000\r
240 eors r2, r2, #0x0000f0\r
241 bne m_write16_not_sreg\r
242 ldr r3, =(Pico+0x22200)\r
243 ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r
244 and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
245 bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
246 orr r2, r2, r1\r
247 strb r2, [r3, #(8+9)]\r
248 bx lr\r
e5503e2f 249\r
0ace9b9a 250m_write16_not_sreg:\r
e5503e2f 251 ldr r2, =PicoOpt\r
e5503e2f 252 ldr r2, [r2]\r
db1d3564 253 tst r2, #POPT_EN_32X\r
254 bne PicoWrite16_32x\r
0ace9b9a 255 bx lr\r
256\r
257.pool\r
e5503e2f 258\r
cff531af 259@ vim:filetype=armasm\r