32x: sh2mame: critical bugfix (irqs on delay slot) + global cycle counter
[picodrive.git] / pico / pico_cmn.c
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8b99ab90 1// common code for Pico.c and cd/Pico.c
acd35d4c 2// (c) Copyright 2007-2009 Grazvydas "notaz" Ignotas
8b99ab90 3
69996cb7 4#define CYCLES_M68K_LINE 488 // suitable for both PAL/NTSC
5#define CYCLES_M68K_VINT_LAG 68
6#define CYCLES_M68K_ASD 148
bf5fbbb4 7#define CYCLES_S68K_LINE 795
8#define CYCLES_S68K_ASD 241
69996cb7 9
10// pad delay (for 6 button pads)
11#define PAD_DELAY \
602133e1 12 if (PicoOpt&POPT_6BTN_PAD) { \
69996cb7 13 if(Pico.m.padDelay[0]++ > 25) Pico.m.padTHPhase[0]=0; \
14 if(Pico.m.padDelay[1]++ > 25) Pico.m.padTHPhase[1]=0; \
15 }
16
bf5fbbb4 17// CPUS_RUN
acd35d4c 18#ifndef RUN_SH2S
be20816c 19#define RUN_SH2S(x)
acd35d4c 20#endif
21
bf5fbbb4 22#ifndef PICO_CD
538a6098 23#define CPUS_RUN(m68k_cycles,s68k_cycles) \
acd35d4c 24{ \
25 SekRunM68k(m68k_cycles); \
be20816c 26 RUN_SH2S(m68k_cycles); \
acd35d4c 27}
bf5fbbb4 28#else
538a6098 29#define CPUS_RUN(m68k_cycles,s68k_cycles) \
bf5fbbb4 30{ \
602133e1 31 if ((PicoOpt&POPT_EN_MCD_PSYNC) && (Pico_mcd->m.busreq&3) == 1) { \
bf5fbbb4 32 SekRunPS(m68k_cycles, s68k_cycles); /* "better/perfect sync" */ \
33 } else { \
34 SekRunM68k(m68k_cycles); \
35 if ((Pico_mcd->m.busreq&3) == 1) /* no busreq/no reset */ \
36 SekRunS68k(s68k_cycles); \
37 } \
bf5fbbb4 38}
39#endif
40
69996cb7 41static int PicoFrameHints(void)
42{
43 struct PicoVideo *pv=&Pico.video;
9761a7d0 44 int lines, y, lines_vis = 224, line_sample, skip, vcnt_wrap;
69996cb7 45 int hint; // Hint counter
46
9761a7d0 47 pv->v_counter = Pico.m.scanline = 0;
538a6098 48
602133e1 49 if ((PicoOpt&POPT_ALT_RENDERER) && !PicoSkipFrame && (pv->reg[1]&0x40)) { // fast rend., display enabled
03e4f2a3 50 // draw a frame just after vblank in alternative render mode
51 // yes, this will cause 1 frame lag, but this is inaccurate mode anyway.
52 PicoFrameFull();
53#ifdef DRAW_FINISH_FUNC
54 DRAW_FINISH_FUNC();
55#endif
56 skip = 1;
57 }
58 else skip=PicoSkipFrame;
59
69996cb7 60 if (Pico.m.pal) {
69996cb7 61 line_sample = 68;
9761a7d0 62 if (pv->reg[1]&8) lines_vis = 240;
69996cb7 63 } else {
69996cb7 64 line_sample = 93;
65 }
66
67 SekCyclesReset();
4b9c5888 68 z80_resetCycles();
bf5fbbb4 69#ifdef PICO_CD
70 SekCyclesResetS68k();
71#endif
4b9c5888 72 PsndDacLine = 0;
7b3f44c6 73 emustatus &= ~1;
69996cb7 74
75 pv->status&=~0x88; // clear V-Int, come out of vblank
76
77 hint=pv->reg[10]; // Load H-Int counter
78 //dprintf("-hint: %i", hint);
79
80 // This is to make active scan longer (needed for Double Dragon 2, mainly)
538a6098 81 CPUS_RUN(CYCLES_M68K_ASD, CYCLES_S68K_ASD);
69996cb7 82
b6d7ac70 83 for (y = 0; y < lines_vis; y++)
69996cb7 84 {
9761a7d0 85 pv->v_counter = Pico.m.scanline = y;
86 if ((pv->reg[12]&6) == 6) { // interlace mode 2
87 pv->v_counter <<= 1;
88 pv->v_counter |= pv->v_counter >> 8;
89 pv->v_counter &= 0xff;
90 }
69996cb7 91
92 // VDP FIFO
93 pv->lwrite_cnt -= 12;
94 if (pv->lwrite_cnt <= 0) {
95 pv->lwrite_cnt=0;
96 Pico.video.status|=0x200;
97 }
98
99 PAD_DELAY
bf5fbbb4 100#ifdef PICO_CD
101 check_cd_dma();
102#endif
db1d3564 103#ifdef PICO_32X
be20816c 104 p32x_pwm_irq_check(1);
db1d3564 105#endif
69996cb7 106
107 // H-Interrupts:
108 if (--hint < 0) // y <= lines_vis: Comix Zone, Golden Axe
109 {
110 hint=pv->reg[10]; // Reload H-Int counter
111 pv->pending_ints|=0x10;
112 if (pv->reg[0]&0x10) {
113 elprintf(EL_INTS, "hint: @ %06x [%i]", SekPc, SekCycleCnt);
114 SekInterrupt(4);
115 }
116 }
117
118 // decide if we draw this line
b6d7ac70 119 if (!skip && (PicoOpt & POPT_ALT_RENDERER))
fad24893 120 {
b6d7ac70 121 // find the right moment for frame renderer, when display is no longer blanked
122 if ((pv->reg[1]&0x40) || y > 100) {
123 PicoFrameFull();
fad24893 124#ifdef DRAW_FINISH_FUNC
b6d7ac70 125 DRAW_FINISH_FUNC();
fad24893 126#endif
b6d7ac70 127 skip = 1;
fad24893 128 }
129 }
69996cb7 130
69996cb7 131 // get samples from sound chips
7b3f44c6 132 if ((y == 224 || y == line_sample) && PsndOut)
4b9c5888 133 {
be297089 134 if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
4b9c5888 135 PicoSyncZ80(SekCycleCnt);
136 if (ym2612.dacen && PsndDacLine <= y)
137 PsndDoDAC(y);
7b3f44c6 138 PsndGetSamples(y);
4b9c5888 139 }
69996cb7 140
141 // Run scanline:
142 if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
538a6098 143 CPUS_RUN(CYCLES_M68K_LINE, CYCLES_S68K_LINE);
bf5fbbb4 144
145#ifdef PICO_CD
146 update_chips();
017512f2 147#else
b0677887 148 if (PicoLineHook) PicoLineHook();
bf5fbbb4 149#endif
69996cb7 150 }
151
03e4f2a3 152 if (!skip)
b6d7ac70 153 {
154 if (DrawScanline < y)
155 PicoDrawSync(y - 1, 0);
156#ifdef DRAW_FINISH_FUNC
03e4f2a3 157 DRAW_FINISH_FUNC();
8ab3e3c1 158#endif
b6d7ac70 159 }
8ab3e3c1 160
947fb5f9 161 // V-int line (224 or 240)
162 Pico.m.scanline = y;
163 pv->v_counter = 0xe0; // bad for 240 mode
164 if ((pv->reg[12]&6) == 6) pv->v_counter = 0xc1;
165
69996cb7 166 // VDP FIFO
167 pv->lwrite_cnt=0;
168 Pico.video.status|=0x200;
169
5f9a0d16 170 memcpy(PicoPadInt, PicoPad, sizeof(PicoPadInt));
69996cb7 171 PAD_DELAY
bf5fbbb4 172#ifdef PICO_CD
173 check_cd_dma();
174#endif
db1d3564 175#ifdef PICO_32X
be20816c 176 p32x_pwm_irq_check(1);
db1d3564 177#endif
69996cb7 178
179 // Last H-Int:
180 if (--hint < 0)
181 {
182 hint=pv->reg[10]; // Reload H-Int counter
183 pv->pending_ints|=0x10;
184 //printf("rhint: %i @ %06x [%i|%i]\n", hint, SekPc, y, SekCycleCnt);
185 if (pv->reg[0]&0x10) SekInterrupt(4);
186 }
187
69996cb7 188 pv->status|=0x08; // go into vblank
189 pv->pending_ints|=0x20;
190
974fdb5b 191#ifdef PICO_32X
192 p32x_start_blank();
193#endif
194
69996cb7 195 // the following SekRun is there for several reasons:
196 // there must be a delay after vblank bit is set and irq is asserted (Mazin Saga)
197 // also delay between F bit (bit 7) is set in SR and IRQ happens (Ex-Mutants)
198 // also delay between last H-int and V-int (Golden Axe 3)
bf5fbbb4 199 SekRunM68k(CYCLES_M68K_VINT_LAG);
4b9c5888 200
69996cb7 201 if (pv->reg[1]&0x20) {
202 elprintf(EL_INTS, "vint: @ %06x [%i]", SekPc, SekCycleCnt);
203 SekInterrupt(6);
204 }
be297089 205 if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80)) {
4b9c5888 206 PicoSyncZ80(SekCycleCnt);
583ab72c 207 elprintf(EL_INTS, "zint");
69996cb7 208 z80_int();
583ab72c 209 }
69996cb7 210
69996cb7 211 // get samples from sound chips
7b3f44c6 212 if (y == 224 && PsndOut)
213 {
214 if (ym2612.dacen && PsndDacLine <= y)
215 PsndDoDAC(y);
216 PsndGetSamples(y);
217 }
69996cb7 218
219 // Run scanline:
220 if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
bf5fbbb4 221 CPUS_RUN(CYCLES_M68K_LINE - CYCLES_M68K_VINT_LAG - CYCLES_M68K_ASD,
538a6098 222 CYCLES_S68K_LINE - CYCLES_S68K_ASD);
bf5fbbb4 223
224#ifdef PICO_CD
017512f2 225 update_chips();
226#else
b0677887 227 if (PicoLineHook) PicoLineHook();
bf5fbbb4 228#endif
69996cb7 229
5e128c6d 230 lines = scanlines_total;
231 vcnt_wrap = Pico.m.pal ? 0x103 : 0xEB; // based on Gens, TODO: verify
69996cb7 232
b6d7ac70 233 for (y++; y < lines; y++)
69996cb7 234 {
9761a7d0 235 pv->v_counter = Pico.m.scanline = y;
236 if (y >= vcnt_wrap)
237 pv->v_counter -= Pico.m.pal ? 56 : 6;
238 if ((pv->reg[12]&6) == 6)
239 pv->v_counter = (pv->v_counter << 1) | 1;
240 pv->v_counter &= 0xff;
69996cb7 241
242 PAD_DELAY
bf5fbbb4 243#ifdef PICO_CD
244 check_cd_dma();
245#endif
db1d3564 246#ifdef PICO_32X
be20816c 247 p32x_pwm_irq_check(1);
db1d3564 248#endif
69996cb7 249
69996cb7 250 // Run scanline:
251 if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
538a6098 252 CPUS_RUN(CYCLES_M68K_LINE, CYCLES_S68K_LINE);
bf5fbbb4 253
254#ifdef PICO_CD
255 update_chips();
017512f2 256#else
b0677887 257 if (PicoLineHook) PicoLineHook();
bf5fbbb4 258#endif
69996cb7 259 }
260
4b9c5888 261 // sync z80
be297089 262 if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
e53704e6 263 PicoSyncZ80(Pico.m.pal ? 151809 : 127671); // cycles adjusted for converter
4b9c5888 264 if (PsndOut && ym2612.dacen && PsndDacLine <= lines-1)
265 PsndDoDAC(lines-1);
266
e53704e6 267 timers_cycle();
268
69996cb7 269 return 0;
270}
271
272#undef PAD_DELAY
bf5fbbb4 273#undef CPUS_RUN
69996cb7 274