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drc: support ms ABI
[picodrive.git] / cpu / drc / emit_arm.c
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1/*
2 * Basic macros to emit ARM instructions and some utils
3 * Copyright (C) 2008,2009,2010 notaz
4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 */
8#define CONTEXT_REG 11
9#define RET_REG 0
10
11// XXX: tcache_ptr type for SVP and SH2 compilers differs..
12#define EMIT_PTR(ptr, x) \
13 do { \
14 *(u32 *)ptr = x; \
15 ptr = (void *)((u8 *)ptr + sizeof(u32)); \
16 COUNT_OP; \
17 } while (0)
18
19#define EMIT(x) EMIT_PTR(tcache_ptr, x)
20
21#define A_R4M (1 << 4)
22#define A_R5M (1 << 5)
23#define A_R6M (1 << 6)
24#define A_R7M (1 << 7)
25#define A_R8M (1 << 8)
26#define A_R9M (1 << 9)
27#define A_R10M (1 << 10)
28#define A_R11M (1 << 11)
29#define A_R12M (1 << 12)
30#define A_R14M (1 << 14)
31#define A_R15M (1 << 15)
32
33#define A_COND_AL 0xe
34#define A_COND_EQ 0x0
35#define A_COND_NE 0x1
36#define A_COND_HS 0x2
37#define A_COND_LO 0x3
38#define A_COND_MI 0x4
39#define A_COND_PL 0x5
40#define A_COND_VS 0x6
41#define A_COND_VC 0x7
42#define A_COND_HI 0x8
43#define A_COND_LS 0x9
44#define A_COND_GE 0xa
45#define A_COND_LT 0xb
46#define A_COND_GT 0xc
47#define A_COND_LE 0xd
48#define A_COND_CS A_COND_HS
49#define A_COND_CC A_COND_LO
50
51/* unified conditions */
52#define DCOND_EQ A_COND_EQ
53#define DCOND_NE A_COND_NE
54#define DCOND_MI A_COND_MI
55#define DCOND_PL A_COND_PL
56#define DCOND_HI A_COND_HI
57#define DCOND_HS A_COND_HS
58#define DCOND_LO A_COND_LO
59#define DCOND_GE A_COND_GE
60#define DCOND_GT A_COND_GT
61#define DCOND_LT A_COND_LT
62#define DCOND_LS A_COND_LS
63#define DCOND_LE A_COND_LE
64#define DCOND_VS A_COND_VS
65#define DCOND_VC A_COND_VC
66
67/* addressing mode 1 */
68#define A_AM1_LSL 0
69#define A_AM1_LSR 1
70#define A_AM1_ASR 2
71#define A_AM1_ROR 3
72
73#define A_AM1_IMM(ror2,imm8) (((ror2)<<8) | (imm8) | 0x02000000)
74#define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
75#define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
76
77/* data processing op */
78#define A_OP_AND 0x0
79#define A_OP_EOR 0x1
80#define A_OP_SUB 0x2
81#define A_OP_RSB 0x3
82#define A_OP_ADD 0x4
83#define A_OP_ADC 0x5
84#define A_OP_SBC 0x6
85#define A_OP_RSC 0x7
86#define A_OP_TST 0x8
87#define A_OP_TEQ 0x9
88#define A_OP_CMP 0xa
89#define A_OP_CMN 0xa
90#define A_OP_ORR 0xc
91#define A_OP_MOV 0xd
92#define A_OP_BIC 0xe
93#define A_OP_MVN 0xf
94
95#define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
96 EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
97
98#define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
99#define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
100#define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm))
101
102#define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
103#define EOP_MVN_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MVN,0, 0,rd,ror2,imm8)
104#define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
105#define EOP_EOR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_EOR,0,rn,rd,ror2,imm8)
106#define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
107#define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
108#define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
109#define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
110#define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
111#define EOP_CMP_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
112#define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
113
114#define EOP_MOV_IMM_C(cond,rd, ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_MOV,0, 0,rd,ror2,imm8)
115#define EOP_ORR_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_ORR,0,rn,rd,ror2,imm8)
116#define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
117
118#define EOP_MOV_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
119#define EOP_MVN_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MVN,s, 0,rd,shift_imm,shift_op,rm)
120#define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
121#define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
122#define EOP_ADC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADC,s,rn,rd,shift_imm,shift_op,rm)
123#define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
124#define EOP_SBC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SBC,s,rn,rd,shift_imm,shift_op,rm)
125#define EOP_AND_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_AND,s,rn,rd,shift_imm,shift_op,rm)
126#define EOP_EOR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_EOR,s,rn,rd,shift_imm,shift_op,rm)
127#define EOP_CMP_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_CMP,1,rn, 0,shift_imm,shift_op,rm)
128#define EOP_TST_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
129#define EOP_TEQ_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
130
131#define EOP_MOV_REG2(s,rd, rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
132#define EOP_ADD_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
133#define EOP_SUB_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
134
135#define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,0)
136#define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,shift_imm)
137#define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSR,shift_imm)
138#define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ASR,shift_imm)
139#define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ROR,shift_imm)
140
141#define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
142#define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
143#define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
144#define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ASR,shift_imm)
145#define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ROR,shift_imm)
146
147#define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
148#define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
149#define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
150
151#define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG(A_COND_AL, rn, 0,A_AM1_LSL,rm)
152
153#define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_LSL,rs)
154#define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_ROR,rs)
155#define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
156#define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
157
158/* addressing mode 2 */
159#define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
160 EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
161
162#define EOP_C_AM2_REG(cond,u,b,l,rn,rd,shift_imm,shift_op,rm) \
163 EMIT(((cond)<<28) | 0x07000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
164 ((shift_imm)<<7) | ((shift_op)<<5) | (rm))
165
166/* addressing mode 3 */
167#define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
168 EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
169 ((s)<<6) | ((h)<<5) | (immed_reg))
170
171#define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
172
173#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
174
175/* ldr and str */
176#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
177#define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,1,1,rn,rd,offset_12)
178
179#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
180#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
181#define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
182#define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
183#define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
184
185#define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
186
187#define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8)
188
189#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
190#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
191#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
192#define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
193#define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
194#define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
195
196/* ldm and stm */
197#define EOP_XXM(cond,p,u,s,w,l,rn,list) \
198 EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
199
200#define EOP_STMIA(rb,list) EOP_XXM(A_COND_AL,0,1,0,0,0,rb,list)
201#define EOP_LDMIA(rb,list) EOP_XXM(A_COND_AL,0,1,0,0,1,rb,list)
202
203#define EOP_STMFD_SP(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
204#define EOP_LDMFD_SP(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
205
206/* branches */
207#define EOP_C_BX(cond,rm) \
208 EMIT(((cond)<<28) | 0x012fff10 | (rm))
209
210#define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \
211 EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
212
213#define EOP_C_B(cond,l,signed_immed_24) \
214 EOP_C_B_PTR(tcache_ptr,cond,l,signed_immed_24)
215
216#define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
217#define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
218
219/* misc */
220#define EOP_C_MUL(cond,s,rd,rs,rm) \
221 EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
222
223#define EOP_C_UMULL(cond,s,rdhi,rdlo,rs,rm) \
224 EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
225
226#define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
227 EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
228
229#define EOP_C_SMLAL(cond,s,rdhi,rdlo,rs,rm) \
230 EMIT(((cond)<<28) | 0x00e00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
231
232#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
233
234#define EOP_C_MRS(cond,rd) \
235 EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
236
237#define EOP_C_MSR_IMM(cond,ror2,imm) \
238 EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
239
240#define EOP_C_MSR_REG(cond,rm) \
241 EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
242
243#define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd)
244#define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
245#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
246
247#define EOP_MOVW(rd,imm) \
248 EMIT(0xe3000000 | ((rd)<<12) | ((imm)&0xfff) | (((imm)<<4)&0xf0000))
249
250#define EOP_MOVT(rd,imm) \
251 EMIT(0xe3400000 | ((rd)<<12) | (((imm)>>16)&0xfff) | (((imm)>>12)&0xf0000))
252
253// XXX: AND, RSB, *C, will break if 1 insn is not enough
254static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm)
255{
256 int ror2;
257 u32 v;
258
259 switch (op) {
260 case A_OP_MOV:
261 rn = 0;
262 if (~imm < 0x10000) {
263 imm = ~imm;
264 op = A_OP_MVN;
265 }
266#ifdef HAVE_ARMV7
267 for (v = imm, ror2 = 0; v && !(v & 3); v >>= 2)
268 ror2--;
269 if (v >> 8) {
270 /* 2+ insns needed - prefer movw/movt */
271 if (op == A_OP_MVN)
272 imm = ~imm;
273 EOP_MOVW(rd, imm);
274 if (imm & 0xffff0000)
275 EOP_MOVT(rd, imm);
276 return;
277 }
278#endif
279 break;
280
281 case A_OP_EOR:
282 case A_OP_SUB:
283 case A_OP_ADD:
284 case A_OP_ORR:
285 case A_OP_BIC:
286 if (s == 0 && imm == 0)
287 return;
288 break;
289 }
290
291 for (v = imm, ror2 = 0; ; ror2 -= 8/2) {
292 /* shift down to get 'best' rot2 */
293 for (; v && !(v & 3); v >>= 2)
294 ror2--;
295
296 EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
297
298 v >>= 8;
299 if (v == 0)
300 break;
301 if (op == A_OP_MOV)
302 op = A_OP_ORR;
303 if (op == A_OP_MVN)
304 op = A_OP_BIC;
305 rn = rd;
306 }
307}
308
309#define emith_op_imm(cond, s, op, r, imm) \
310 emith_op_imm2(cond, s, op, r, r, imm)
311
312// test op
313#define emith_top_imm(cond, op, r, imm) do { \
314 u32 ror2, v; \
315 for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \
316 ror2--; \
317 EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \
318} while (0)
319
320#define is_offset_24(val) \
321 ((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
322
323static int emith_xbranch(int cond, void *target, int is_call)
324{
325 int val = (u32 *)target - (u32 *)tcache_ptr - 2;
326 int direct = is_offset_24(val);
327 u32 *start_ptr = (u32 *)tcache_ptr;
328
329 if (direct)
330 {
331 EOP_C_B(cond,is_call,val & 0xffffff); // b, bl target
332 }
333 else
334 {
335#ifdef __EPOC32__
336// elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
337 if (is_call)
338 EOP_ADD_IMM(14,15,0,8); // add lr,pc,#8
339 EOP_C_AM2_IMM(cond,1,0,1,15,15,0); // ldrcc pc,[pc]
340 EOP_MOV_REG_SIMPLE(15,15); // mov pc, pc
341 EMIT((u32)target);
342#else
343 // should never happen
344 elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
345 exit(1);
346#endif
347 }
348
349 return (u32 *)tcache_ptr - start_ptr;
350}
351
352#define JMP_POS(ptr) \
353 ptr = tcache_ptr; \
354 tcache_ptr += sizeof(u32)
355
356#define JMP_EMIT(cond, ptr) { \
357 u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
358 EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \
359}
360
361#define EMITH_JMP_START(cond) { \
362 void *cond_ptr; \
363 JMP_POS(cond_ptr)
364
365#define EMITH_JMP_END(cond) \
366 JMP_EMIT(cond, cond_ptr); \
367}
368
369// fake "simple" or "short" jump - using cond insns instead
370#define EMITH_NOTHING1(cond) \
371 (void)(cond)
372
373#define EMITH_SJMP_DECL_()
374#define EMITH_SJMP_START_(cond) EMITH_NOTHING1(cond)
375#define EMITH_SJMP_END_(cond) EMITH_NOTHING1(cond)
376#define EMITH_SJMP_START(cond) EMITH_NOTHING1(cond)
377#define EMITH_SJMP_END(cond) EMITH_NOTHING1(cond)
378#define EMITH_SJMP3_START(cond) EMITH_NOTHING1(cond)
379#define EMITH_SJMP3_MID(cond) EMITH_NOTHING1(cond)
380#define EMITH_SJMP3_END()
381
382#define emith_move_r_r(d, s) \
383 EOP_MOV_REG_SIMPLE(d, s)
384
385#define emith_move_r_r_ptr(d, s) \
386 emith_move_r_r(d, s)
387
388#define emith_mvn_r_r(d, s) \
389 EOP_MVN_REG(A_COND_AL,0,d,s,A_AM1_LSL,0)
390
391#define emith_add_r_r_r_lsl(d, s1, s2, lslimm) \
392 EOP_ADD_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
393
394#define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
395 EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
396
397#define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
398 EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
399
400#define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) \
401 EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSR,lsrimm)
402
403#define emith_or_r_r_lsl(d, s, lslimm) \
404 emith_or_r_r_r_lsl(d, d, s, lslimm)
405
406#define emith_eor_r_r_lsr(d, s, lsrimm) \
407 emith_eor_r_r_r_lsr(d, d, s, lsrimm)
408
409#define emith_add_r_r_r(d, s1, s2) \
410 emith_add_r_r_r_lsl(d, s1, s2, 0)
411
412#define emith_or_r_r_r(d, s1, s2) \
413 emith_or_r_r_r_lsl(d, s1, s2, 0)
414
415#define emith_eor_r_r_r(d, s1, s2) \
416 emith_eor_r_r_r_lsl(d, s1, s2, 0)
417
418#define emith_add_r_r(d, s) \
419 emith_add_r_r_r(d, d, s)
420
421#define emith_sub_r_r(d, s) \
422 EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
423
424#define emith_adc_r_r(d, s) \
425 EOP_ADC_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
426
427#define emith_and_r_r(d, s) \
428 EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
429
430#define emith_or_r_r(d, s) \
431 emith_or_r_r_r(d, d, s)
432
433#define emith_eor_r_r(d, s) \
434 emith_eor_r_r_r(d, d, s)
435
436#define emith_tst_r_r(d, s) \
437 EOP_TST_REG(A_COND_AL,d,s,A_AM1_LSL,0)
438
439#define emith_tst_r_r_ptr(d, s) \
440 emith_tst_r_r(d, s)
441
442#define emith_teq_r_r(d, s) \
443 EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
444
445#define emith_cmp_r_r(d, s) \
446 EOP_CMP_REG(A_COND_AL,d,s,A_AM1_LSL,0)
447
448#define emith_addf_r_r(d, s) \
449 EOP_ADD_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
450
451#define emith_subf_r_r(d, s) \
452 EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
453
454#define emith_adcf_r_r(d, s) \
455 EOP_ADC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
456
457#define emith_sbcf_r_r(d, s) \
458 EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
459
460#define emith_eorf_r_r(d, s) \
461 EOP_EOR_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
462
463#define emith_move_r_imm(r, imm) \
464 emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
465
466#define emith_add_r_imm(r, imm) \
467 emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
468
469#define emith_adc_r_imm(r, imm) \
470 emith_op_imm(A_COND_AL, 0, A_OP_ADC, r, imm)
471
472#define emith_sub_r_imm(r, imm) \
473 emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
474
475#define emith_bic_r_imm(r, imm) \
476 emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
477
478#define emith_and_r_imm(r, imm) \
479 emith_op_imm(A_COND_AL, 0, A_OP_AND, r, imm)
480
481#define emith_or_r_imm(r, imm) \
482 emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
483
484#define emith_eor_r_imm(r, imm) \
485 emith_op_imm(A_COND_AL, 0, A_OP_EOR, r, imm)
486
487// note: only use 8bit imm for these
488#define emith_tst_r_imm(r, imm) \
489 emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
490
491#define emith_cmp_r_imm(r, imm) { \
492 u32 op = A_OP_CMP, imm_ = imm; \
493 if (~imm_ < 0x100) { \
494 imm_ = ~imm_; \
495 op = A_OP_CMN; \
496 } \
497 emith_top_imm(A_COND_AL, op, r, imm); \
498}
499
500#define emith_subf_r_imm(r, imm) \
501 emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
502
503#define emith_move_r_imm_c(cond, r, imm) \
504 emith_op_imm(cond, 0, A_OP_MOV, r, imm)
505
506#define emith_add_r_imm_c(cond, r, imm) \
507 emith_op_imm(cond, 0, A_OP_ADD, r, imm)
508
509#define emith_sub_r_imm_c(cond, r, imm) \
510 emith_op_imm(cond, 0, A_OP_SUB, r, imm)
511
512#define emith_or_r_imm_c(cond, r, imm) \
513 emith_op_imm(cond, 0, A_OP_ORR, r, imm)
514
515#define emith_eor_r_imm_c(cond, r, imm) \
516 emith_op_imm(cond, 0, A_OP_EOR, r, imm)
517
518#define emith_bic_r_imm_c(cond, r, imm) \
519 emith_op_imm(cond, 0, A_OP_BIC, r, imm)
520
521#define emith_move_r_imm_s8(r, imm) { \
522 if ((imm) & 0x80) \
523 EOP_MVN_IMM(r, 0, ((imm) ^ 0xff)); \
524 else \
525 EOP_MOV_IMM(r, 0, imm); \
526}
527
528#define emith_and_r_r_imm(d, s, imm) \
529 emith_op_imm2(A_COND_AL, 0, A_OP_AND, d, s, imm)
530
531#define emith_add_r_r_imm(d, s, imm) \
532 emith_op_imm2(A_COND_AL, 0, A_OP_ADD, d, s, imm)
533
534#define emith_add_r_r_ptr_imm(d, s, imm) \
535 emith_add_r_r_imm(d, s, imm)
536
537#define emith_sub_r_r_imm(d, s, imm) \
538 emith_op_imm2(A_COND_AL, 0, A_OP_SUB, d, s, imm)
539
540#define emith_neg_r_r(d, s) \
541 EOP_RSB_IMM(d, s, 0, 0)
542
543#define emith_lsl(d, s, cnt) \
544 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
545
546#define emith_lsr(d, s, cnt) \
547 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
548
549#define emith_asr(d, s, cnt) \
550 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt)
551
552#define emith_ror_c(cond, d, s, cnt) \
553 EOP_MOV_REG(cond,0,d,s,A_AM1_ROR,cnt)
554
555#define emith_ror(d, s, cnt) \
556 emith_ror_c(A_COND_AL, d, s, cnt)
557
558#define emith_rol(d, s, cnt) \
559 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \
560
561#define emith_lslf(d, s, cnt) \
562 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
563
564#define emith_lsrf(d, s, cnt) \
565 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSR,cnt)
566
567#define emith_asrf(d, s, cnt) \
568 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
569
570// note: only C flag updated correctly
571#define emith_rolf(d, s, cnt) { \
572 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,32-(cnt)); \
573 /* we don't have ROL so we shift to get the right carry */ \
574 EOP_TST_REG(A_COND_AL,d,d,A_AM1_LSR,1); \
575}
576
577#define emith_rorf(d, s, cnt) \
578 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,cnt)
579
580#define emith_rolcf(d) \
581 emith_adcf_r_r(d, d)
582
583#define emith_rorcf(d) \
584 EOP_MOV_REG(A_COND_AL,1,d,d,A_AM1_ROR,0) /* ROR #0 -> RRX */
585
586#define emith_negcf_r_r(d, s) \
587 EOP_C_DOP_IMM(A_COND_AL,A_OP_RSC,1,s,d,0,0)
588
589#define emith_mul(d, s1, s2) { \
590 if ((d) != (s1)) /* rd != rm limitation */ \
591 EOP_MUL(d, s1, s2); \
592 else \
593 EOP_MUL(d, s2, s1); \
594}
595
596#define emith_mul_u64(dlo, dhi, s1, s2) \
597 EOP_C_UMULL(A_COND_AL,0,dhi,dlo,s1,s2)
598
599#define emith_mul_s64(dlo, dhi, s1, s2) \
600 EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
601
602#define emith_mula_s64(dlo, dhi, s1, s2) \
603 EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
604
605// misc
606#define emith_read_r_r_offs_c(cond, r, rs, offs) \
607 EOP_LDR_IMM2(cond, r, rs, offs)
608
609#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
610 EOP_LDRB_IMM2(cond, r, rs, offs)
611
612#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
613 EOP_LDRH_IMM2(cond, r, rs, offs)
614
615#define emith_read_r_r_offs(r, rs, offs) \
616 emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
617
618#define emith_read8_r_r_offs(r, rs, offs) \
619 emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs)
620
621#define emith_read16_r_r_offs(r, rs, offs) \
622 emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs)
623
624#define emith_ctx_read(r, offs) \
625 emith_read_r_r_offs(r, CONTEXT_REG, offs)
626
627#define emith_ctx_read_ptr(r, offs) \
628 emith_ctx_read(r, offs)
629
630#define emith_ctx_write(r, offs) \
631 EOP_STR_IMM(r, CONTEXT_REG, offs)
632
633#define emith_ctx_do_multiple(op, r, offs, count, tmpr) do { \
634 int v_, r_ = r, c_ = count, b_ = CONTEXT_REG; \
635 for (v_ = 0; c_; c_--, r_++) \
636 v_ |= 1 << r_; \
637 if ((offs) != 0) { \
638 EOP_ADD_IMM(tmpr,CONTEXT_REG,30/2,(offs)>>2);\
639 b_ = tmpr; \
640 } \
641 op(b_,v_); \
642} while(0)
643
644#define emith_ctx_read_multiple(r, offs, count, tmpr) \
645 emith_ctx_do_multiple(EOP_LDMIA, r, offs, count, tmpr)
646
647#define emith_ctx_write_multiple(r, offs, count, tmpr) \
648 emith_ctx_do_multiple(EOP_STMIA, r, offs, count, tmpr)
649
650#define emith_clear_msb_c(cond, d, s, count) { \
651 u32 t; \
652 if ((count) <= 8) { \
653 t = (count) - 8; \
654 t = (0xff << t) & 0xff; \
655 EOP_BIC_IMM(d,s,8/2,t); \
656 EOP_C_DOP_IMM(cond,A_OP_BIC,0,s,d,8/2,t); \
657 } else if ((count) >= 24) { \
658 t = (count) - 24; \
659 t = 0xff >> t; \
660 EOP_AND_IMM(d,s,0,t); \
661 EOP_C_DOP_IMM(cond,A_OP_AND,0,s,d,0,t); \
662 } else { \
663 EOP_MOV_REG(cond,0,d,s,A_AM1_LSL,count); \
664 EOP_MOV_REG(cond,0,d,d,A_AM1_LSR,count); \
665 } \
666}
667
668#define emith_clear_msb(d, s, count) \
669 emith_clear_msb_c(A_COND_AL, d, s, count)
670
671#define emith_sext(d, s, bits) { \
672 EOP_MOV_REG_LSL(d,s,32 - (bits)); \
673 EOP_MOV_REG_ASR(d,d,32 - (bits)); \
674}
675
676#define emith_do_caller_regs(mask, func) { \
677 u32 _reg_mask = (mask) & 0x500f; \
678 if (_reg_mask) { \
679 if (__builtin_parity(_reg_mask) == 1) \
680 _reg_mask |= 0x10; /* eabi align */ \
681 func(_reg_mask); \
682 } \
683}
684
685#define emith_save_caller_regs(mask) \
686 emith_do_caller_regs(mask, EOP_STMFD_SP)
687
688#define emith_restore_caller_regs(mask) \
689 emith_do_caller_regs(mask, EOP_LDMFD_SP)
690
691// upto 4 args
692#define emith_pass_arg_r(arg, reg) \
693 EOP_MOV_REG_SIMPLE(arg, reg)
694
695#define emith_pass_arg_imm(arg, imm) \
696 emith_move_r_imm(arg, imm)
697
698#define emith_jump(target) \
699 emith_jump_cond(A_COND_AL, target)
700
701#define emith_jump_patchable(target) \
702 emith_jump(target)
703
704#define emith_jump_cond(cond, target) \
705 emith_xbranch(cond, target, 0)
706
707#define emith_jump_cond_patchable(cond, target) \
708 emith_jump_cond(cond, target)
709
710#define emith_jump_patch(ptr, target) do { \
711 u32 *ptr_ = ptr; \
712 u32 val_ = (u32 *)(target) - ptr_ - 2; \
713 *ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \
714} while (0)
715
716#define emith_jump_at(ptr, target) { \
717 u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
718 EOP_C_B_PTR(ptr, A_COND_AL, 0, val_ & 0xffffff); \
719}
720
721#define emith_jump_reg_c(cond, r) \
722 EOP_C_BX(cond, r)
723
724#define emith_jump_reg(r) \
725 emith_jump_reg_c(A_COND_AL, r)
726
727#define emith_jump_ctx_c(cond, offs) \
728 EOP_LDR_IMM2(cond,15,CONTEXT_REG,offs)
729
730#define emith_jump_ctx(offs) \
731 emith_jump_ctx_c(A_COND_AL, offs)
732
733#define emith_call_cond(cond, target) \
734 emith_xbranch(cond, target, 1)
735
736#define emith_call(target) \
737 emith_call_cond(A_COND_AL, target)
738
739#define emith_call_ctx(offs) { \
740 emith_move_r_r(14, 15); \
741 emith_jump_ctx(offs); \
742}
743
744#define emith_ret_c(cond) \
745 emith_jump_reg_c(cond, 14)
746
747#define emith_ret() \
748 emith_ret_c(A_COND_AL)
749
750#define emith_ret_to_ctx(offs) \
751 emith_ctx_write(14, offs)
752
753#define emith_push_ret() \
754 EOP_STMFD_SP(A_R14M)
755
756#define emith_pop_and_ret() \
757 EOP_LDMFD_SP(A_R15M)
758
759#define host_instructions_updated(base, end) \
760 cache_flush_d_inval_i(base, end)
761
762#define host_arg2reg(rd, arg) \
763 rd = arg
764
765/* SH2 drc specific */
766/* pushes r12 for eabi alignment */
767#define emith_sh2_drc_entry() \
768 EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R14M)
769
770#define emith_sh2_drc_exit() \
771 EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R15M)
772
773#define emith_sh2_wcall(a, tab) { \
774 emith_lsr(12, a, SH2_WRITE_SHIFT); \
775 EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \
776 emith_move_r_r(2, CONTEXT_REG); \
777 emith_jump_reg(12); \
778}
779
780#define emith_sh2_dtbf_loop() { \
781 int cr, rn; \
782 int tmp_ = rcache_get_tmp(); \
783 cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
784 rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW); \
785 emith_sub_r_imm(rn, 1); /* sub rn, #1 */ \
786 emith_bic_r_imm(cr, 1); /* bic cr, #1 */ \
787 emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
788 cycles = 0; \
789 emith_asrf(tmp_, cr, 2+12); /* movs tmp_, cr, asr #2+12 */\
790 EOP_MOV_IMM_C(A_COND_MI,tmp_,0,0); /* movmi tmp_, #0 */ \
791 emith_lsl(cr, cr, 20); /* mov cr, cr, lsl #20 */ \
792 emith_lsr(cr, cr, 20); /* mov cr, cr, lsr #20 */ \
793 emith_subf_r_r(rn, tmp_); /* subs rn, tmp_ */ \
794 EOP_RSB_IMM_C(A_COND_LS,tmp_,rn,0,0); /* rsbls tmp_, rn, #0 */ \
795 EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp_,A_AM1_LSL,12+2); /* orrls cr,tmp_,lsl #12+2 */\
796 EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1); /* orrls cr, #1 */ \
797 EOP_MOV_IMM_C(A_COND_LS,rn,0,0); /* movls rn, #0 */ \
798 rcache_free_tmp(tmp_); \
799}
800
801#define emith_write_sr(sr, srcr) { \
802 emith_lsr(sr, sr, 10); \
803 emith_or_r_r_r_lsl(sr, sr, srcr, 22); \
804 emith_ror(sr, sr, 22); \
805}
806
807#define emith_carry_to_t(srr, is_sub) { \
808 if (is_sub) { /* has inverted C on ARM */ \
809 emith_or_r_imm_c(A_COND_CC, srr, 1); \
810 emith_bic_r_imm_c(A_COND_CS, srr, 1); \
811 } else { \
812 emith_or_r_imm_c(A_COND_CS, srr, 1); \
813 emith_bic_r_imm_c(A_COND_CC, srr, 1); \
814 } \
815}
816
817#define emith_tpop_carry(sr, is_sub) { \
818 if (is_sub) \
819 emith_eor_r_imm(sr, 1); \
820 emith_lsrf(sr, sr, 1); \
821}
822
823#define emith_tpush_carry(sr, is_sub) { \
824 emith_adc_r_r(sr, sr); \
825 if (is_sub) \
826 emith_eor_r_imm(sr, 1); \
827}
828
829/*
830 * if Q
831 * t = carry(Rn += Rm)
832 * else
833 * t = carry(Rn -= Rm)
834 * T ^= t
835 */
836#define emith_sh2_div1_step(rn, rm, sr) { \
837 void *jmp0, *jmp1; \
838 emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
839 JMP_POS(jmp0); /* beq do_sub */ \
840 emith_addf_r_r(rn, rm); \
841 emith_eor_r_imm_c(A_COND_CS, sr, T); \
842 JMP_POS(jmp1); /* b done */ \
843 JMP_EMIT(A_COND_EQ, jmp0); /* do_sub: */ \
844 emith_subf_r_r(rn, rm); \
845 emith_eor_r_imm_c(A_COND_CC, sr, T); \
846 JMP_EMIT(A_COND_AL, jmp1); /* done: */ \
847}
848
fast MegaDrive/MegaCD/32X emulator