PicoLoadStateHook = NULL;\r
carthw_chunks = NULL;\r
\r
- PicoMemReset();\r
-\r
if (!(PicoAHW & (PAHW_MCD|PAHW_SMS)))\r
PicoCartDetect();\r
\r
// setup correct memory map for loaded ROM\r
- // call PicoMemReset again due to possible memmap change\r
switch (PicoAHW) {\r
default:\r
elprintf(EL_STATUS|EL_ANOMALY, "starting in unknown hw configuration: %x", PicoAHW);\r
case PAHW_PICO: PicoMemSetupPico(); break;\r
case PAHW_SMS: PicoMemSetupMS(); break;\r
}\r
- PicoMemReset();\r
\r
if (PicoAHW & PAHW_SMS)\r
PicoPowerMS();\r
return rom_strcmp(0x150, name);\r
}\r
\r
+static unsigned int rom_read32(int addr)\r
+{\r
+ unsigned short *m = (unsigned short *)(Pico.rom + addr);\r
+ return (m[0] << 16) | m[1];\r
+}\r
+\r
/*\r
* various cart-specific things, which can't be handled by generic code\r
* (maybe I should start using CRC for this stuff?)\r
static void PicoCartDetect(void)\r
{\r
int sram_size = 0, csum;\r
- Pico.m.sram_reg = 0;\r
+ Pico.m.sram_status = 0;\r
\r
- csum = PicoRead32(0x18c) & 0xffff;\r
+ csum = rom_read32(0x18c) & 0xffff;\r
\r
if (Pico.rom[0x1B1] == 'R' && Pico.rom[0x1B0] == 'A')\r
{\r
if (Pico.rom[0x1B2] & 0x40)\r
{\r
// EEPROM\r
- SRam.start = PicoRead32(0x1B4) & ~1; // zero address is used for clock by some games\r
- SRam.end = PicoRead32(0x1B8);\r
+ SRam.start = rom_read32(0x1B4) & ~1; // zero address is used for clock by some games\r
+ SRam.end = rom_read32(0x1B8);\r
sram_size = 0x2000;\r
- Pico.m.sram_reg |= 4;\r
+ Pico.m.sram_status |= SRS_EEPROM;\r
} else {\r
// normal SRAM\r
- SRam.start = PicoRead32(0x1B4) & ~0xff;\r
- SRam.end = PicoRead32(0x1B8) | 1;\r
+ SRam.start = rom_read32(0x1B4) & ~0xff;\r
+ SRam.end = rom_read32(0x1B8) | 1;\r
sram_size = SRam.end - SRam.start + 1;\r
}\r
SRam.start &= ~0xff000000;\r
SRam.end &= ~0xff000000;\r
- Pico.m.sram_reg |= 0x10; // SRAM was detected\r
+ Pico.m.sram_status |= SRS_DETECTED;\r
}\r
if (sram_size <= 0)\r
{\r
name_cmp("RINGS OF POWER") == 0)\r
{\r
SRam.start = SRam.end = 0x200000;\r
- Pico.m.sram_reg = 0x14;\r
+ Pico.m.sram_status = SRS_DETECTED|SRS_EEPROM;\r
SRam.eeprom_abits = 0;\r
SRam.eeprom_bit_cl = 6;\r
SRam.eeprom_bit_in = 7;\r
{\r
SRam.start = 0x300000;\r
SRam.end = 0x380001;\r
- Pico.m.sram_reg = 0x14;\r
+ Pico.m.sram_status = SRS_DETECTED|SRS_EEPROM;\r
SRam.eeprom_type = 2;\r
SRam.eeprom_abits = 0;\r
SRam.eeprom_bit_cl = 1;\r