{\r
u32 d = 0;\r
if (a == 0x400001) {\r
- if (SRam.data != NULL)\r
+ if (Pico.sv.data != NULL)\r
d = 3; // 64k cart\r
return d;\r
}\r
\r
if ((a & 0xfe0000) == 0x600000) {\r
- if (SRam.data != NULL)\r
- d = SRam.data[((a >> 1) & 0xffff) + 0x2000];\r
+ if (Pico.sv.data != NULL)\r
+ d = Pico.sv.data[((a >> 1) & 0xffff) + 0x2000];\r
return d;\r
}\r
\r
static void PicoWriteM68k8_ramc(u32 a, u32 d)\r
{\r
if ((a & 0xfe0000) == 0x600000) {\r
- if (SRam.data != NULL && (Pico_mcd->m.bcram_reg & 1)) {\r
- SRam.data[((a>>1) & 0xffff) + 0x2000] = d;\r
- SRam.changed = 1;\r
+ if (Pico.sv.data != NULL && (Pico_mcd->m.bcram_reg & 1)) {\r
+ Pico.sv.data[((a>>1) & 0xffff) + 0x2000] = d;\r
+ Pico.sv.changed = 1;\r
}\r
return;\r
}\r
static void PicoWriteS68k8_bram(u32 a, u32 d)\r
{\r
Pico_mcd->bram[(a >> 1) & 0x1fff] = d;\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
\r
static void PicoWriteS68k16_bram(u32 a, u32 d)\r
a = (a >> 1) & 0x1fff;\r
Pico_mcd->bram[a++] = d;\r
Pico_mcd->bram[a++] = d >> 8; // TODO: verify..\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
\r
// main68k map (BIOS mapped by PicoMemSetup()):\r
// RAM cart\r
- if (PicoOpt & POPT_EN_MCD_RAMCART) {\r
+ if (PicoIn.opt & POPT_EN_MCD_RAMCART) {\r
cpu68k_map_set(m68k_read8_map, 0x400000, 0x7fffff, PicoReadM68k8_ramc, 1);\r
cpu68k_map_set(m68k_read16_map, 0x400000, 0x7fffff, PicoReadM68k16_ramc, 1);\r
cpu68k_map_set(m68k_write8_map, 0x400000, 0x7fffff, PicoWriteM68k8_ramc, 1);\r
\r
// setup FAME fetchmap\r
{\r
+#ifdef __clang__\r
+ volatile // prevent strange relocs from clang\r
+#endif\r
+ unsigned long ptr_ram = (unsigned long)PicoMem.ram;\r
int i;\r
+\r
// M68k\r
// by default, point everything to fitst 64k of ROM (BIOS)\r
for (i = 0; i < M68K_FETCHBANK1; i++)\r
PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom;\r
// .. and RAM\r
for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
- PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
+ PicoCpuFM68k.Fetch[i] = ptr_ram - (i<<(24-FAMEC_FETCHBITS));\r
// S68k\r
// PRG RAM is default\r
for (i = 0; i < M68K_FETCHBANK1; i++)\r