// This is part of Pico Library\r
\r
// (c) Copyright 2004 Dave, All rights reserved.\r
-// (c) Copyright 2006,2007 notaz, All rights reserved.\r
+// (c) Copyright 2006-2009 notaz, All rights reserved.\r
// Free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
\r
\r
#include "pico_int.h"\r
+#include "memory.h"\r
\r
#include "sound/ym2612.h"\r
#include "sound/sn76496.h"\r
\r
-#ifndef UTYPES_DEFINED\r
-typedef unsigned char u8;\r
-typedef unsigned short u16;\r
-typedef unsigned int u32;\r
-#define UTYPES_DEFINED\r
-#endif\r
-\r
extern unsigned int lastSSRamWrite; // used by serial eeprom code\r
\r
-#ifdef _ASM_MEMORY_C\r
-u32 PicoRead8(u32 a);\r
-u32 PicoRead16(u32 a);\r
-void PicoWrite8(u32 a,u8 d);\r
-void PicoWriteRomHW_SSF2(u32 a,u32 d);\r
-#endif\r
+unsigned long m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];\r
+unsigned long m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
+unsigned long m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
+unsigned long m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
+\r
+static void xmap_set(unsigned long *map, int shift, int start_addr, int end_addr,\r
+ void *func_or_mh, int is_func)\r
+{\r
+ unsigned long addr = (unsigned long)func_or_mh;\r
+ int mask = (1 << shift) - 1;\r
+ int i;\r
+\r
+ if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {\r
+ elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",\r
+ start_addr, end_addr);\r
+ return;\r
+ }\r
+\r
+ if (addr & 1) {\r
+ elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);\r
+ return;\r
+ }\r
+\r
+ if (!is_func)\r
+ addr -= start_addr;\r
+\r
+ for (i = start_addr >> shift; i <= end_addr >> shift; i++) {\r
+ map[i] = addr >> 1;\r
+ if (is_func)\r
+ map[i] |= 1 << (sizeof(addr) * 8 - 1);\r
+ }\r
+}\r
+\r
+void z80_map_set(unsigned long *map, int start_addr, int end_addr,\r
+ void *func_or_mh, int is_func)\r
+{\r
+ xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
+}\r
+\r
+void cpu68k_map_set(unsigned long *map, int start_addr, int end_addr,\r
+ void *func_or_mh, int is_func)\r
+{\r
+ xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
+}\r
+\r
+// more specialized/optimized function (does same as above)\r
+void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)\r
+{\r
+ unsigned long *r8map, *r16map, *w8map, *w16map;\r
+ unsigned long addr = (unsigned long)ptr;\r
+ int shift = M68K_MEM_SHIFT;\r
+ int i;\r
+\r
+ if (!is_sub) {\r
+ r8map = m68k_read8_map;\r
+ r16map = m68k_read16_map;\r
+ w8map = m68k_write8_map;\r
+ w16map = m68k_write16_map;\r
+ } else {\r
+ r8map = s68k_read8_map;\r
+ r16map = s68k_read16_map;\r
+ w8map = s68k_write8_map;\r
+ w16map = s68k_write16_map;\r
+ }\r
+\r
+ addr -= start_addr;\r
+ addr >>= 1;\r
+ for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
+ r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;\r
+}\r
+\r
+static u32 m68k_unmapped_read8(u32 a)\r
+{\r
+ elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);\r
+ return 0; // assume pulldown, as if MegaCD2 was attached\r
+}\r
+\r
+static u32 m68k_unmapped_read16(u32 a)\r
+{\r
+ elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);\r
+ return 0;\r
+}\r
+\r
+static void m68k_unmapped_write8(u32 a, u32 d)\r
+{\r
+ elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
+}\r
+\r
+static void m68k_unmapped_write16(u32 a, u32 d)\r
+{\r
+ elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
+}\r
+\r
+void m68k_map_unmap(int start_addr, int end_addr)\r
+{\r
+ unsigned long addr;\r
+ int shift = M68K_MEM_SHIFT;\r
+ int i;\r
+\r
+ addr = (unsigned long)m68k_unmapped_read8;\r
+ for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
+ m68k_read8_map[i] = (addr >> 1) | (1 << 31);\r
+\r
+ addr = (unsigned long)m68k_unmapped_read16;\r
+ for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
+ m68k_read16_map[i] = (addr >> 1) | (1 << 31);\r
+\r
+ addr = (unsigned long)m68k_unmapped_write8;\r
+ for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
+ m68k_write8_map[i] = (addr >> 1) | (1 << 31);\r
+\r
+ addr = (unsigned long)m68k_unmapped_write16;\r
+ for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
+ m68k_write16_map[i] = (addr >> 1) | (1 << 31);\r
+}\r
+\r
+MAKE_68K_READ8(m68k_read8, m68k_read8_map)\r
+MAKE_68K_READ16(m68k_read16, m68k_read16_map)\r
+MAKE_68K_READ32(m68k_read32, m68k_read16_map)\r
+MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)\r
+MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)\r
+MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)\r
+\r
+// -----------------------------------------------------------------\r
+\r
+static u32 ym2612_read_local_68k(void);\r
+static int ym2612_write_local(u32 a, u32 d, int is_from_z80);\r
+static void z80_mem_setup(void);\r
\r
\r
#ifdef EMU_CORE_DEBUG\r
PicoCheckPc(pc);\r
}\r
\r
-#ifndef _ASM_MEMORY_C\r
-PICO_INTERNAL_ASM void PicoMemReset(void)\r
-{\r
-}\r
-#endif\r
-\r
// -----------------------------------------------------------------\r
+// memmap helpers\r
\r
-int PadRead(int i)\r
+static int PadRead(int i)\r
{\r
int pad,value,data_reg;\r
pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
return value; // will mirror later\r
}\r
\r
-\r
-#ifndef _ASM_MEMORY_C\r
-static\r
-#endif\r
-u32 SRAMRead(u32 a)\r
+static u32 io_ports_read(u32 a)\r
{\r
- unsigned int sreg = Pico.m.sram_reg;\r
- if (!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
- elprintf(EL_SRAMIO, "normal sram detected.");\r
- Pico.m.sram_reg|=0x10; // should be normal SRAM\r
+ u32 d;\r
+ a = (a>>1) & 0xf;\r
+ switch (a) {\r
+ case 0: d = Pico.m.hardware; break; // Hardware value (Version register)\r
+ case 1: d = PadRead(0); break;\r
+ case 2: d = PadRead(1); break;\r
+ default: d = Pico.ioports[a]; break; // IO ports can be used as RAM\r
}\r
- if (sreg & 4) // EEPROM read\r
- return SRAMReadEEPROM();\r
- else // if(sreg & 1) // (sreg&5) is one of prerequisites\r
- return *(u8 *)(SRam.data-SRam.start+a);\r
+ return d;\r
}\r
\r
-#ifndef _ASM_MEMORY_C\r
-static\r
-#endif\r
-u32 SRAMRead16(u32 a)\r
+static void io_ports_write(u32 a, u32 d)\r
{\r
- u32 d;\r
- if (Pico.m.sram_reg & 4) {\r
- d = SRAMReadEEPROM();\r
- d |= d << 8;\r
- } else {\r
- u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
- d =*pm++ << 8;\r
- d|=*pm++;\r
+ a = (a>>1) & 0xf;\r
+\r
+ // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
+ if (1 <= a && a <= 2 && (PicoOpt & POPT_6BTN_PAD))\r
+ {\r
+ Pico.m.padDelay[a - 1] = 0;\r
+ if (!(Pico.ioports[a] & 0x40) && (d & 0x40))\r
+ Pico.m.padTHPhase[a - 1]++;\r
}\r
- return d;\r
+\r
+ // cartain IO ports can be used as RAM\r
+ Pico.ioports[a] = d;\r
}\r
\r
-static void SRAMWrite(u32 a, u32 d)\r
+static void ctl_write_z80busreq(u32 d)\r
{\r
- unsigned int sreg = Pico.m.sram_reg;\r
- if(!(sreg & 0x10)) {\r
- // not detected SRAM\r
- if((a&~1)==0x200000) {\r
- elprintf(EL_SRAMIO, "eeprom detected.");\r
- sreg|=4; // this should be a game with EEPROM (like NBA Jam)\r
- SRam.start=0x200000; SRam.end=SRam.start+1;\r
- } else\r
- elprintf(EL_SRAMIO, "normal sram detected.");\r
- sreg|=0x10;\r
- Pico.m.sram_reg=sreg;\r
+ d&=1; d^=1;\r
+ elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);\r
+ if (d ^ Pico.m.z80Run)\r
+ {\r
+ if (d)\r
+ {\r
+ z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r
+ }\r
+ else\r
+ {\r
+ z80stopCycle = SekCyclesDone();\r
+ if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset)\r
+ PicoSyncZ80(z80stopCycle);\r
+ }\r
+ Pico.m.z80Run = d;\r
}\r
- if(sreg & 4) { // EEPROM write\r
- // this diff must be at most 16 for NBA Jam to work\r
- if(SekCyclesDoneT()-lastSSRamWrite < 16) {\r
- // just update pending state\r
- elprintf(EL_EEPROM, "eeprom: skip because cycles=%i", SekCyclesDoneT()-lastSSRamWrite);\r
- SRAMUpdPending(a, d);\r
- } else {\r
- int old=sreg;\r
- SRAMWriteEEPROM(sreg>>6); // execute pending\r
- SRAMUpdPending(a, d);\r
- if ((old^Pico.m.sram_reg)&0xc0) // update time only if SDA/SCL changed\r
- lastSSRamWrite = SekCyclesDoneT();\r
+}\r
+\r
+static void ctl_write_z80reset(u32 d)\r
+{\r
+ d&=1; d^=1;\r
+ elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);\r
+ if (d ^ Pico.m.z80_reset)\r
+ {\r
+ if (d)\r
+ {\r
+ if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run)\r
+ PicoSyncZ80(SekCyclesDone());\r
+ YM2612ResetChip();\r
+ timers_reset();\r
}\r
- } else if(!(sreg & 2)) {\r
- u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
- if(*pm != (u8)d) {\r
- SRam.changed = 1;\r
- *pm=(u8)d;\r
+ else\r
+ {\r
+ z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r
+ z80_reset();\r
}\r
+ Pico.m.z80_reset = d;\r
}\r
}\r
\r
+\r
// for nonstandard reads\r
+// TODO: mv to carthw\r
static u32 OtherRead16End(u32 a, int realsize)\r
{\r
u32 d=0;\r
return d;\r
}\r
\r
-\r
-//extern UINT32 mz80GetRegisterValue(void *, UINT32);\r
-\r
static void OtherWrite8End(u32 a,u32 d,int realsize)\r
{\r
- // sram\r
- if(a >= SRam.start && a <= SRam.end) {\r
- elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d, SekPc);\r
- SRAMWrite(a, d);\r
- return;\r
- }\r
-\r
#ifdef _ASM_MEMORY_C\r
// special ROM hardware (currently only banking and sram reg supported)\r
if((a&0xfffff1) == 0xA130F1) {\r
// sram access register\r
if(a == 0xA130F1) {\r
elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
- Pico.m.sram_reg &= ~3;\r
- Pico.m.sram_reg |= (u8)(d&3);\r
+ Pico.m.sram_status &= ~(SRS_MAPPED|SRS_READONLY);\r
+ Pico.m.sram_status |= (u8)(d&3);\r
return;\r
}\r
#endif\r
Pico.m.prot_bytes[(a>>2)&1] = (u8)d;\r
}\r
\r
-#include "memory_cmn.c"\r
+// -----------------------------------------------------------------\r
\r
+// cart (save) RAM area (usually 0x200000 - ...)\r
+static u32 PicoRead8_sram(u32 a)\r
+{\r
+ int srs = Pico.m.sram_status;\r
+ u32 d;\r
+ if (SRam.end >= a && a >= SRam.start && (srs & (SRS_MAPPED|SRS_EEPROM)))\r
+ {\r
+ if (srs & SRS_EEPROM)\r
+ d = EEPROM_read();\r
+ else\r
+ d = *(u8 *)(SRam.data - SRam.start + a);\r
+ elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
+ return d;\r
+ }\r
\r
-// -----------------------------------------------------------------\r
-// Read Rom and read Ram\r
+ if (a < Pico.romsize)\r
+ return Pico.rom[a ^ 1];\r
+ \r
+ return m68k_unmapped_read8(a);\r
+}\r
\r
-#ifndef _ASM_MEMORY_C\r
-PICO_INTERNAL_ASM u32 PicoRead8(u32 a)\r
+static u32 PicoRead16_sram(u32 a)\r
{\r
- u32 d=0;\r
+ int srs = Pico.m.sram_status;\r
+ u32 d;\r
+ if (SRam.end >= a && a >= SRam.start && (srs & (SRS_MAPPED|SRS_EEPROM)))\r
+ {\r
+ if (srs & SRS_EEPROM) {\r
+ d = EEPROM_read();\r
+ d |= d << 8;\r
+ } else {\r
+ u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
+ d = pm[0] << 8;\r
+ d |= pm[1];\r
+ }\r
+ elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
+ return d;\r
+ }\r
\r
- if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram\r
+ if (a < Pico.romsize)\r
+ return *(u16 *)(Pico.rom + a);\r
\r
- a&=0xffffff;\r
+ return m68k_unmapped_read16(a);\r
+}\r
\r
-#ifndef EMU_CORE_DEBUG\r
- // sram\r
- if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
- d = SRAMRead(a);\r
- elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
- goto end;\r
+static void PicoWrite8_sram(u32 a, u32 d)\r
+{\r
+ unsigned int srs = Pico.m.sram_status;\r
+ elprintf(EL_SRAMIO, "sram wX [%06x] %02x @ %06x", a, d & 0xffff, SekPc);\r
+ if (srs & SRS_EEPROM) // EEPROM write\r
+ {\r
+ // this diff must be at most 16 for NBA Jam to work\r
+ if (SekCyclesDoneT() - lastSSRamWrite < 16) {\r
+ // just update pending state\r
+ elprintf(EL_EEPROM, "eeprom: skip because cycles=%i",\r
+ SekCyclesDoneT() - lastSSRamWrite);\r
+ EEPROM_upd_pending(a, d);\r
+ } else {\r
+ EEPROM_write(srs >> 6); // execute pending\r
+ EEPROM_upd_pending(a, d);\r
+ if ((srs ^ Pico.m.sram_status) & 0xc0) // update time only if SDA/SCL changed\r
+ lastSSRamWrite = SekCyclesDoneT();\r
+ }\r
}\r
-#endif\r
+ else if (!(srs & SRS_READONLY)) {\r
+ u8 *pm=(u8 *)(SRam.data - SRam.start + a);\r
+ if (*pm != (u8)d) {\r
+ SRam.changed = 1;\r
+ *pm = (u8)d;\r
+ }\r
+ }\r
+}\r
\r
- if (a<Pico.romsize) { d = *(u8 *)(Pico.rom+(a^1)); goto end; } // Rom\r
- log_io(a, 8, 0);\r
- if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r
+static void PicoWrite16_sram(u32 a, u32 d)\r
+{\r
+ // XXX: hardware could easily use MSB too..\r
+ PicoWrite8_sram(a + 1, d);\r
+}\r
\r
- if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead8(a); goto end; } // VDP\r
+// z80 area (0xa00000 - 0xa0ffff)\r
+// TODO: verify mirrors VDP and bank reg (bank area mirroring verified)\r
+static u32 PicoRead8_z80(u32 a)\r
+{\r
+ u32 d = 0xff;\r
+ if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r
+ elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);\r
+ // open bus. Pulled down if MegaCD2 is attached.\r
+ return 0;\r
+ }\r
\r
- d=OtherRead16(a&~1, 8);\r
- if ((a&1)==0) d>>=8;\r
+ if ((a & 0x4000) == 0x0000)\r
+ d = Pico.zram[a & 0x1fff];\r
+ else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff\r
+ d = ym2612_read_local_68k(); \r
+ else\r
+ elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
+ return d;\r
+}\r
\r
-end:\r
- elprintf(EL_IO, "r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
-#ifdef EMU_CORE_DEBUG\r
- if (a>=Pico.romsize) {\r
- lastread_a = a;\r
- lastread_d[lrp_cyc++&15] = (u8)d;\r
+static u32 PicoRead16_z80(u32 a)\r
+{\r
+ u32 d = PicoRead8_z80(a);\r
+ return d | (d << 8);\r
+}\r
+\r
+static void PicoWrite8_z80(u32 a, u32 d)\r
+{\r
+ if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {\r
+ // verified on real hw\r
+ elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
+ return;\r
+ }\r
+\r
+ if ((a & 0x4000) == 0x0000) { // z80 RAM\r
+ SekCyclesBurn(2); // hack\r
+ Pico.zram[a & 0x1fff] = (u8)d;\r
+ return;\r
+ }\r
+ if ((a & 0x6000) == 0x4000) { // FM Sound\r
+ if (PicoOpt & POPT_EN_FM)\r
+ emustatus |= ym2612_write_local(a&3, d&0xff, 0)&1;\r
+ return;\r
+ }\r
+ // TODO: probably other VDP access too? Maybe more mirrors?\r
+ if ((a & 0x7ff9) == 0x7f11) { // PSG Sound\r
+ if (PicoOpt & POPT_EN_PSG)\r
+ SN76496Write(d);\r
+ return;\r
+ }\r
+#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)\r
+ if ((a & 0x7f00) == 0x6000) // Z80 BANK register\r
+ {\r
+ Pico.m.z80_bank68k >>= 1;\r
+ Pico.m.z80_bank68k |= d << 8;\r
+ Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one\r
+ elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);\r
+ return;\r
}\r
#endif\r
- return d;\r
+ elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
}\r
\r
-PICO_INTERNAL_ASM u32 PicoRead16(u32 a)\r
+static void PicoWrite16_z80(u32 a, u32 d)\r
{\r
- u32 d=0;\r
-\r
- if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram\r
+ // for RAM, only most significant byte is sent\r
+ // TODO: verify remaining accesses\r
+ PicoWrite8_z80(a, d >> 8);\r
+}\r
\r
- a&=0xfffffe;\r
+// IO/control area (0xa10000 - 0xa1ffff)\r
+u32 PicoRead8_io(u32 a)\r
+{\r
+ u32 d;\r
\r
-#ifndef EMU_CORE_DEBUG\r
- // sram\r
- if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
- d = SRAMRead16(a);\r
- elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
+ if ((a & 0xffe0) == 0x0000) { // I/O ports\r
+ d = io_ports_read(a);\r
goto end;\r
}\r
-#endif\r
\r
- if (a<Pico.romsize) { d = *(u16 *)(Pico.rom+a); goto end; } // Rom\r
- log_io(a, 16, 0);\r
+ // faking open bus (MegaCD pulldowns don't work here curiously)\r
+ d = Pico.m.rotate++;\r
+ d ^= d << 6;\r
\r
- if ((a&0xe700e0)==0xc00000)\r
- d = PicoVideoRead(a);\r
- else d = OtherRead16(a, 16);\r
+ // bit8 seems to be readable in this range\r
+ if ((a & 0xfc01) == 0x1000)\r
+ d &= ~0x01;\r
\r
-end:\r
- elprintf(EL_IO, "r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
-#ifdef EMU_CORE_DEBUG\r
- if (a>=Pico.romsize) {\r
- lastread_a = a;\r
- lastread_d[lrp_cyc++&15] = d;\r
+ if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)\r
+ d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;\r
+ elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
+ goto end;\r
}\r
-#endif\r
+\r
+ d = m68k_unmapped_read8(a);\r
+end:\r
return d;\r
}\r
\r
-PICO_INTERNAL_ASM u32 PicoRead32(u32 a)\r
+u32 PicoRead16_io(u32 a)\r
{\r
- u32 d=0;\r
-\r
- if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram\r
-\r
- a&=0xfffffe;\r
+ u32 d;\r
\r
- // sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
- d = (SRAMRead16(a)<<16)|SRAMRead16(a+2);\r
- elprintf(EL_SRAMIO, "sram r32 [%06x] %08x @ %06x", a, d, SekPc);\r
+ if ((a & 0xffe0) == 0x0000) { // I/O ports\r
+ d = io_ports_read(a);\r
goto end;\r
}\r
\r
- if (a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+a); d = (pm[0]<<16)|pm[1]; goto end; } // Rom\r
- log_io(a, 32, 0);\r
+ // faking open bus\r
+ d = (Pico.m.rotate += 0x41);\r
+ d ^= (d << 5) ^ (d << 8);\r
\r
- if ((a&0xe700e0)==0xc00000)\r
- d = (PicoVideoRead(a)<<16)|PicoVideoRead(a+2);\r
- else d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
+ // bit8 seems to be readable in this range\r
+ if ((a & 0xfc00) == 0x1000)\r
+ d &= ~0x0100;\r
\r
-end:\r
- elprintf(EL_IO, "r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
-#ifdef EMU_CORE_DEBUG\r
- if (a>=Pico.romsize) {\r
- lastread_a = a;\r
- lastread_d[lrp_cyc++&15] = d;\r
+ if ((a & 0xff00) == 0x1100) { // z80 busreq\r
+ d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;\r
+ elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
+ goto end;\r
}\r
-#endif\r
+\r
+ d = m68k_unmapped_read16(a);\r
+end:\r
return d;\r
}\r
-#endif\r
\r
-// -----------------------------------------------------------------\r
-// Write Ram\r
+void PicoWrite8_io(u32 a, u32 d)\r
+{\r
+ if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)\r
+ io_ports_write(a, d);\r
+ return;\r
+ }\r
+ if ((a & 0xff01) == 0x1100) { // z80 busreq\r
+ ctl_write_z80busreq(d);\r
+ return;\r
+ }\r
+ if ((a & 0xff01) == 0x1200) { // z80 reset\r
+ ctl_write_z80reset(d);\r
+ return;\r
+ }\r
+ if (a == 0xa130f1) { // sram access register\r
+ elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
+ Pico.m.sram_status &= ~(SRS_MAPPED|SRS_READONLY);\r
+ Pico.m.sram_status |= (u8)(d & 3);\r
+ return;\r
+ }\r
+ m68k_unmapped_write8(a, d);\r
+}\r
\r
-#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)\r
-PICO_INTERNAL_ASM void PicoWrite8(u32 a,u8 d)\r
+void PicoWrite16_io(u32 a, u32 d)\r
{\r
- elprintf(EL_IO, "w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
-#ifdef EMU_CORE_DEBUG\r
- lastwrite_cyc_d[lwp_cyc++&15] = d;\r
-#endif\r
+ if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)\r
+ io_ports_write(a, d);\r
+ return;\r
+ }\r
+ if ((a & 0xff00) == 0x1100) { // z80 busreq\r
+ ctl_write_z80busreq(d >> 8);\r
+ return;\r
+ }\r
+ if ((a & 0xff00) == 0x1200) { // z80 reset\r
+ ctl_write_z80reset(d >> 8);\r
+ return;\r
+ }\r
+ if (a == 0xa130f0) { // sram access register\r
+ elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
+ Pico.m.sram_status &= ~(SRS_MAPPED|SRS_READONLY);\r
+ Pico.m.sram_status |= (u8)(d & 3);\r
+ return;\r
+ }\r
+ m68k_unmapped_write16(a, d);\r
+}\r
\r
- if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram\r
- log_io(a, 8, 1);\r
+// VDP area (0xc00000 - 0xdfffff)\r
+// TODO: verify if lower byte goes to PSG on word writes\r
+static u32 PicoRead8_vdp(u32 a)\r
+{\r
+ if ((a & 0x00e0) == 0x0000)\r
+ return PicoVideoRead8(a);\r
\r
- a&=0xffffff;\r
- OtherWrite8(a,d);\r
+ elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
+ return 0;\r
}\r
-#endif\r
\r
-void PicoWrite16(u32 a,u16 d)\r
+static u32 PicoRead16_vdp(u32 a)\r
{\r
- elprintf(EL_IO, "w16: %06x, %04x", a&0xffffff, d);\r
-#ifdef EMU_CORE_DEBUG\r
- lastwrite_cyc_d[lwp_cyc++&15] = d;\r
-#endif\r
-\r
- if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram\r
- log_io(a, 16, 1);\r
+ if ((a & 0x00e0) == 0x0000)\r
+ return PicoVideoRead(a);\r
\r
- a&=0xfffffe;\r
- if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; } // VDP\r
- OtherWrite16(a,d);\r
+ elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);\r
+ return 0;\r
}\r
\r
-static void PicoWrite32(u32 a,u32 d)\r
+static void PicoWrite8_vdp(u32 a, u32 d)\r
{\r
- elprintf(EL_IO, "w32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
-#ifdef EMU_CORE_DEBUG\r
- lastwrite_cyc_d[lwp_cyc++&15] = d;\r
-#endif\r
-\r
- if ((a&0xe00000)==0xe00000)\r
- {\r
- // Ram:\r
- u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r
- pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
+ if ((a & 0x00f9) == 0x0011) { // PSG Sound\r
+ if (PicoOpt & POPT_EN_PSG)\r
+ SN76496Write(d);\r
return;\r
}\r
- log_io(a, 32, 1);\r
-\r
- a&=0xfffffe;\r
- if ((a&0xe700e0)==0xc00000)\r
- {\r
- // VDP:\r
- PicoVideoWrite(a, (u16)(d>>16));\r
- PicoVideoWrite(a+2,(u16)d);\r
+ if ((a & 0x00e0) == 0x0000) {\r
+ d &= 0xff;\r
+ PicoVideoWrite(a, d | (d << 8));\r
return;\r
}\r
\r
- OtherWrite16(a, (u16)(d>>16));\r
- OtherWrite16(a+2,(u16)d);\r
+ elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
}\r
\r
+static void PicoWrite16_vdp(u32 a, u32 d)\r
+{\r
+ if ((a & 0x00f9) == 0x0010) { // PSG Sound\r
+ if (PicoOpt & POPT_EN_PSG)\r
+ SN76496Write(d);\r
+ return;\r
+ }\r
+ if ((a & 0x00e0) == 0x0000) {\r
+ PicoVideoWrite(a, d);\r
+ return;\r
+ }\r
+\r
+ elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
+}\r
\r
// -----------------------------------------------------------------\r
\r
+// TODO: rm\r
static void OtherWrite16End(u32 a,u32 d,int realsize)\r
{\r
PicoWrite8Hook(a, d>>8, realsize);\r
\r
PICO_INTERNAL void PicoMemSetup(void)\r
{\r
+ int mask, rs, a;\r
+\r
+ // setup the memory map\r
+ cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);\r
+ cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);\r
+ cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);\r
+ cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);\r
+\r
+ // ROM\r
+ // align to bank size. We know ROM loader allocated enough for this\r
+ mask = (1 << M68K_MEM_SHIFT) - 1;\r
+ rs = (Pico.romsize + mask) & ~mask;\r
+ cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);\r
+ cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);\r
+\r
+ // Common case of on-cart (save) RAM, usually at 0x200000-...\r
+ rs = SRam.end - SRam.start;\r
+ if (rs > 0 && SRam.data != NULL) {\r
+ rs = (rs + mask) & ~mask;\r
+ if (SRam.start + rs >= 0x1000000)\r
+ rs = 0x1000000 - SRam.start;\r
+ cpu68k_map_set(m68k_read8_map, SRam.start, SRam.start + rs - 1, PicoRead8_sram, 1);\r
+ cpu68k_map_set(m68k_read16_map, SRam.start, SRam.start + rs - 1, PicoRead16_sram, 1);\r
+ cpu68k_map_set(m68k_write8_map, SRam.start, SRam.start + rs - 1, PicoWrite8_sram, 1);\r
+ cpu68k_map_set(m68k_write16_map, SRam.start, SRam.start + rs - 1, PicoWrite16_sram, 1);\r
+ }\r
+\r
+ // Z80 region\r
+ cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);\r
+ cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);\r
+ cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);\r
+ cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);\r
+\r
+ // IO/control region\r
+ cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);\r
+ cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);\r
+ cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);\r
+ cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);\r
+\r
+ // VDP region\r
+ for (a = 0xc00000; a < 0xe00000; a += 0x010000) {\r
+ if ((a & 0xe700e0) != 0xc00000)\r
+ continue;\r
+ cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);\r
+ cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);\r
+ cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);\r
+ cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);\r
+ }\r
+\r
+ // RAM and it's mirrors\r
+ for (a = 0xe00000; a < 0x1000000; a += 0x010000) {\r
+ cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.ram, 0);\r
+ cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.ram, 0);\r
+ cpu68k_map_set(m68k_write8_map, a, a + 0xffff, Pico.ram, 0);\r
+ cpu68k_map_set(m68k_write16_map, a, a + 0xffff, Pico.ram, 0);\r
+ }\r
+\r
// Setup memory callbacks:\r
#ifdef EMU_C68K\r
- PicoCpuCM68k.checkpc=PicoCheckPc;\r
- PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoRead8;\r
- PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoRead16;\r
- PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoRead32;\r
- PicoCpuCM68k.write8 =PicoWrite8;\r
- PicoCpuCM68k.write16=PicoWrite16;\r
- PicoCpuCM68k.write32=PicoWrite32;\r
+ PicoCpuCM68k.checkpc = PicoCheckPc;\r
+ PicoCpuCM68k.fetch8 = PicoCpuCM68k.read8 = m68k_read8;\r
+ PicoCpuCM68k.fetch16 = PicoCpuCM68k.read16 = m68k_read16;\r
+ PicoCpuCM68k.fetch32 = PicoCpuCM68k.read32 = m68k_read32;\r
+ PicoCpuCM68k.write8 = m68k_write8;\r
+ PicoCpuCM68k.write16 = m68k_write16;\r
+ PicoCpuCM68k.write32 = m68k_write32;\r
#endif\r
#ifdef EMU_F68K\r
- PicoCpuFM68k.read_byte =PicoRead8;\r
- PicoCpuFM68k.read_word =PicoRead16;\r
- PicoCpuFM68k.read_long =PicoRead32;\r
- PicoCpuFM68k.write_byte=PicoWrite8;\r
- PicoCpuFM68k.write_word=PicoWrite16;\r
- PicoCpuFM68k.write_long=PicoWrite32;\r
+ PicoCpuFM68k.read_byte = m68k_read8;\r
+ PicoCpuFM68k.read_word = m68k_read16;\r
+ PicoCpuFM68k.read_long = m68k_read32;\r
+ PicoCpuFM68k.write_byte = m68k_write8;\r
+ PicoCpuFM68k.write_word = m68k_write16;\r
+ PicoCpuFM68k.write_long = m68k_write32;\r
\r
// setup FAME fetchmap\r
{\r
\r
static void m68k_mem_setup(void)\r
{\r
- pm68k_read_memory_8 = PicoRead8;\r
- pm68k_read_memory_16 = PicoRead16;\r
- pm68k_read_memory_32 = PicoRead32;\r
- pm68k_write_memory_8 = PicoWrite8;\r
- pm68k_write_memory_16 = PicoWrite16;\r
- pm68k_write_memory_32 = PicoWrite32;\r
+ pm68k_read_memory_8 = m68k_read8;\r
+ pm68k_read_memory_16 = m68k_read16;\r
+ pm68k_read_memory_32 = m68k_read32;\r
+ pm68k_write_memory_8 = m68k_write8;\r
+ pm68k_write_memory_16 = m68k_write16;\r
+ pm68k_write_memory_32 = m68k_write32;\r
pm68k_read_memory_pcr_8 = m68k_read_memory_pcr_8;\r
pm68k_read_memory_pcr_16 = m68k_read_memory_pcr_16;\r
pm68k_read_memory_pcr_32 = m68k_read_memory_pcr_32;\r
}\r
\r
// ym2612 DAC and timer I/O handlers for z80\r
-int ym2612_write_local(u32 a, u32 d, int is_from_z80)\r
+static int ym2612_write_local(u32 a, u32 d, int is_from_z80)\r
{\r
int addr;\r
\r
return ym2612.OPN.ST.status;\r
}\r
\r
-u32 ym2612_read_local_68k(void)\r
+static u32 ym2612_read_local_68k(void)\r
{\r
int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;\r
\r
goto out;\r
}\r
\r
+ ret = m68k_read8(addr68k);\r
elprintf(EL_ANOMALY, "z80->68k upper read [%06x] %02x", addr68k, ret);\r
- if (PicoAHW & PAHW_MCD)\r
- ret = PicoReadM68k8(addr68k);\r
- else ret = PicoRead8(addr68k);\r
\r
out:\r
elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
addr68k += a & 0x7fff;\r
\r
elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
- if (PicoAHW & PAHW_MCD)\r
- PicoWriteM68k8(addr68k, data);\r
- else PicoWrite8(addr68k, data);\r
+ m68k_write8(addr68k, data);\r
}\r
\r
// -----------------------------------------------------------------\r
elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);\r
}\r
\r
-void z80_mem_setup(void)\r
+static void z80_mem_setup(void)\r
{\r
z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);\r
z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);\r
notaz.gp2x.de / picodrive.git / blobdiff