new memory handling, but asm and mappers need update.

[picodrive.git] / pico / misc.c

diff --git a/pico/misc.c b/pico/misc.c
index 014ffa1..0ce1489 100644 (file)
--- a/pico/misc.c
+++ b/pico/misc.c
@@ -95,11 +95,11 @@ const unsigned char hcounts_32[] = {
 \r
 unsigned int lastSSRamWrite = 0xffff0000;\r
 \r
-// sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=(unused),\r
+// sram_status: LAtd sela (L=pending SCL, A=pending SDA, t=(unused),\r
 //                      d=SRAM was detected (header or by access), s=started, e=save is EEPROM, l=old SCL, a=old SDA)\r
-PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)\r
+PICO_INTERNAL void EEPROM_write(unsigned int d) // ???? ??la (l=SCL, a=SDA)\r
 {\r
-  unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.eeprom_addr, scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;\r
+  unsigned int sreg = Pico.m.sram_status, saddr = Pico.m.eeprom_addr, scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;\r
 \r
   elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,\r
     (d&2)>>1, d&1, SekCyclesDoneT()-lastSSRamWrite);\r
@@ -197,21 +197,21 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
   }\r
 \r
   sreg &= ~3; sreg |= d&3; // remember SCL and SDA\r
-  Pico.m.sram_reg    = (unsigned char) sreg;\r
+  Pico.m.sram_status    = (unsigned char) sreg;\r
   Pico.m.eeprom_cycle= (unsigned char) scyc;\r
   Pico.m.eeprom_slave= (unsigned char) ssa;\r
   Pico.m.eeprom_addr = (unsigned short)saddr;\r
 }\r
 \r
-PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)\r
+PICO_INTERNAL_ASM unsigned int EEPROM_read(void)\r
 {\r
   unsigned int shift, d;\r
   unsigned int sreg, saddr, scyc, ssa, interval;\r
 \r
   // flush last pending write\r
-  SRAMWriteEEPROM(Pico.m.sram_reg>>6);\r
+  EEPROM_write(Pico.m.sram_status>>6);\r
 \r
-  sreg = Pico.m.sram_reg; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;\r
+  sreg = Pico.m.sram_status; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;\r
   interval = SekCyclesDoneT()-lastSSRamWrite;\r
   d = (sreg>>6)&1; // use SDA as "open bus"\r
 \r
@@ -250,9 +250,9 @@ PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)
   return (d << SRam.eeprom_bit_out);\r
 }\r
 \r
-PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d)\r
+PICO_INTERNAL void EEPROM_upd_pending(unsigned int a, unsigned int d)\r
 {\r
-  unsigned int d1, sreg = Pico.m.sram_reg;\r
+  unsigned int d1, sreg = Pico.m.sram_status;\r
 \r
   if (!((SRam.eeprom_abits^a)&1))\r
   {\r
@@ -269,7 +269,7 @@ PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d)
     sreg |= d1<<6;\r
   }\r
 \r
-  Pico.m.sram_reg = (unsigned char) sreg;\r
+  Pico.m.sram_status = (unsigned char) sreg;\r
 }\r
 \r
 \r