-// Pico Library - Internal Header File\r
-\r
-// (c) Copyright 2004 Dave, All rights reserved.\r
-// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r
-// Free for non-commercial use.\r
-\r
-// For commercial use, separate licencing terms must be obtained.\r
+/*\r
+ * PicoDrive - Internal Header File\r
+ * (c) Copyright Dave, 2004\r
+ * (C) notaz, 2006-2010\r
+ *\r
+ * This work is licensed under the terms of MAME license.\r
+ * See COPYING file in the top-level directory.\r
+ */\r
\r
#ifndef PICO_INTERNAL_INCLUDED\r
#define PICO_INTERNAL_INCLUDED\r
\r
// ----------------------- 68000 CPU -----------------------\r
#ifdef EMU_C68K\r
-#include "../cpu/Cyclone/Cyclone.h"\r
+#include "../cpu/cyclone/Cyclone.h"\r
extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
-#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
-#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
-#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
+#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
+#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
+#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
+#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
+#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
+#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
+#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
-#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
+#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
+\r
+#define SekNotPolling PicoCpuCM68k.not_pol\r
+#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
\r
#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
+#define SekIrqLevel PicoCpuCM68k.irq\r
\r
-#ifdef EMU_M68K\r
-#define EMU_CORE_DEBUG\r
-#endif\r
#endif\r
\r
#ifdef EMU_F68K\r
#include "../cpu/fame/fame.h"\r
extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
-#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
-#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
-#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
+#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
+#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
+#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
+#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
+#define SekSr PicoCpuFM68k.sr\r
+#define SekSrS68k PicoCpuFS68k.sr\r
#define SekSetStop(x) { \\r
PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
}\r
+#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
-#define SekShouldInterrupt fm68k_would_interrupt()\r
+#define SekShouldInterrupt() fm68k_would_interrupt()\r
+\r
+#define SekNotPolling PicoCpuFM68k.not_polling\r
+#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
\r
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
+#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
\r
-#ifdef EMU_M68K\r
-#define EMU_CORE_DEBUG\r
-#endif\r
#endif\r
\r
#ifdef EMU_M68K\r
#include "../cpu/musashi/m68kcpu.h"\r
extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
#ifndef SekCyclesLeft\r
-#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
-#define SekEndTimeslice(after) SET_CYCLES(after)\r
-#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
+#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
+#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
+#define SekDar(x) PicoCpuMM68k.dar[x]\r
+#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
+#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
+#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
#define SekSetStop(x) { \\r
if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
else PicoCpuMM68k.stopped=0; \\r
if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
else PicoCpuMS68k.stopped=0; \\r
}\r
+#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
-#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
+#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
+\r
+#define SekNotPolling PicoCpuMM68k.not_polling\r
+#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
\r
#define SekInterrupt(irq) { \\r
void *oldcontext = m68ki_cpu_p; \\r
m68k_set_irq(irq); \\r
m68k_set_context(oldcontext); \\r
}\r
+#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
\r
#endif\r
#endif // EMU_M68K\r
\r
-extern int SekCycleCnt; // cycles done in this frame\r
-extern int SekCycleAim; // cycle aim\r
-extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
-\r
-#define SekCyclesReset() { \\r
- SekCycleCntT+=SekCycleAim; \\r
- SekCycleCnt-=SekCycleAim; \\r
- SekCycleAim=0; \\r
+// while running, cnt represents target of current timeslice\r
+// while not in SekRun(), it's actual cycles done\r
+// (but always use SekCyclesDone() if you need current position)\r
+// cnt may change if timeslice is ended prematurely or extended,\r
+// so we use SekCycleAim for the actual target\r
+extern unsigned int SekCycleCnt;\r
+extern unsigned int SekCycleAim;\r
+\r
+// number of cycles done (can be checked anywhere)\r
+#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
+\r
+// burn cycles while not in SekRun() and while in\r
+#define SekCyclesBurn(c) SekCycleCnt += c\r
+#define SekCyclesBurnRun(c) { \\r
+ SekCyclesLeft -= c; \\r
}\r
-#define SekCyclesBurn(c) SekCycleCnt+=c\r
-#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
-#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
\r
+// note: sometimes may extend timeslice to delay an irq\r
#define SekEndRun(after) { \\r
- SekCycleCnt -= SekCyclesLeft - (after); \\r
- if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
- SekEndTimeslice(after); \\r
+ SekCycleCnt -= SekCyclesLeft - (after); \\r
+ SekCyclesLeft = after; \\r
}\r
\r
+extern unsigned int SekCycleCntS68k;\r
+extern unsigned int SekCycleAimS68k;\r
+\r
#define SekEndRunS68k(after) { \\r
- SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
- if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
- SekEndTimesliceS68k(after); \\r
+ if (SekCyclesLeftS68k > (after)) { \\r
+ SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
+ SekCyclesLeftS68k = after; \\r
+ } \\r
}\r
\r
-extern int SekCycleCntS68k;\r
-extern int SekCycleAimS68k;\r
+#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
\r
-#define SekCyclesResetS68k() { \\r
- SekCycleCntS68k-=SekCycleAimS68k; \\r
- SekCycleAimS68k=0; \\r
-}\r
-#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
-\r
-#ifdef EMU_CORE_DEBUG\r
-extern int dbg_irq_level;\r
-#undef SekEndTimeslice\r
-#undef SekCyclesBurn\r
-#undef SekEndRun\r
-#undef SekInterrupt\r
-#define SekEndTimeslice(c)\r
-#define SekCyclesBurn(c) c\r
-#define SekEndRun(c)\r
-#define SekInterrupt(irq) dbg_irq_level=irq\r
-#endif\r
+// compare cycles, handling overflows\r
+// check if a > b\r
+#define CYCLES_GT(a, b) \\r
+ ((int)((a) - (b)) > 0)\r
+// check if a >= b\r
+#define CYCLES_GE(a, b) \\r
+ ((int)((a) - (b)) >= 0)\r
\r
// ----------------------- Z80 CPU -----------------------\r
\r
-#if defined(_USE_MZ80)\r
-#include "../cpu/mz80/mz80.h"\r
-\r
-#define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r
-#define z80_run_nr(cycles) mz80_run(cycles)\r
-#define z80_int() mz80int(0)\r
-\r
-#elif defined(_USE_DRZ80)\r
+#if defined(_USE_DRZ80)\r
#include "../cpu/DrZ80/drz80.h"\r
\r
extern struct DrZ80 drZ80;\r
#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
#define z80_int() drZ80.Z80_IRQ = 1\r
+#define z80_int() drZ80.Z80_IRQ = 1\r
+#define z80_nmi() drZ80.Z80IF |= 8\r
\r
#define z80_cyclesLeft drZ80.cycles\r
#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
+#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
\r
#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
#define z80_run(cycles) (cycles)\r
#define z80_run_nr(cycles)\r
#define z80_int()\r
+#define z80_nmi()\r
\r
#endif\r
\r
-extern int z80stopCycle; /* in 68k cycles */\r
+#define Z80_STATE_SIZE 0x60\r
+\r
+extern unsigned int last_z80_sync;\r
extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
extern int z80_cycle_aim;\r
extern int z80_scanline;\r
extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
\r
#define z80_resetCycles() \\r
+ last_z80_sync = SekCyclesDone(); \\r
z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
\r
#define z80_cyclesDone() \\r
\r
#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
\r
-#define Z80_MEM_SHIFT 13\r
-extern unsigned long z80_read_map [0x10000 >> Z80_MEM_SHIFT];\r
-extern unsigned long z80_write_map[0x10000 >> Z80_MEM_SHIFT];\r
-typedef unsigned char (z80_read_f)(unsigned short a);\r
-typedef void (z80_write_f)(unsigned int a, unsigned char data);\r
+// ----------------------- SH2 CPU -----------------------\r
+\r
+#include "cpu/sh2/sh2.h"\r
+\r
+extern SH2 sh2s[2];\r
+#define msh2 sh2s[0]\r
+#define ssh2 sh2s[1]\r
+\r
+#ifndef DRC_SH2\r
+# define sh2_end_run(sh2, after_) do { \\r
+ if ((sh2)->icount > (after_)) { \\r
+ (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
+ (sh2)->icount = after_; \\r
+ } \\r
+} while (0)\r
+# define sh2_cycles_left(sh2) (sh2)->icount\r
+# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
+# define sh2_pc(sh2) (sh2)->ppc\r
+#else\r
+# define sh2_end_run(sh2, after_) do { \\r
+ int left_ = (signed int)(sh2)->sr >> 12; \\r
+ if (left_ > (after_)) { \\r
+ (sh2)->cycles_timeslice -= left_ - (after_); \\r
+ (sh2)->sr &= 0xfff; \\r
+ (sh2)->sr |= (after_) << 12; \\r
+ } \\r
+} while (0)\r
+# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
+# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
+# define sh2_pc(sh2) (sh2)->pc\r
+#endif\r
+\r
+#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
+#define sh2_cycles_done_t(sh2) \\r
+ ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
+#define sh2_cycles_done_m68k(sh2) \\r
+ ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
+\r
+#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
+#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
+#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
+#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
+\r
+#define sh2_set_gbr(c, v) \\r
+ { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
+#define sh2_set_vbr(c, v) \\r
+ { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
+\r
+#define elprintf_sh2(sh2, w, f, ...) \\r
+ elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
\r
// ---------------------------------------------------------\r
\r
#define OSC_NTSC 53693100\r
#define OSC_PAL 53203424\r
\r
+#define PVD_KILL_A (1 << 0)\r
+#define PVD_KILL_B (1 << 1)\r
+#define PVD_KILL_S_LO (1 << 2)\r
+#define PVD_KILL_S_HI (1 << 3)\r
+#define PVD_KILL_32X (1 << 4)\r
+#define PVD_FORCE_A (1 << 5)\r
+#define PVD_FORCE_B (1 << 6)\r
+#define PVD_FORCE_S (1 << 7)\r
+\r
struct PicoVideo\r
{\r
unsigned char reg[0x20];\r
unsigned char pending_ints; // pending interrupts: ??VH????\r
signed char lwrite_cnt; // VDP write count during active display line\r
unsigned short v_counter; // V-counter\r
- unsigned char pad[0x10];\r
+ unsigned short debug; // raw debug register\r
+ unsigned char debug_p; // ... parsed: PVD_*\r
+ unsigned char addr_u;\r
+ unsigned char pad[0x0c];\r
};\r
\r
struct PicoMisc\r
unsigned char pal; // 08 1=PAL 0=NTSC\r
unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
unsigned short z80_bank68k; // 0a\r
- unsigned short z80_lastaddr; // this is for Z80 faking\r
- unsigned char pad0;\r
- unsigned char z80_reset; // z80 reset held\r
+ unsigned short pad0;\r
+ unsigned char ncart_in; // 0e !cart_in\r
+ unsigned char z80_reset; // 0f z80 reset held\r
unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
unsigned short eeprom_addr; // EEPROM address register\r
unsigned char eeprom_cycle; // EEPROM cycle number\r
unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
unsigned char eeprom_status;\r
- unsigned char pad1;\r
+ unsigned char pad2;\r
unsigned short dma_xfers; // 18\r
unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
unsigned int frame_count; // 1c for movies and idle det\r
};\r
\r
+struct PicoMS\r
+{\r
+ unsigned char carthw[0x10];\r
+ unsigned char io_ctl;\r
+ unsigned char nmi_state;\r
+ unsigned char pad[0x4e];\r
+};\r
+\r
+// emu state and data for the asm code\r
+struct PicoEState\r
+{\r
+ int DrawScanline;\r
+ int rendstatus;\r
+ void *DrawLineDest; // draw destination\r
+ unsigned char *HighCol;\r
+ int *HighPreSpr;\r
+ void *Pico_video;\r
+ void *Pico_vram;\r
+ int *PicoOpt;\r
+ unsigned char *Draw2FB;\r
+ unsigned short HighPal[0x100];\r
+};\r
+\r
// some assembly stuff depend on these, do not touch!\r
struct Pico\r
{\r
unsigned char vramb[0x4000]; // VRAM in SMS mode\r
};\r
unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
- unsigned char ioports[0x10];\r
- unsigned char sms_io_ctl;\r
- unsigned char pad[0xef]; // unused\r
+ unsigned char ioports[0x10]; // XXX: fix asm and mv\r
+ unsigned char pad[0xf0]; // unused\r
unsigned short cram[0x40]; // 0x22100\r
unsigned short vsram[0x40]; // 0x22180\r
\r
unsigned char *rom; // 0x22200\r
- unsigned int romsize; // 0x22204\r
+ unsigned int romsize; // 0x22204 (on 32bits)\r
\r
struct PicoMisc m;\r
struct PicoVideo video;\r
+ struct PicoMS ms;\r
+ struct PicoEState est;\r
};\r
\r
// sram\r
};\r
\r
// MCD\r
-#include "cd/cd_sys.h"\r
-#include "cd/LC89510.h"\r
-#include "cd/gfx_cd.h"\r
+#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
\r
struct mcd_pcm\r
{\r
unsigned char enabled; // reg8\r
unsigned char cur_ch;\r
unsigned char bank;\r
- int pad1;\r
+ unsigned int update_cycles;\r
\r
struct pcm_chan // 08, size 0x10\r
{\r
} ch[8];\r
};\r
\r
+#define PCD_ST_S68K_RST 1\r
+\r
struct mcd_misc\r
{\r
- unsigned short hint_vector;\r
- unsigned char busreq;\r
- unsigned char s68k_pend_ints;\r
- unsigned int state_flags; // 04: emu state: reset_pending\r
- unsigned int counter75hz;\r
- unsigned int pad0;\r
- int timer_int3; // 10\r
- unsigned int timer_stopwatch;\r
- unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
- unsigned char pad2;\r
- unsigned short pad3;\r
- int pad[9];\r
+ unsigned short hint_vector;\r
+ unsigned char busreq; // not s68k_regs[1]\r
+ unsigned char s68k_pend_ints;\r
+ unsigned int state_flags; // 04\r
+ unsigned int stopwatch_base_c;\r
+ unsigned short m68k_poll_a;\r
+ unsigned short m68k_poll_cnt;\r
+ unsigned short s68k_poll_a;\r
+ unsigned short s68k_poll_cnt;\r
+ unsigned int s68k_poll_clk;\r
+ unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
+ unsigned char dmna_ret_2m;\r
+ unsigned char need_sync;\r
+ unsigned char pad3;\r
+ int pad4[9];\r
};\r
\r
typedef struct\r
{\r
- unsigned char bios[0x20000]; // 000000: 128K\r
- union { // 020000: 512K\r
- unsigned char prg_ram[0x80000];\r
- unsigned char prg_ram_b[4][0x20000];\r
- };\r
- union { // 0a0000: 256K\r
- struct {\r
- unsigned char word_ram2M[0x40000];\r
- unsigned char unused0[0x20000];\r
- };\r
- struct {\r
- unsigned char unused1[0x20000];\r
- unsigned char word_ram1M[2][0x20000];\r
- };\r
- };\r
- union { // 100000: 64K\r
- unsigned char pcm_ram[0x10000];\r
- unsigned char pcm_ram_b[0x10][0x1000];\r
- };\r
- unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
- unsigned char bram[0x2000]; // 110200: 8K\r
- struct mcd_misc m; // 112200: misc\r
- struct mcd_pcm pcm; // 112240:\r
- _scd_toc TOC; // not to be saved\r
- CDD cdd;\r
- CDC cdc;\r
- _scd scd;\r
- Rot_Comp rot_comp;\r
+ unsigned char bios[0x20000]; // 000000: 128K\r
+ union { // 020000: 512K\r
+ unsigned char prg_ram[0x80000];\r
+ unsigned char prg_ram_b[4][0x20000];\r
+ };\r
+ union { // 0a0000: 256K\r
+ struct {\r
+ unsigned char word_ram2M[0x40000];\r
+ unsigned char unused0[0x20000];\r
+ };\r
+ struct {\r
+ unsigned char unused1[0x20000];\r
+ unsigned char word_ram1M[2][0x20000];\r
+ };\r
+ };\r
+ union { // 100000: 64K\r
+ unsigned char pcm_ram[0x10000];\r
+ unsigned char pcm_ram_b[0x10][0x1000];\r
+ };\r
+ unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
+ unsigned char bram[0x2000]; // 110200: 8K\r
+ struct mcd_misc m; // 112200: misc\r
+ struct mcd_pcm pcm; // 112240:\r
+ void *cdda_stream;\r
+ int cdda_type;\r
+ int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
+ int pcm_mixpos;\r
+ char pcm_mixbuf_dirty;\r
+ char pcm_regs_dirty;\r
} mcd_state;\r
\r
+// XXX: this will need to be reworked for cart+cd support.\r
#define Pico_mcd ((mcd_state *)Pico.rom)\r
\r
+// 32X\r
+#define P32XS_FM (1<<15)\r
+#define P32XS_nCART (1<< 8)\r
+#define P32XS_REN (1<< 7)\r
+#define P32XS_nRES (1<< 1)\r
+#define P32XS_ADEN (1<< 0)\r
+#define P32XS2_ADEN (1<< 9)\r
+#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
+#define P32XS_68S (1<< 2)\r
+#define P32XS_DMA (1<< 1)\r
+#define P32XS_RV (1<< 0)\r
+\r
+#define P32XV_nPAL (1<<15) // VDP\r
+#define P32XV_PRI (1<< 7)\r
+#define P32XV_Mx (3<< 0) // display mode mask\r
+\r
+#define P32XV_SFT (1<< 0)\r
+\r
+#define P32XV_VBLK (1<<15)\r
+#define P32XV_HBLK (1<<14)\r
+#define P32XV_PEN (1<<13)\r
+#define P32XV_nFEN (1<< 1)\r
+#define P32XV_FS (1<< 0)\r
+\r
+#define P32XP_RTP (1<<7) // PWM control\r
+#define P32XP_FULL (1<<15) // PWM pulse\r
+#define P32XP_EMPTY (1<<14)\r
+\r
+#define P32XF_68KCPOLL (1 << 0)\r
+#define P32XF_68KVPOLL (1 << 1)\r
+#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
+\r
+#define P32XI_VRES (1 << 14/2) // IRL/2\r
+#define P32XI_VINT (1 << 12/2)\r
+#define P32XI_HINT (1 << 10/2)\r
+#define P32XI_CMD (1 << 8/2)\r
+#define P32XI_PWM (1 << 6/2)\r
+\r
+// peripheral reg access\r
+#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
+\r
+#define DMAC_FIFO_LEN (4*2)\r
+#define PWM_BUFF_LEN 1024 // in one channel samples\r
+\r
+#define SH2_DRCBLK_RAM_SHIFT 1\r
+#define SH2_DRCBLK_DA_SHIFT 1\r
+\r
+#define SH2_READ_SHIFT 25\r
+#define SH2_WRITE_SHIFT 25\r
+\r
+struct Pico32x\r
+{\r
+ unsigned short regs[0x20];\r
+ unsigned short vdp_regs[0x10]; // 0x40\r
+ unsigned short sh2_regs[3]; // 0x60\r
+ unsigned char pending_fb;\r
+ unsigned char dirty_pal;\r
+ unsigned int emu_flags;\r
+ unsigned char sh2irq_mask[2];\r
+ unsigned char sh2irqi[2]; // individual\r
+ unsigned int sh2irqs; // common irqs\r
+ unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
+ unsigned int pad[4];\r
+ unsigned int dmac0_fifo_ptr;\r
+ unsigned short vdp_fbcr_fake;\r
+ unsigned short pad2;\r
+ unsigned char comm_dirty_68k;\r
+ unsigned char comm_dirty_sh2;\r
+ unsigned char pwm_irq_cnt;\r
+ unsigned char pad1;\r
+ unsigned short pwm_p[2]; // pwm pos in fifo\r
+ unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
+ unsigned int reserved[6];\r
+};\r
+\r
+struct Pico32xMem\r
+{\r
+ unsigned char sdram[0x40000];\r
+#ifdef DRC_SH2\r
+ unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
+#endif\r
+ unsigned short dram[2][0x20000/2]; // AKA fb\r
+ union {\r
+ unsigned char m68k_rom[0x100];\r
+ unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
+ };\r
+#ifdef DRC_SH2\r
+ unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
+#endif\r
+ union {\r
+ unsigned char b[0x800];\r
+ unsigned short w[0x800/2];\r
+ } sh2_rom_m;\r
+ union {\r
+ unsigned char b[0x400];\r
+ unsigned short w[0x400/2];\r
+ } sh2_rom_s;\r
+ unsigned short pal[0x100];\r
+ unsigned short pal_native[0x100]; // converted to native (for renderer)\r
+ signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
+ signed short pwm_current[2]; // current converted samples\r
+ unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
+};\r
\r
// area.c\r
-PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
-PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
extern void (*PicoLoadStateHook)(void);\r
\r
-// cd/area.c\r
-PICO_INTERNAL int PicoCdSaveState(void *file);\r
-PICO_INTERNAL int PicoCdLoadState(void *file);\r
-\r
typedef struct {\r
int chunk;\r
int size;\r
extern carthw_state_chunk *carthw_chunks;\r
#define CHUNK_CARTHW 64\r
\r
-// area.c\r
-typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r
-typedef size_t (areaeof)(void *file);\r
-typedef int (areaseek)(void *file, long offset, int whence);\r
-typedef int (areaclose)(void *file);\r
-extern arearw *areaRead; // external read and write function pointers for\r
-extern arearw *areaWrite; // gzip save state ability\r
-extern areaeof *areaEof;\r
-extern areaseek *areaSeek;\r
-extern areaclose *areaClose;\r
-\r
// cart.c\r
+extern int PicoCartResize(int newsize);\r
+extern void Byteswap(void *dst, const void *src, int len);\r
extern void (*PicoCartMemSetup)(void);\r
extern void (*PicoCartUnloadHook)(void);\r
\r
int CM_compareRun(int cyc, int is_sub);\r
\r
// draw.c\r
+void PicoDrawInit(void);\r
PICO_INTERNAL void PicoFrameStart(void);\r
void PicoDrawSync(int to, int blank_last_line);\r
-void BackFill(int reg7, int sh);\r
-void FinalizeLineRGB555(int sh);\r
-extern int DrawScanline;\r
+void BackFill(int reg7, int sh, struct PicoEState *est);\r
+void FinalizeLine555(int sh, int line, struct PicoEState *est);\r
+extern int (*PicoScanBegin)(unsigned int num);\r
+extern int (*PicoScanEnd)(unsigned int num);\r
#define MAX_LINE_SPRITES 29\r
extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
+extern void *DrawLineDestBase;\r
+extern int DrawLineDestIncrement;\r
\r
// draw2.c\r
+void PicoDraw2Init(void);\r
PICO_INTERNAL void PicoFrameFull();\r
\r
// mode4.c\r
void PicoFrameStartMode4(void);\r
void PicoLineMode4(int line);\r
void PicoDoHighPal555M4(void);\r
-void PicoDrawSetColorFormatMode4(int which);\r
+void PicoDrawSetOutputMode4(pdso_t which);\r
\r
// memory.c\r
-PICO_INTERNAL void PicoInitPc(unsigned int pc);\r
-PICO_INTERNAL unsigned int PicoCheckPc(unsigned int pc);\r
PICO_INTERNAL void PicoMemSetup(void);\r
unsigned int PicoRead8_io(unsigned int a);\r
unsigned int PicoRead16_io(unsigned int a);\r
// pico/memory.c\r
PICO_INTERNAL void PicoMemSetupPico(void);\r
\r
+// cd/cdc.c\r
+void cdc_init(void);\r
+void cdc_reset(void);\r
+int cdc_context_save(unsigned char *state);\r
+int cdc_context_load(unsigned char *state);\r
+int cdc_context_load_old(unsigned char *state);\r
+void cdc_dma_update(void);\r
+int cdc_decoder_update(unsigned char header[4]);\r
+void cdc_reg_w(unsigned char data);\r
+unsigned char cdc_reg_r(void);\r
+unsigned short cdc_host_r(void);\r
+\r
+// cd/cdd.c\r
+void cdd_reset(void);\r
+int cdd_context_save(unsigned char *state);\r
+int cdd_context_load(unsigned char *state);\r
+int cdd_context_load_old(unsigned char *state);\r
+void cdd_read_data(unsigned char *dst);\r
+void cdd_read_audio(unsigned int samples);\r
+void cdd_update(void);\r
+void cdd_process(void);\r
+\r
+// cd/cd_image.c\r
+int load_cd_image(const char *cd_img_name, int *type);\r
+\r
+// cd/gfx.c\r
+void gfx_init(void);\r
+void gfx_start(unsigned int base);\r
+void gfx_update(unsigned int cycles);\r
+int gfx_context_save(unsigned char *state);\r
+int gfx_context_load(const unsigned char *state);\r
+\r
+// cd/gfx_dma.c\r
+void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
+\r
// cd/memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
-PICO_INTERNAL_ASM void PicoMemRemapCD(int r3);\r
-PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
+unsigned int PicoRead8_mcd_io(unsigned int a);\r
+unsigned int PicoRead16_mcd_io(unsigned int a);\r
+void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
+void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
+void pcd_state_loaded_mem(void);\r
\r
// pico.c\r
extern struct Pico Pico;\r
extern struct PicoSRAM SRam;\r
extern int PicoPadInt[2];\r
extern int emustatus;\r
+extern int scanlines_total;\r
extern void (*PicoResetHook)(void);\r
extern void (*PicoLineHook)(void);\r
PICO_INTERNAL int CheckDMA(void);\r
PICO_INTERNAL void PicoDetectRegion(void);\r
-PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
+PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
+\r
+// cd/mcd.c\r
+#define PCDS_IEN1 (1<<1)\r
+#define PCDS_IEN2 (1<<2)\r
+#define PCDS_IEN3 (1<<3)\r
+#define PCDS_IEN4 (1<<4)\r
+#define PCDS_IEN5 (1<<5)\r
+#define PCDS_IEN6 (1<<6)\r
\r
-// cd/pico.c\r
PICO_INTERNAL void PicoInitMCD(void);\r
PICO_INTERNAL void PicoExitMCD(void);\r
PICO_INTERNAL void PicoPowerMCD(void);\r
PICO_INTERNAL int PicoResetMCD(void);\r
PICO_INTERNAL void PicoFrameMCD(void);\r
\r
+enum pcd_event {\r
+ PCD_EVENT_CDC,\r
+ PCD_EVENT_TIMER3,\r
+ PCD_EVENT_GFX,\r
+ PCD_EVENT_DMA,\r
+ PCD_EVENT_COUNT,\r
+};\r
+extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
+void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
+void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
+void pcd_prepare_frame(void);\r
+unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
+int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
+void pcd_run_cpus(int m68k_cycles);\r
+void pcd_soft_reset(void);\r
+void pcd_state_loaded(void);\r
+\r
+// cd/pcm.c\r
+void pcd_pcm_sync(unsigned int to);\r
+void pcd_pcm_update(int *buffer, int length, int stereo);\r
+void pcd_pcm_write(unsigned int a, unsigned int d);\r
+unsigned int pcd_pcm_read(unsigned int a);\r
+\r
// pico/pico.c\r
PICO_INTERNAL void PicoInitPico(void);\r
PICO_INTERNAL void PicoReratePico(void);\r
PICO_INTERNAL int SekReset(void);\r
PICO_INTERNAL void SekState(int *data);\r
PICO_INTERNAL void SekSetRealTAS(int use_real);\r
+PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
+PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
void SekStepM68k(void);\r
void SekInitIdleDet(void);\r
void SekFinishIdleDet(void);\r
+#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
+void SekTrace(int is_s68k);\r
+#else\r
+#define SekTrace(x)\r
+#endif\r
\r
// cd/sek.c\r
PICO_INTERNAL void SekInitS68k(void);\r
PICO_INTERNAL int SekResetS68k(void);\r
PICO_INTERNAL int SekInterruptS68k(int irq);\r
+void SekInterruptClearS68k(int irq);\r
\r
// sound/sound.c\r
-PICO_INTERNAL void cdda_start_play();\r
extern short cdda_out_buffer[2*1152];\r
extern int PsndLen_exc_cnt;\r
extern int PsndLen_exc_add;\r
extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
extern int timer_b_next_oflow, timer_b_step;\r
\r
+void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
+\r
void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
void ym2612_pack_state(void);\r
void ym2612_unpack_state(void);\r
\r
\r
// videoport.c\r
+extern int line_base_cycles;\r
PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
-extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
+extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask);\r
\r
// misc.c\r
PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
-PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
-PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
+PICO_INTERNAL_ASM void memcpy32(void *dest, const void *src, int count); // 32bit word count\r
+PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);\r
\r
// eeprom.c\r
void EEPROM_write8(unsigned int a, unsigned int d);\r
\r
// z80 functionality wrappers\r
PICO_INTERNAL void z80_init(void);\r
-PICO_INTERNAL void z80_pack(unsigned char *data);\r
-PICO_INTERNAL void z80_unpack(unsigned char *data);\r
+PICO_INTERNAL void z80_pack(void *data);\r
+PICO_INTERNAL int z80_unpack(const void *data);\r
PICO_INTERNAL void z80_reset(void);\r
PICO_INTERNAL void z80_exit(void);\r
\r
PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
\r
-// cd/buffering.c\r
-PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
-\r
// sound/sound.c\r
PICO_INTERNAL void PsndReset(void);\r
PICO_INTERNAL void PsndDoDAC(int line_to);\r
extern int PsndDacLine;\r
\r
// sms.c\r
+#ifndef NO_SMS\r
void PicoPowerMS(void);\r
void PicoResetMS(void);\r
void PicoMemSetupMS(void);\r
+void PicoStateLoadedMS(void);\r
void PicoFrameMS(void);\r
void PicoFrameDrawOnlyMS(void);\r
+#else\r
+#define PicoPowerMS()\r
+#define PicoResetMS()\r
+#define PicoMemSetupMS()\r
+#define PicoStateLoadedMS()\r
+#define PicoFrameMS()\r
+#define PicoFrameDrawOnlyMS()\r
+#endif\r
+\r
+// 32x/32x.c\r
+#ifndef NO_32X\r
+extern struct Pico32x Pico32x;\r
+enum p32x_event {\r
+ P32X_EVENT_PWM,\r
+ P32X_EVENT_FILLEND,\r
+ P32X_EVENT_HINT,\r
+ P32X_EVENT_COUNT,\r
+};\r
+extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
+\r
+void Pico32xInit(void);\r
+void PicoPower32x(void);\r
+void PicoReset32x(void);\r
+void Pico32xStartup(void);\r
+void PicoUnload32x(void);\r
+void PicoFrame32x(void);\r
+void Pico32xStateLoaded(int is_early);\r
+void p32x_sync_sh2s(unsigned int m68k_target);\r
+void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
+void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
+void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
+void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
+void p32x_reset_sh2s(void);\r
+void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
+void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
+void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
+\r
+// 32x/memory.c\r
+struct Pico32xMem *Pico32xMem;\r
+unsigned int PicoRead8_32x(unsigned int a);\r
+unsigned int PicoRead16_32x(unsigned int a);\r
+void PicoWrite8_32x(unsigned int a, unsigned int d);\r
+void PicoWrite16_32x(unsigned int a, unsigned int d);\r
+void PicoMemSetup32x(void);\r
+void Pico32xSwapDRAM(int b);\r
+void Pico32xMemStateLoaded(void);\r
+void p32x_m68k_poll_event(unsigned int flags);\r
+void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
+\r
+// 32x/draw.c\r
+void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
+void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r
+void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
+void PicoDraw32xLayerMdOnly(int offs, int lines);\r
+extern int (*PicoScan32xBegin)(unsigned int num);\r
+extern int (*PicoScan32xEnd)(unsigned int num);\r
+enum {\r
+ PDM32X_OFF,\r
+ PDM32X_32X_ONLY,\r
+ PDM32X_BOTH,\r
+};\r
+extern int Pico32xDrawMode;\r
+\r
+// 32x/pwm.c\r
+unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
+ unsigned int m68k_cycles);\r
+void p32x_pwm_write16(unsigned int a, unsigned int d,\r
+ SH2 *sh2, unsigned int m68k_cycles);\r
+void p32x_pwm_update(int *buf32, int length, int stereo);\r
+void p32x_pwm_ctl_changed(void);\r
+void p32x_pwm_schedule(unsigned int m68k_now);\r
+void p32x_pwm_schedule_sh2(SH2 *sh2);\r
+void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
+void p32x_pwm_irq_event(unsigned int m68k_now);\r
+void p32x_pwm_state_loaded(void);\r
+\r
+// 32x/sh2soc.c\r
+void p32x_dreq0_trigger(void);\r
+void p32x_dreq1_trigger(void);\r
+void p32x_timers_recalc(void);\r
+void p32x_timers_do(unsigned int m68k_slice);\r
+void sh2_peripheral_reset(SH2 *sh2);\r
+unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+\r
+#else\r
+#define Pico32xInit()\r
+#define PicoPower32x()\r
+#define PicoReset32x()\r
+#define PicoFrame32x()\r
+#define PicoUnload32x()\r
+#define Pico32xStateLoaded()\r
+#define FinalizeLine32xRGB555 NULL\r
+#define p32x_pwm_update(...)\r
+#define p32x_timers_recalc()\r
+#endif\r
\r
/* avoid dependency on newer glibc */\r
static __inline int isspace_(int c)\r
return (0x09 <= c && c <= 0x0d) || c == ' ';\r
}\r
\r
+#ifndef ARRAY_SIZE\r
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
+#endif\r
+\r
// emulation event logging\r
#ifndef EL_LOGMASK\r
-#define EL_LOGMASK 0\r
+# ifdef __x86_64__ // HACK\r
+# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
+# else\r
+# define EL_LOGMASK (EL_STATUS)\r
+# endif\r
#endif\r
\r
#define EL_HVCNT 0x00000001 /* hv counter reads */\r
#define EL_IDLE 0x00010000 /* idle loop det. */\r
#define EL_CDREGS 0x00020000 /* MCD: register access */\r
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
+#define EL_32X 0x00080000\r
+#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
+#define EL_32XP 0x00200000 /* 32X peripherals */\r
+#define EL_CD 0x00400000 /* MCD */\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
\r
#if EL_LOGMASK\r
-extern void lprintf(const char *fmt, ...);\r
#define elprintf(w,f,...) \\r
-{ \\r
+do { \\r
if ((w) & EL_LOGMASK) \\r
lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
-}\r
+} while (0)\r
#elif defined(_MSC_VER)\r
#define elprintf\r
#else\r
#define elprintf(w,f,...)\r
#endif\r
\r
+// profiling\r
+#ifdef PPROF\r
+#include <platform/linux/pprof.h>\r
+#else\r
+#define pprof_init()\r
+#define pprof_finish()\r
+#define pprof_start(x)\r
+#define pprof_end(...)\r
+#define pprof_end_sub(...)\r
+#endif\r
+\r
+#ifdef EVT_LOG\r
+enum evt {\r
+ EVT_FRAME_START,\r
+ EVT_NEXT_LINE,\r
+ EVT_RUN_START,\r
+ EVT_RUN_END,\r
+ EVT_POLL_START,\r
+ EVT_POLL_END,\r
+ EVT_CNT\r
+};\r
+\r
+enum evt_cpu {\r
+ EVT_M68K,\r
+ EVT_S68K,\r
+ EVT_MSH2,\r
+ EVT_SSH2,\r
+ EVT_CPU_CNT\r
+};\r
+\r
+void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
+void pevt_dump(void);\r
+\r
+#define pevt_log_m68k(e) \\r
+ pevt_log(SekCyclesDone(), EVT_M68K, e)\r
+#define pevt_log_m68k_o(e) \\r
+ pevt_log(SekCyclesDone(), EVT_M68K, e)\r
+#define pevt_log_sh2(sh2, e) \\r
+ pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
+#define pevt_log_sh2_o(sh2, e) \\r
+ pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
+#else\r
+#define pevt_log(c, e)\r
+#define pevt_log_m68k(e)\r
+#define pevt_log_m68k_o(e)\r
+#define pevt_log_sh2(sh2, e)\r
+#define pevt_log_sh2_o(sh2, e)\r
+#define pevt_dump()\r
+#endif\r
+\r
+// misc\r
#ifdef _MSC_VER\r
#define cdprintf\r
#else\r
#define cdprintf(x...)\r
#endif\r
\r
-#if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 3\r
-#define MEMH_FUNC __attribute__((aligned(4)))\r
+#if defined(__GNUC__) && defined(__i386__)\r
+#define REGPARM(x) __attribute__((regparm(x)))\r
+#else\r
+#define REGPARM(x)\r
+#endif\r
+\r
+#ifdef __GNUC__\r
+#define NOINLINE __attribute__((noinline))\r
#else\r
-#define MEMH_FUNC\r
+#define NOINLINE\r
#endif\r
\r
#ifdef __cplusplus\r
notaz.gp2x.de / picodrive.git / blobdiff