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1 | /* Teensyduino Core Library |
| 2 | * http://www.pjrc.com/teensy/ |
| 3 | * Copyright (c) 2013 PJRC.COM, LLC. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining |
| 6 | * a copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sublicense, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
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13 | * 1. The above copyright notice and this permission notice shall be |
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14 | * included in all copies or substantial portions of the Software. |
| 15 | * |
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16 | * 2. If the Software is incorporated into a build system that allows |
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17 | * selection among a list of target devices, then similar target |
| 18 | * devices manufactured by PJRC.COM must be included in the list of |
| 19 | * target devices and selectable in the same manner. |
| 20 | * |
| 21 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 22 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 23 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 24 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 25 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 26 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 27 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 28 | * SOFTWARE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef _core_pins_h_ |
| 32 | #define _core_pins_h_ |
| 33 | |
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34 | #include "kinetis.h" |
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35 | #include "pins_arduino.h" |
| 36 | |
| 37 | |
| 38 | #define HIGH 1 |
| 39 | #define LOW 0 |
| 40 | #define INPUT 0 |
| 41 | #define OUTPUT 1 |
| 42 | #define INPUT_PULLUP 2 |
| 43 | #define LSBFIRST 0 |
| 44 | #define MSBFIRST 1 |
| 45 | #define _BV(n) (1<<(n)) |
| 46 | #define CHANGE 4 |
| 47 | #define FALLING 2 |
| 48 | #define RISING 3 |
| 49 | |
| 50 | // Pin Arduino |
| 51 | // 0 B16 RXD |
| 52 | // 1 B17 TXD |
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53 | // 2 D0 |
| 54 | // 3 A12 FTM1_CH0 |
| 55 | // 4 A13 FTM1_CH1 |
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56 | // 5 D7 FTM0_CH7 OC0B/T1 |
| 57 | // 6 D4 FTM0_CH4 OC0A |
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58 | // 7 D2 |
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59 | // 8 D3 ICP1 |
| 60 | // 9 C3 FTM0_CH2 OC1A |
| 61 | // 10 C4 FTM0_CH3 SS/OC1B |
| 62 | // 11 C6 MOSI/OC2A |
| 63 | // 12 C7 MISO |
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64 | // 13 C5 SCK |
| 65 | // 14 D1 |
| 66 | // 15 C0 |
| 67 | // 16 B0 (FTM1_CH0) |
| 68 | // 17 B1 (FTM1_CH1) |
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69 | // 18 B3 SDA |
| 70 | // 19 B2 SCL |
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71 | // 20 D5 FTM0_CH5 |
| 72 | // 21 D6 FTM0_CH6 |
| 73 | // 22 C1 FTM0_CH0 |
| 74 | // 23 C2 FTM0_CH1 |
| 75 | // 24 A5 (FTM0_CH2) |
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76 | // 25 B19 |
| 77 | // 26 E1 |
| 78 | // 27 C9 |
| 79 | // 28 C8 |
| 80 | // 29 C10 |
| 81 | // 30 C11 |
| 82 | // 31 E0 |
| 83 | // 32 B18 |
| 84 | // 33 A4 (FTM0_CH1) |
| 85 | // (34) analog only |
| 86 | // (35) analog only |
| 87 | // (36) analog only |
| 88 | // (37) analog only |
| 89 | |
| 90 | // not available to user: |
| 91 | // A0 FTM0_CH5 SWD Clock |
| 92 | // A1 FTM0_CH6 USB ID |
| 93 | // A2 FTM0_CH7 SWD Trace |
| 94 | // A3 FTM0_CH0 SWD Data |
| 95 | |
| 96 | #define CORE_NUM_TOTAL_PINS 34 |
| 97 | #define CORE_NUM_DIGITAL 34 |
| 98 | #define CORE_NUM_INTERRUPT 34 |
| 99 | #if defined(__MK20DX128__) |
| 100 | #define CORE_NUM_ANALOG 14 |
| 101 | #define CORE_NUM_PWM 10 |
| 102 | #elif defined(__MK20DX256__) |
| 103 | #define CORE_NUM_ANALOG 21 |
| 104 | #define CORE_NUM_PWM 12 |
| 105 | #endif |
| 106 | |
| 107 | #define CORE_PIN0_BIT 16 |
| 108 | #define CORE_PIN1_BIT 17 |
| 109 | #define CORE_PIN2_BIT 0 |
| 110 | #define CORE_PIN3_BIT 12 |
| 111 | #define CORE_PIN4_BIT 13 |
| 112 | #define CORE_PIN5_BIT 7 |
| 113 | #define CORE_PIN6_BIT 4 |
| 114 | #define CORE_PIN7_BIT 2 |
| 115 | #define CORE_PIN8_BIT 3 |
| 116 | #define CORE_PIN9_BIT 3 |
| 117 | #define CORE_PIN10_BIT 4 |
| 118 | #define CORE_PIN11_BIT 6 |
| 119 | #define CORE_PIN12_BIT 7 |
| 120 | #define CORE_PIN13_BIT 5 |
| 121 | #define CORE_PIN14_BIT 1 |
| 122 | #define CORE_PIN15_BIT 0 |
| 123 | #define CORE_PIN16_BIT 0 |
| 124 | #define CORE_PIN17_BIT 1 |
| 125 | #define CORE_PIN18_BIT 3 |
| 126 | #define CORE_PIN19_BIT 2 |
| 127 | #define CORE_PIN20_BIT 5 |
| 128 | #define CORE_PIN21_BIT 6 |
| 129 | #define CORE_PIN22_BIT 1 |
| 130 | #define CORE_PIN23_BIT 2 |
| 131 | #define CORE_PIN24_BIT 5 |
| 132 | #define CORE_PIN25_BIT 19 |
| 133 | #define CORE_PIN26_BIT 1 |
| 134 | #define CORE_PIN27_BIT 9 |
| 135 | #define CORE_PIN28_BIT 8 |
| 136 | #define CORE_PIN29_BIT 10 |
| 137 | #define CORE_PIN30_BIT 11 |
| 138 | #define CORE_PIN31_BIT 0 |
| 139 | #define CORE_PIN32_BIT 18 |
| 140 | #define CORE_PIN33_BIT 4 |
| 141 | |
| 142 | #define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) |
| 143 | #define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) |
| 144 | #define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT)) |
| 145 | #define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT)) |
| 146 | #define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT)) |
| 147 | #define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT)) |
| 148 | #define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT)) |
| 149 | #define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT)) |
| 150 | #define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT)) |
| 151 | #define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT)) |
| 152 | #define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT)) |
| 153 | #define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT)) |
| 154 | #define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT)) |
| 155 | #define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT)) |
| 156 | #define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT)) |
| 157 | #define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT)) |
| 158 | #define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT)) |
| 159 | #define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT)) |
| 160 | #define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT)) |
| 161 | #define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT)) |
| 162 | #define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT)) |
| 163 | #define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT)) |
| 164 | #define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT)) |
| 165 | #define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT)) |
| 166 | #define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT)) |
| 167 | #define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT)) |
| 168 | #define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT)) |
| 169 | #define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT)) |
| 170 | #define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT)) |
| 171 | #define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT)) |
| 172 | #define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT)) |
| 173 | #define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT)) |
| 174 | #define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT)) |
| 175 | #define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT)) |
| 176 | |
| 177 | #define CORE_PIN0_PORTREG GPIOB_PDOR |
| 178 | #define CORE_PIN1_PORTREG GPIOB_PDOR |
| 179 | #define CORE_PIN2_PORTREG GPIOD_PDOR |
| 180 | #define CORE_PIN3_PORTREG GPIOA_PDOR |
| 181 | #define CORE_PIN4_PORTREG GPIOA_PDOR |
| 182 | #define CORE_PIN5_PORTREG GPIOD_PDOR |
| 183 | #define CORE_PIN6_PORTREG GPIOD_PDOR |
| 184 | #define CORE_PIN7_PORTREG GPIOD_PDOR |
| 185 | #define CORE_PIN8_PORTREG GPIOD_PDOR |
| 186 | #define CORE_PIN9_PORTREG GPIOC_PDOR |
| 187 | #define CORE_PIN10_PORTREG GPIOC_PDOR |
| 188 | #define CORE_PIN11_PORTREG GPIOC_PDOR |
| 189 | #define CORE_PIN12_PORTREG GPIOC_PDOR |
| 190 | #define CORE_PIN13_PORTREG GPIOC_PDOR |
| 191 | #define CORE_PIN14_PORTREG GPIOD_PDOR |
| 192 | #define CORE_PIN15_PORTREG GPIOC_PDOR |
| 193 | #define CORE_PIN16_PORTREG GPIOB_PDOR |
| 194 | #define CORE_PIN17_PORTREG GPIOB_PDOR |
| 195 | #define CORE_PIN18_PORTREG GPIOB_PDOR |
| 196 | #define CORE_PIN19_PORTREG GPIOB_PDOR |
| 197 | #define CORE_PIN20_PORTREG GPIOD_PDOR |
| 198 | #define CORE_PIN21_PORTREG GPIOD_PDOR |
| 199 | #define CORE_PIN22_PORTREG GPIOC_PDOR |
| 200 | #define CORE_PIN23_PORTREG GPIOC_PDOR |
| 201 | #define CORE_PIN24_PORTREG GPIOA_PDOR |
| 202 | #define CORE_PIN25_PORTREG GPIOB_PDOR |
| 203 | #define CORE_PIN26_PORTREG GPIOE_PDOR |
| 204 | #define CORE_PIN27_PORTREG GPIOC_PDOR |
| 205 | #define CORE_PIN28_PORTREG GPIOC_PDOR |
| 206 | #define CORE_PIN29_PORTREG GPIOC_PDOR |
| 207 | #define CORE_PIN30_PORTREG GPIOC_PDOR |
| 208 | #define CORE_PIN31_PORTREG GPIOE_PDOR |
| 209 | #define CORE_PIN32_PORTREG GPIOB_PDOR |
| 210 | #define CORE_PIN33_PORTREG GPIOA_PDOR |
| 211 | |
| 212 | #define CORE_PIN0_PORTSET GPIOB_PSOR |
| 213 | #define CORE_PIN1_PORTSET GPIOB_PSOR |
| 214 | #define CORE_PIN2_PORTSET GPIOD_PSOR |
| 215 | #define CORE_PIN3_PORTSET GPIOA_PSOR |
| 216 | #define CORE_PIN4_PORTSET GPIOA_PSOR |
| 217 | #define CORE_PIN5_PORTSET GPIOD_PSOR |
| 218 | #define CORE_PIN6_PORTSET GPIOD_PSOR |
| 219 | #define CORE_PIN7_PORTSET GPIOD_PSOR |
| 220 | #define CORE_PIN8_PORTSET GPIOD_PSOR |
| 221 | #define CORE_PIN9_PORTSET GPIOC_PSOR |
| 222 | #define CORE_PIN10_PORTSET GPIOC_PSOR |
| 223 | #define CORE_PIN11_PORTSET GPIOC_PSOR |
| 224 | #define CORE_PIN12_PORTSET GPIOC_PSOR |
| 225 | #define CORE_PIN13_PORTSET GPIOC_PSOR |
| 226 | #define CORE_PIN14_PORTSET GPIOD_PSOR |
| 227 | #define CORE_PIN15_PORTSET GPIOC_PSOR |
| 228 | #define CORE_PIN16_PORTSET GPIOB_PSOR |
| 229 | #define CORE_PIN17_PORTSET GPIOB_PSOR |
| 230 | #define CORE_PIN18_PORTSET GPIOB_PSOR |
| 231 | #define CORE_PIN19_PORTSET GPIOB_PSOR |
| 232 | #define CORE_PIN20_PORTSET GPIOD_PSOR |
| 233 | #define CORE_PIN21_PORTSET GPIOD_PSOR |
| 234 | #define CORE_PIN22_PORTSET GPIOC_PSOR |
| 235 | #define CORE_PIN23_PORTSET GPIOC_PSOR |
| 236 | #define CORE_PIN24_PORTSET GPIOA_PSOR |
| 237 | #define CORE_PIN25_PORTSET GPIOB_PSOR |
| 238 | #define CORE_PIN26_PORTSET GPIOE_PSOR |
| 239 | #define CORE_PIN27_PORTSET GPIOC_PSOR |
| 240 | #define CORE_PIN28_PORTSET GPIOC_PSOR |
| 241 | #define CORE_PIN29_PORTSET GPIOC_PSOR |
| 242 | #define CORE_PIN30_PORTSET GPIOC_PSOR |
| 243 | #define CORE_PIN31_PORTSET GPIOE_PSOR |
| 244 | #define CORE_PIN32_PORTSET GPIOB_PSOR |
| 245 | #define CORE_PIN33_PORTSET GPIOA_PSOR |
| 246 | |
| 247 | #define CORE_PIN0_PORTCLEAR GPIOB_PCOR |
| 248 | #define CORE_PIN1_PORTCLEAR GPIOB_PCOR |
| 249 | #define CORE_PIN2_PORTCLEAR GPIOD_PCOR |
| 250 | #define CORE_PIN3_PORTCLEAR GPIOA_PCOR |
| 251 | #define CORE_PIN4_PORTCLEAR GPIOA_PCOR |
| 252 | #define CORE_PIN5_PORTCLEAR GPIOD_PCOR |
| 253 | #define CORE_PIN6_PORTCLEAR GPIOD_PCOR |
| 254 | #define CORE_PIN7_PORTCLEAR GPIOD_PCOR |
| 255 | #define CORE_PIN8_PORTCLEAR GPIOD_PCOR |
| 256 | #define CORE_PIN9_PORTCLEAR GPIOC_PCOR |
| 257 | #define CORE_PIN10_PORTCLEAR GPIOC_PCOR |
| 258 | #define CORE_PIN11_PORTCLEAR GPIOC_PCOR |
| 259 | #define CORE_PIN12_PORTCLEAR GPIOC_PCOR |
| 260 | #define CORE_PIN13_PORTCLEAR GPIOC_PCOR |
| 261 | #define CORE_PIN14_PORTCLEAR GPIOD_PCOR |
| 262 | #define CORE_PIN15_PORTCLEAR GPIOC_PCOR |
| 263 | #define CORE_PIN16_PORTCLEAR GPIOB_PCOR |
| 264 | #define CORE_PIN17_PORTCLEAR GPIOB_PCOR |
| 265 | #define CORE_PIN18_PORTCLEAR GPIOB_PCOR |
| 266 | #define CORE_PIN19_PORTCLEAR GPIOB_PCOR |
| 267 | #define CORE_PIN20_PORTCLEAR GPIOD_PCOR |
| 268 | #define CORE_PIN21_PORTCLEAR GPIOD_PCOR |
| 269 | #define CORE_PIN22_PORTCLEAR GPIOC_PCOR |
| 270 | #define CORE_PIN23_PORTCLEAR GPIOC_PCOR |
| 271 | #define CORE_PIN24_PORTCLEAR GPIOA_PCOR |
| 272 | #define CORE_PIN25_PORTCLEAR GPIOB_PCOR |
| 273 | #define CORE_PIN26_PORTCLEAR GPIOE_PCOR |
| 274 | #define CORE_PIN27_PORTCLEAR GPIOC_PCOR |
| 275 | #define CORE_PIN28_PORTCLEAR GPIOC_PCOR |
| 276 | #define CORE_PIN29_PORTCLEAR GPIOC_PCOR |
| 277 | #define CORE_PIN30_PORTCLEAR GPIOC_PCOR |
| 278 | #define CORE_PIN31_PORTCLEAR GPIOE_PCOR |
| 279 | #define CORE_PIN32_PORTCLEAR GPIOB_PCOR |
| 280 | #define CORE_PIN33_PORTCLEAR GPIOA_PCOR |
| 281 | |
| 282 | #define CORE_PIN0_DDRREG GPIOB_PDDR |
| 283 | #define CORE_PIN1_DDRREG GPIOB_PDDR |
| 284 | #define CORE_PIN2_DDRREG GPIOD_PDDR |
| 285 | #define CORE_PIN3_DDRREG GPIOA_PDDR |
| 286 | #define CORE_PIN4_DDRREG GPIOA_PDDR |
| 287 | #define CORE_PIN5_DDRREG GPIOD_PDDR |
| 288 | #define CORE_PIN6_DDRREG GPIOD_PDDR |
| 289 | #define CORE_PIN7_DDRREG GPIOD_PDDR |
| 290 | #define CORE_PIN8_DDRREG GPIOD_PDDR |
| 291 | #define CORE_PIN9_DDRREG GPIOC_PDDR |
| 292 | #define CORE_PIN10_DDRREG GPIOC_PDDR |
| 293 | #define CORE_PIN11_DDRREG GPIOC_PDDR |
| 294 | #define CORE_PIN12_DDRREG GPIOC_PDDR |
| 295 | #define CORE_PIN13_DDRREG GPIOC_PDDR |
| 296 | #define CORE_PIN14_DDRREG GPIOD_PDDR |
| 297 | #define CORE_PIN15_DDRREG GPIOC_PDDR |
| 298 | #define CORE_PIN16_DDRREG GPIOB_PDDR |
| 299 | #define CORE_PIN17_DDRREG GPIOB_PDDR |
| 300 | #define CORE_PIN18_DDRREG GPIOB_PDDR |
| 301 | #define CORE_PIN19_DDRREG GPIOB_PDDR |
| 302 | #define CORE_PIN20_DDRREG GPIOD_PDDR |
| 303 | #define CORE_PIN21_DDRREG GPIOD_PDDR |
| 304 | #define CORE_PIN22_DDRREG GPIOC_PDDR |
| 305 | #define CORE_PIN23_DDRREG GPIOC_PDDR |
| 306 | #define CORE_PIN24_DDRREG GPIOA_PDDR |
| 307 | #define CORE_PIN25_DDRREG GPIOB_PDDR |
| 308 | #define CORE_PIN26_DDRREG GPIOE_PDDR |
| 309 | #define CORE_PIN27_DDRREG GPIOC_PDDR |
| 310 | #define CORE_PIN28_DDRREG GPIOC_PDDR |
| 311 | #define CORE_PIN29_DDRREG GPIOC_PDDR |
| 312 | #define CORE_PIN30_DDRREG GPIOC_PDDR |
| 313 | #define CORE_PIN31_DDRREG GPIOE_PDDR |
| 314 | #define CORE_PIN32_DDRREG GPIOB_PDDR |
| 315 | #define CORE_PIN33_DDRREG GPIOA_PDDR |
| 316 | |
| 317 | #define CORE_PIN0_PINREG GPIOB_PDIR |
| 318 | #define CORE_PIN1_PINREG GPIOB_PDIR |
| 319 | #define CORE_PIN2_PINREG GPIOD_PDIR |
| 320 | #define CORE_PIN3_PINREG GPIOA_PDIR |
| 321 | #define CORE_PIN4_PINREG GPIOA_PDIR |
| 322 | #define CORE_PIN5_PINREG GPIOD_PDIR |
| 323 | #define CORE_PIN6_PINREG GPIOD_PDIR |
| 324 | #define CORE_PIN7_PINREG GPIOD_PDIR |
| 325 | #define CORE_PIN8_PINREG GPIOD_PDIR |
| 326 | #define CORE_PIN9_PINREG GPIOC_PDIR |
| 327 | #define CORE_PIN10_PINREG GPIOC_PDIR |
| 328 | #define CORE_PIN11_PINREG GPIOC_PDIR |
| 329 | #define CORE_PIN12_PINREG GPIOC_PDIR |
| 330 | #define CORE_PIN13_PINREG GPIOC_PDIR |
| 331 | #define CORE_PIN14_PINREG GPIOD_PDIR |
| 332 | #define CORE_PIN15_PINREG GPIOC_PDIR |
| 333 | #define CORE_PIN16_PINREG GPIOB_PDIR |
| 334 | #define CORE_PIN17_PINREG GPIOB_PDIR |
| 335 | #define CORE_PIN18_PINREG GPIOB_PDIR |
| 336 | #define CORE_PIN19_PINREG GPIOB_PDIR |
| 337 | #define CORE_PIN20_PINREG GPIOD_PDIR |
| 338 | #define CORE_PIN21_PINREG GPIOD_PDIR |
| 339 | #define CORE_PIN22_PINREG GPIOC_PDIR |
| 340 | #define CORE_PIN23_PINREG GPIOC_PDIR |
| 341 | #define CORE_PIN24_PINREG GPIOA_PDIR |
| 342 | #define CORE_PIN25_PINREG GPIOB_PDIR |
| 343 | #define CORE_PIN26_PINREG GPIOE_PDIR |
| 344 | #define CORE_PIN27_PINREG GPIOC_PDIR |
| 345 | #define CORE_PIN28_PINREG GPIOC_PDIR |
| 346 | #define CORE_PIN29_PINREG GPIOC_PDIR |
| 347 | #define CORE_PIN30_PINREG GPIOC_PDIR |
| 348 | #define CORE_PIN31_PINREG GPIOE_PDIR |
| 349 | #define CORE_PIN32_PINREG GPIOB_PDIR |
| 350 | #define CORE_PIN33_PINREG GPIOA_PDIR |
| 351 | |
| 352 | #define CORE_PIN0_CONFIG PORTB_PCR16 |
| 353 | #define CORE_PIN1_CONFIG PORTB_PCR17 |
| 354 | #define CORE_PIN2_CONFIG PORTD_PCR0 |
| 355 | #define CORE_PIN3_CONFIG PORTA_PCR12 |
| 356 | #define CORE_PIN4_CONFIG PORTA_PCR13 |
| 357 | #define CORE_PIN5_CONFIG PORTD_PCR7 |
| 358 | #define CORE_PIN6_CONFIG PORTD_PCR4 |
| 359 | #define CORE_PIN7_CONFIG PORTD_PCR2 |
| 360 | #define CORE_PIN8_CONFIG PORTD_PCR3 |
| 361 | #define CORE_PIN9_CONFIG PORTC_PCR3 |
| 362 | #define CORE_PIN10_CONFIG PORTC_PCR4 |
| 363 | #define CORE_PIN11_CONFIG PORTC_PCR6 |
| 364 | #define CORE_PIN12_CONFIG PORTC_PCR7 |
| 365 | #define CORE_PIN13_CONFIG PORTC_PCR5 |
| 366 | #define CORE_PIN14_CONFIG PORTD_PCR1 |
| 367 | #define CORE_PIN15_CONFIG PORTC_PCR0 |
| 368 | #define CORE_PIN16_CONFIG PORTB_PCR0 |
| 369 | #define CORE_PIN17_CONFIG PORTB_PCR1 |
| 370 | #define CORE_PIN18_CONFIG PORTB_PCR3 |
| 371 | #define CORE_PIN19_CONFIG PORTB_PCR2 |
| 372 | #define CORE_PIN20_CONFIG PORTD_PCR5 |
| 373 | #define CORE_PIN21_CONFIG PORTD_PCR6 |
| 374 | #define CORE_PIN22_CONFIG PORTC_PCR1 |
| 375 | #define CORE_PIN23_CONFIG PORTC_PCR2 |
| 376 | #define CORE_PIN24_CONFIG PORTA_PCR5 |
| 377 | #define CORE_PIN25_CONFIG PORTB_PCR19 |
| 378 | #define CORE_PIN26_CONFIG PORTE_PCR1 |
| 379 | #define CORE_PIN27_CONFIG PORTC_PCR9 |
| 380 | #define CORE_PIN28_CONFIG PORTC_PCR8 |
| 381 | #define CORE_PIN29_CONFIG PORTC_PCR10 |
| 382 | #define CORE_PIN30_CONFIG PORTC_PCR11 |
| 383 | #define CORE_PIN31_CONFIG PORTE_PCR0 |
| 384 | #define CORE_PIN32_CONFIG PORTB_PCR18 |
| 385 | #define CORE_PIN33_CONFIG PORTA_PCR4 |
| 386 | |
| 387 | #define CORE_ADC0_PIN 14 |
| 388 | #define CORE_ADC1_PIN 15 |
| 389 | #define CORE_ADC2_PIN 16 |
| 390 | #define CORE_ADC3_PIN 17 |
| 391 | #define CORE_ADC4_PIN 18 |
| 392 | #define CORE_ADC5_PIN 19 |
| 393 | #define CORE_ADC6_PIN 20 |
| 394 | #define CORE_ADC7_PIN 21 |
| 395 | #define CORE_ADC8_PIN 22 |
| 396 | #define CORE_ADC9_PIN 23 |
| 397 | #define CORE_ADC10_PIN 34 |
| 398 | #define CORE_ADC11_PIN 35 |
| 399 | #define CORE_ADC12_PIN 36 |
| 400 | #define CORE_ADC13_PIN 37 |
| 401 | |
| 402 | #define CORE_RXD0_PIN 0 |
| 403 | #define CORE_TXD0_PIN 1 |
| 404 | #define CORE_RXD1_PIN 9 |
| 405 | #define CORE_TXD1_PIN 10 |
| 406 | #define CORE_RXD2_PIN 7 |
| 407 | #define CORE_TXD2_PIN 8 |
| 408 | |
| 409 | #define CORE_INT0_PIN 0 |
| 410 | #define CORE_INT1_PIN 1 |
| 411 | #define CORE_INT2_PIN 2 |
| 412 | #define CORE_INT3_PIN 3 |
| 413 | #define CORE_INT4_PIN 4 |
| 414 | #define CORE_INT5_PIN 5 |
| 415 | #define CORE_INT6_PIN 6 |
| 416 | #define CORE_INT7_PIN 7 |
| 417 | #define CORE_INT8_PIN 8 |
| 418 | #define CORE_INT9_PIN 9 |
| 419 | #define CORE_INT10_PIN 10 |
| 420 | #define CORE_INT11_PIN 11 |
| 421 | #define CORE_INT12_PIN 12 |
| 422 | #define CORE_INT13_PIN 13 |
| 423 | #define CORE_INT14_PIN 14 |
| 424 | #define CORE_INT15_PIN 15 |
| 425 | #define CORE_INT16_PIN 16 |
| 426 | #define CORE_INT17_PIN 17 |
| 427 | #define CORE_INT18_PIN 18 |
| 428 | #define CORE_INT19_PIN 19 |
| 429 | #define CORE_INT20_PIN 20 |
| 430 | #define CORE_INT21_PIN 21 |
| 431 | #define CORE_INT22_PIN 22 |
| 432 | #define CORE_INT23_PIN 23 |
| 433 | #define CORE_INT24_PIN 24 |
| 434 | #define CORE_INT25_PIN 25 |
| 435 | #define CORE_INT26_PIN 26 |
| 436 | #define CORE_INT27_PIN 27 |
| 437 | #define CORE_INT28_PIN 28 |
| 438 | #define CORE_INT29_PIN 29 |
| 439 | #define CORE_INT30_PIN 30 |
| 440 | #define CORE_INT31_PIN 31 |
| 441 | #define CORE_INT32_PIN 32 |
| 442 | #define CORE_INT33_PIN 33 |
| 443 | #define CORE_INT_EVERY_PIN 1 |
| 444 | |
| 445 | |
| 446 | |
| 447 | |
| 448 | #ifdef __cplusplus |
| 449 | extern "C" { |
| 450 | #endif |
| 451 | |
| 452 | void digitalWrite(uint8_t pin, uint8_t val); |
| 453 | static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused)); |
| 454 | static inline void digitalWriteFast(uint8_t pin, uint8_t val) |
| 455 | { |
| 456 | if (__builtin_constant_p(pin)) { |
| 457 | if (val) { |
| 458 | if (pin == 0) { |
| 459 | CORE_PIN0_PORTSET = CORE_PIN0_BITMASK; |
| 460 | } else if (pin == 1) { |
| 461 | CORE_PIN1_PORTSET = CORE_PIN1_BITMASK; |
| 462 | } else if (pin == 2) { |
| 463 | CORE_PIN2_PORTSET = CORE_PIN2_BITMASK; |
| 464 | } else if (pin == 3) { |
| 465 | CORE_PIN3_PORTSET = CORE_PIN3_BITMASK; |
| 466 | } else if (pin == 4) { |
| 467 | CORE_PIN4_PORTSET = CORE_PIN4_BITMASK; |
| 468 | } else if (pin == 5) { |
| 469 | CORE_PIN5_PORTSET = CORE_PIN5_BITMASK; |
| 470 | } else if (pin == 6) { |
| 471 | CORE_PIN6_PORTSET = CORE_PIN6_BITMASK; |
| 472 | } else if (pin == 7) { |
| 473 | CORE_PIN7_PORTSET = CORE_PIN7_BITMASK; |
| 474 | } else if (pin == 8) { |
| 475 | CORE_PIN8_PORTSET = CORE_PIN8_BITMASK; |
| 476 | } else if (pin == 9) { |
| 477 | CORE_PIN9_PORTSET = CORE_PIN9_BITMASK; |
| 478 | } else if (pin == 10) { |
| 479 | CORE_PIN10_PORTSET = CORE_PIN10_BITMASK; |
| 480 | } else if (pin == 11) { |
| 481 | CORE_PIN11_PORTSET = CORE_PIN11_BITMASK; |
| 482 | } else if (pin == 12) { |
| 483 | CORE_PIN12_PORTSET = CORE_PIN12_BITMASK; |
| 484 | } else if (pin == 13) { |
| 485 | CORE_PIN13_PORTSET = CORE_PIN13_BITMASK; |
| 486 | } else if (pin == 14) { |
| 487 | CORE_PIN14_PORTSET = CORE_PIN14_BITMASK; |
| 488 | } else if (pin == 15) { |
| 489 | CORE_PIN15_PORTSET = CORE_PIN15_BITMASK; |
| 490 | } else if (pin == 16) { |
| 491 | CORE_PIN16_PORTSET = CORE_PIN16_BITMASK; |
| 492 | } else if (pin == 17) { |
| 493 | CORE_PIN17_PORTSET = CORE_PIN17_BITMASK; |
| 494 | } else if (pin == 18) { |
| 495 | CORE_PIN18_PORTSET = CORE_PIN18_BITMASK; |
| 496 | } else if (pin == 19) { |
| 497 | CORE_PIN19_PORTSET = CORE_PIN19_BITMASK; |
| 498 | } else if (pin == 20) { |
| 499 | CORE_PIN20_PORTSET = CORE_PIN20_BITMASK; |
| 500 | } else if (pin == 21) { |
| 501 | CORE_PIN21_PORTSET = CORE_PIN21_BITMASK; |
| 502 | } else if (pin == 22) { |
| 503 | CORE_PIN22_PORTSET = CORE_PIN22_BITMASK; |
| 504 | } else if (pin == 23) { |
| 505 | CORE_PIN23_PORTSET = CORE_PIN23_BITMASK; |
| 506 | } else if (pin == 24) { |
| 507 | CORE_PIN24_PORTSET = CORE_PIN24_BITMASK; |
| 508 | } else if (pin == 25) { |
| 509 | CORE_PIN25_PORTSET = CORE_PIN25_BITMASK; |
| 510 | } else if (pin == 26) { |
| 511 | CORE_PIN26_PORTSET = CORE_PIN26_BITMASK; |
| 512 | } else if (pin == 27) { |
| 513 | CORE_PIN27_PORTSET = CORE_PIN27_BITMASK; |
| 514 | } else if (pin == 28) { |
| 515 | CORE_PIN28_PORTSET = CORE_PIN28_BITMASK; |
| 516 | } else if (pin == 29) { |
| 517 | CORE_PIN29_PORTSET = CORE_PIN29_BITMASK; |
| 518 | } else if (pin == 30) { |
| 519 | CORE_PIN30_PORTSET = CORE_PIN30_BITMASK; |
| 520 | } else if (pin == 31) { |
| 521 | CORE_PIN31_PORTSET = CORE_PIN31_BITMASK; |
| 522 | } else if (pin == 32) { |
| 523 | CORE_PIN32_PORTSET = CORE_PIN32_BITMASK; |
| 524 | } else if (pin == 33) { |
| 525 | CORE_PIN33_PORTSET = CORE_PIN33_BITMASK; |
| 526 | } |
| 527 | } else { |
| 528 | if (pin == 0) { |
| 529 | CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK; |
| 530 | } else if (pin == 1) { |
| 531 | CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK; |
| 532 | } else if (pin == 2) { |
| 533 | CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK; |
| 534 | } else if (pin == 3) { |
| 535 | CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK; |
| 536 | } else if (pin == 4) { |
| 537 | CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK; |
| 538 | } else if (pin == 5) { |
| 539 | CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK; |
| 540 | } else if (pin == 6) { |
| 541 | CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK; |
| 542 | } else if (pin == 7) { |
| 543 | CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK; |
| 544 | } else if (pin == 8) { |
| 545 | CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK; |
| 546 | } else if (pin == 9) { |
| 547 | CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK; |
| 548 | } else if (pin == 10) { |
| 549 | CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK; |
| 550 | } else if (pin == 11) { |
| 551 | CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK; |
| 552 | } else if (pin == 12) { |
| 553 | CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK; |
| 554 | } else if (pin == 13) { |
| 555 | CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK; |
| 556 | } else if (pin == 14) { |
| 557 | CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK; |
| 558 | } else if (pin == 15) { |
| 559 | CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK; |
| 560 | } else if (pin == 16) { |
| 561 | CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK; |
| 562 | } else if (pin == 17) { |
| 563 | CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK; |
| 564 | } else if (pin == 18) { |
| 565 | CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK; |
| 566 | } else if (pin == 19) { |
| 567 | CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK; |
| 568 | } else if (pin == 20) { |
| 569 | CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK; |
| 570 | } else if (pin == 21) { |
| 571 | CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK; |
| 572 | } else if (pin == 22) { |
| 573 | CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK; |
| 574 | } else if (pin == 23) { |
| 575 | CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK; |
| 576 | } else if (pin == 24) { |
| 577 | CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK; |
| 578 | } else if (pin == 25) { |
| 579 | CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK; |
| 580 | } else if (pin == 26) { |
| 581 | CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK; |
| 582 | } else if (pin == 27) { |
| 583 | CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK; |
| 584 | } else if (pin == 28) { |
| 585 | CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK; |
| 586 | } else if (pin == 29) { |
| 587 | CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK; |
| 588 | } else if (pin == 30) { |
| 589 | CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK; |
| 590 | } else if (pin == 31) { |
| 591 | CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK; |
| 592 | } else if (pin == 32) { |
| 593 | CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK; |
| 594 | } else if (pin == 33) { |
| 595 | CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK; |
| 596 | } |
| 597 | } |
| 598 | } else { |
| 599 | if (val) { |
| 600 | *portSetRegister(pin) = 1; |
| 601 | } else { |
| 602 | *portClearRegister(pin) = 1; |
| 603 | } |
| 604 | } |
| 605 | } |
| 606 | |
| 607 | uint8_t digitalRead(uint8_t pin); |
| 608 | static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused)); |
| 609 | static inline uint8_t digitalReadFast(uint8_t pin) |
| 610 | { |
| 611 | if (__builtin_constant_p(pin)) { |
| 612 | if (pin == 0) { |
| 613 | return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0; |
| 614 | } else if (pin == 1) { |
| 615 | return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0; |
| 616 | } else if (pin == 2) { |
| 617 | return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0; |
| 618 | } else if (pin == 3) { |
| 619 | return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0; |
| 620 | } else if (pin == 4) { |
| 621 | return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0; |
| 622 | } else if (pin == 5) { |
| 623 | return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0; |
| 624 | } else if (pin == 6) { |
| 625 | return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0; |
| 626 | } else if (pin == 7) { |
| 627 | return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0; |
| 628 | } else if (pin == 8) { |
| 629 | return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0; |
| 630 | } else if (pin == 9) { |
| 631 | return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0; |
| 632 | } else if (pin == 10) { |
| 633 | return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0; |
| 634 | } else if (pin == 11) { |
| 635 | return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0; |
| 636 | } else if (pin == 12) { |
| 637 | return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0; |
| 638 | } else if (pin == 13) { |
| 639 | return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0; |
| 640 | } else if (pin == 14) { |
| 641 | return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0; |
| 642 | } else if (pin == 15) { |
| 643 | return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0; |
| 644 | } else if (pin == 16) { |
| 645 | return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0; |
| 646 | } else if (pin == 17) { |
| 647 | return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0; |
| 648 | } else if (pin == 18) { |
| 649 | return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0; |
| 650 | } else if (pin == 19) { |
| 651 | return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0; |
| 652 | } else if (pin == 20) { |
| 653 | return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0; |
| 654 | } else if (pin == 21) { |
| 655 | return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0; |
| 656 | } else if (pin == 22) { |
| 657 | return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0; |
| 658 | } else if (pin == 23) { |
| 659 | return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0; |
| 660 | } else if (pin == 24) { |
| 661 | return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0; |
| 662 | } else if (pin == 25) { |
| 663 | return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0; |
| 664 | } else if (pin == 26) { |
| 665 | return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0; |
| 666 | } else if (pin == 27) { |
| 667 | return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0; |
| 668 | } else if (pin == 28) { |
| 669 | return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0; |
| 670 | } else if (pin == 29) { |
| 671 | return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0; |
| 672 | } else if (pin == 30) { |
| 673 | return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0; |
| 674 | } else if (pin == 31) { |
| 675 | return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0; |
| 676 | } else if (pin == 32) { |
| 677 | return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0; |
| 678 | } else if (pin == 33) { |
| 679 | return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0; |
| 680 | } else { |
| 681 | return 0; |
| 682 | } |
| 683 | } else { |
| 684 | return *portInputRegister(pin); |
| 685 | } |
| 686 | } |
| 687 | |
| 688 | |
| 689 | void pinMode(uint8_t pin, uint8_t mode); |
| 690 | void init_pins(void); |
| 691 | void analogWrite(uint8_t pin, int val); |
| 692 | void analogWriteRes(uint32_t bits); |
| 693 | static inline void analogWriteResolution(uint32_t bits) { analogWriteRes(bits); } |
| 694 | void analogWriteFrequency(uint8_t pin, uint32_t frequency); |
| 695 | void analogWriteDAC0(int val); |
| a773ac06 |
696 | #ifdef __cplusplus |
| 697 | void attachInterruptVector(IRQ_NUMBER_t irq, void (*function)(void)); |
| 698 | #else |
| 699 | void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)(void)); |
| 700 | #endif |
| 35f00b6c |
701 | void attachInterrupt(uint8_t pin, void (*function)(void), int mode); |
| 702 | void detachInterrupt(uint8_t pin); |
| 703 | void _init_Teensyduino_internal_(void); |
| 704 | |
| 705 | int analogRead(uint8_t pin); |
| 706 | void analogReference(uint8_t type); |
| 707 | void analogReadRes(unsigned int bits); |
| 708 | static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); } |
| 709 | void analogReadAveraging(unsigned int num); |
| 710 | void analog_init(void); |
| 711 | |
| 712 | #define DEFAULT 0 |
| 713 | #define INTERNAL 2 |
| 714 | #define INTERNAL1V2 2 |
| 715 | #define INTERNAL1V1 2 |
| 716 | #define EXTERNAL 0 |
| 717 | |
| 718 | int touchRead(uint8_t pin); |
| 719 | |
| 720 | |
| 721 | static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused)); |
| 722 | extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline)); |
| 723 | extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline)); |
| 724 | extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline)); |
| 725 | |
| 726 | static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) |
| 727 | { |
| 728 | if (__builtin_constant_p(bitOrder)) { |
| 729 | if (bitOrder == LSBFIRST) { |
| 730 | shiftOut_lsbFirst(dataPin, clockPin, value); |
| 731 | } else { |
| 732 | shiftOut_msbFirst(dataPin, clockPin, value); |
| 733 | } |
| 734 | } else { |
| 735 | _shiftOut(dataPin, clockPin, bitOrder, value); |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused)); |
| 740 | extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline)); |
| 741 | extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline)); |
| 742 | extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline)); |
| 743 | |
| 744 | static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) |
| 745 | { |
| 746 | if (__builtin_constant_p(bitOrder)) { |
| 747 | if (bitOrder == LSBFIRST) { |
| 748 | return shiftIn_lsbFirst(dataPin, clockPin); |
| 749 | } else { |
| 750 | return shiftIn_msbFirst(dataPin, clockPin); |
| 751 | } |
| 752 | } else { |
| 753 | return _shiftIn(dataPin, clockPin, bitOrder); |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | void _reboot_Teensyduino_(void) __attribute__((noreturn)); |
| 758 | void _restart_Teensyduino_(void) __attribute__((noreturn)); |
| 759 | |
| 760 | void yield(void); |
| 761 | |
| 762 | void delay(uint32_t msec); |
| 763 | |
| 764 | extern volatile uint32_t systick_millis_count; |
| 765 | |
| 766 | static inline uint32_t millis(void) __attribute__((always_inline, unused)); |
| 767 | static inline uint32_t millis(void) |
| 768 | { |
| 769 | volatile uint32_t ret = systick_millis_count; // single aligned 32 bit is atomic; |
| 770 | return ret; |
| 771 | } |
| 772 | |
| 773 | uint32_t micros(void); |
| 774 | |
| 775 | static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused)); |
| 776 | static inline void delayMicroseconds(uint32_t usec) |
| 777 | { |
| a773ac06 |
778 | #if F_CPU == 168000000 |
| 779 | uint32_t n = usec * 56; |
| 780 | #elif F_CPU == 144000000 |
| 781 | uint32_t n = usec * 48; |
| 782 | #elif F_CPU == 120000000 |
| 783 | uint32_t n = usec * 40; |
| 784 | #elif F_CPU == 96000000 |
| 35f00b6c |
785 | uint32_t n = usec << 5; |
| a773ac06 |
786 | #elif F_CPU == 72000000 |
| 787 | uint32_t n = usec * 24; |
| 35f00b6c |
788 | #elif F_CPU == 48000000 |
| 789 | uint32_t n = usec << 4; |
| 790 | #elif F_CPU == 24000000 |
| 791 | uint32_t n = usec << 3; |
| a773ac06 |
792 | #elif F_CPU == 16000000 |
| 793 | uint32_t n = usec << 2; |
| 794 | #elif F_CPU == 8000000 |
| 795 | uint32_t n = usec << 1; |
| 796 | #elif F_CPU == 4000000 |
| 797 | uint32_t n = usec; |
| 798 | #elif F_CPU == 2000000 |
| 799 | uint32_t n = usec >> 1; |
| 35f00b6c |
800 | #endif |
| a773ac06 |
801 | // changed because a delay of 1 micro Sec @ 2MHz will be 0 |
| 802 | if (n == 0) return; |
| 803 | __asm__ volatile( |
| 35f00b6c |
804 | "L_%=_delayMicroseconds:" "\n\t" |
| a773ac06 |
805 | #if F_CPU < 24000000 |
| 806 | "nop" "\n\t" |
| 807 | #endif |
| 35f00b6c |
808 | "subs %0, #1" "\n\t" |
| 809 | "bne L_%=_delayMicroseconds" "\n" |
| 810 | : "+r" (n) : |
| 811 | ); |
| 812 | } |
| 813 | |
| 814 | #ifdef __cplusplus |
| 815 | } |
| 816 | #endif |
| 817 | |
| 818 | |
| 819 | |
| 820 | |
| 821 | |
| 822 | |
| 823 | |
| 824 | |
| 825 | #ifdef __cplusplus |
| 826 | extern "C" { |
| 827 | #endif |
| 828 | unsigned long rtc_get(void); |
| 829 | void rtc_set(unsigned long t); |
| 830 | void rtc_compensate(int adjust); |
| 831 | #ifdef __cplusplus |
| 832 | } |
| 833 | class teensy3_clock_class |
| 834 | { |
| 835 | public: |
| 836 | static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); } |
| 837 | static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); } |
| 838 | static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); } |
| 839 | }; |
| 840 | extern teensy3_clock_class Teensy3Clock; |
| 841 | #endif |
| 842 | |
| 843 | |
| 844 | |
| 845 | |
| 846 | #endif |
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