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teensy3lib: do level masking instead of disable
[teensytas.git] / teensy3 / kinetis.h
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a773ac06 1/* Teensyduino Core Library
2 * http://www.pjrc.com/teensy/
3 * Copyright (c) 2013 PJRC.COM, LLC.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * 1. The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
15 *
16 * 2. If the Software is incorporated into a build system that allows
17 * selection among a list of target devices, then similar target
18 * devices manufactured by PJRC.COM must be included in the list of
19 * target devices and selectable in the same manner.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
24 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
25 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
26 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
27 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 * SOFTWARE.
29 */
30
31#ifndef _kinetis_h_
32#define _kinetis_h_
33
34#include <stdint.h>
35
36// Teensy 3.0
37#if defined(__MK20DX128__)
38enum IRQ_NUMBER_t {
39 IRQ_DMA_CH0 = 0,
40 IRQ_DMA_CH1 = 1,
41 IRQ_DMA_CH2 = 2,
42 IRQ_DMA_CH3 = 3,
43 IRQ_DMA_ERROR = 4,
44 IRQ_FTFL_COMPLETE = 6,
45 IRQ_FTFL_COLLISION = 7,
46 IRQ_LOW_VOLTAGE = 8,
47 IRQ_LLWU = 9,
48 IRQ_WDOG = 10,
49 IRQ_I2C0 = 11,
50 IRQ_SPI0 = 12,
51 IRQ_I2S0_TX = 13,
52 IRQ_I2S0_RX = 14,
53 IRQ_UART0_LON = 15,
54 IRQ_UART0_STATUS = 16,
55 IRQ_UART0_ERROR = 17,
56 IRQ_UART1_STATUS = 18,
57 IRQ_UART1_ERROR = 19,
58 IRQ_UART2_STATUS = 20,
59 IRQ_UART2_ERROR = 21,
60 IRQ_ADC0 = 22,
61 IRQ_CMP0 = 23,
62 IRQ_CMP1 = 24,
63 IRQ_FTM0 = 25,
64 IRQ_FTM1 = 26,
65 IRQ_CMT = 27,
66 IRQ_RTC_ALARM = 28,
67 IRQ_RTC_SECOND = 29,
68 IRQ_PIT_CH0 = 30,
69 IRQ_PIT_CH1 = 31,
70 IRQ_PIT_CH2 = 32,
71 IRQ_PIT_CH3 = 33,
72 IRQ_PDB = 34,
73 IRQ_USBOTG = 35,
74 IRQ_USBDCD = 36,
75 IRQ_TSI = 37,
76 IRQ_MCG = 38,
77 IRQ_LPTMR = 39,
78 IRQ_PORTA = 40,
79 IRQ_PORTB = 41,
80 IRQ_PORTC = 42,
81 IRQ_PORTD = 43,
82 IRQ_PORTE = 44,
83 IRQ_SOFTWARE = 45
84};
85#define NVIC_NUM_INTERRUPTS 46
86#define DMA_NUM_CHANNELS 4
87#define KINETISK_UART0
88#define KINETISK_UART0_FIFO
89#define KINETISK_UART1
90#define KINETISK_UART2
91
92// Teensy 3.1
93#elif defined(__MK20DX256__)
94enum IRQ_NUMBER_t {
95 IRQ_DMA_CH0 = 0,
96 IRQ_DMA_CH1 = 1,
97 IRQ_DMA_CH2 = 2,
98 IRQ_DMA_CH3 = 3,
99 IRQ_DMA_CH4 = 4,
100 IRQ_DMA_CH5 = 5,
101 IRQ_DMA_CH6 = 6,
102 IRQ_DMA_CH7 = 7,
103 IRQ_DMA_CH8 = 8,
104 IRQ_DMA_CH9 = 9,
105 IRQ_DMA_CH10 = 10,
106 IRQ_DMA_CH11 = 11,
107 IRQ_DMA_CH12 = 12,
108 IRQ_DMA_CH13 = 13,
109 IRQ_DMA_CH14 = 14,
110 IRQ_DMA_CH15 = 15,
111 IRQ_DMA_ERROR = 16,
112 IRQ_FTFL_COMPLETE = 18,
113 IRQ_FTFL_COLLISION = 19,
114 IRQ_LOW_VOLTAGE = 20,
115 IRQ_LLWU = 21,
116 IRQ_WDOG = 22,
117 IRQ_I2C0 = 24,
118 IRQ_I2C1 = 25,
119 IRQ_SPI0 = 26,
120 IRQ_SPI1 = 27,
121 IRQ_CAN_MESSAGE = 29,
122 IRQ_CAN_BUS_OFF = 30,
123 IRQ_CAN_ERROR = 31,
124 IRQ_CAN_TX_WARN = 32,
125 IRQ_CAN_RX_WARN = 33,
126 IRQ_CAN_WAKEUP = 34,
127 IRQ_I2S0_TX = 35,
128 IRQ_I2S0_RX = 36,
129 IRQ_UART0_LON = 44,
130 IRQ_UART0_STATUS = 45,
131 IRQ_UART0_ERROR = 46,
132 IRQ_UART1_STATUS = 47,
133 IRQ_UART1_ERROR = 48,
134 IRQ_UART2_STATUS = 49,
135 IRQ_UART2_ERROR = 50,
136 IRQ_ADC0 = 57,
137 IRQ_ADC1 = 58,
138 IRQ_CMP0 = 59,
139 IRQ_CMP1 = 60,
140 IRQ_CMP2 = 61,
141 IRQ_FTM0 = 62,
142 IRQ_FTM1 = 63,
143 IRQ_FTM2 = 64,
144 IRQ_CMT = 65,
145 IRQ_RTC_ALARM = 66,
146 IRQ_RTC_SECOND = 67,
147 IRQ_PIT_CH0 = 68,
148 IRQ_PIT_CH1 = 69,
149 IRQ_PIT_CH2 = 70,
150 IRQ_PIT_CH3 = 71,
151 IRQ_PDB = 72,
152 IRQ_USBOTG = 73,
153 IRQ_USBDCD = 74,
154 IRQ_DAC0 = 81,
155 IRQ_TSI = 83,
156 IRQ_MCG = 84,
157 IRQ_LPTMR = 85,
158 IRQ_PORTA = 87,
159 IRQ_PORTB = 88,
160 IRQ_PORTC = 89,
161 IRQ_PORTD = 90,
162 IRQ_PORTE = 91,
163 IRQ_SOFTWARE = 94
164};
165#define NVIC_NUM_INTERRUPTS 95
166#define DMA_NUM_CHANNELS 16
167#define KINETISK_UART0
168#define KINETISK_UART0_FIFO
169#define KINETISK_UART1
170#define KINETISK_UART1_FIFO
171#define KINETISK_UART2
172
173#endif // end of board-specific definitions
174
175
176#if (F_CPU == 168000000)
177 #define F_BUS 56000000
178 #define F_MEM 33600000
179#elif (F_CPU == 144000000)
180 #define F_BUS 48000000
181 #define F_MEM 28800000
182#elif (F_CPU == 120000000)
183 #define F_BUS 60000000
184 #define F_MEM 24000000
185#elif (F_CPU == 96000000)
186 #define F_BUS 48000000
187 #define F_MEM 24000000
188#elif (F_CPU == 72000000)
189 #define F_BUS 36000000
190 #define F_MEM 24000000
191#elif (F_CPU == 48000000)
192 #define F_BUS 48000000
193 #define F_MEM 24000000
194#elif (F_CPU == 24000000)
195 #define F_BUS 24000000
196 #define F_MEM 24000000
197#elif (F_CPU == 16000000)
198 #define F_BUS 16000000
199 #define F_MEM 16000000
200#elif (F_CPU == 8000000)
201 #define F_BUS 8000000
202 #define F_MEM 8000000
203#elif (F_CPU == 4000000)
204 #define F_BUS 4000000
205 #define F_MEM 4000000
206#elif (F_CPU == 2000000)
207 #define F_BUS 2000000
208 #define F_MEM 1000000
209#endif
210
211
212#ifndef NULL
213#define NULL ((void *)0)
214#endif
215
216// chapter 11: Port control and interrupts (PORT)
217#define PORTA_PCR0 (*(volatile uint32_t *)0x40049000) // Pin Control Register n
218#define PORT_PCR_ISF ((uint32_t)0x01000000) // Interrupt Status Flag
219#define PORT_PCR_IRQC(n) ((uint32_t)(((n) & 15) << 16)) // Interrupt Configuration
220#define PORT_PCR_IRQC_MASK ((uint32_t)0x000F0000)
221#define PORT_PCR_LK ((uint32_t)0x00008000) // Lock Register
222#define PORT_PCR_MUX(n) ((uint32_t)(((n) & 7) << 8)) // Pin Mux Control
223#define PORT_PCR_MUX_MASK ((uint32_t)0x00000700)
224#define PORT_PCR_DSE ((uint32_t)0x00000040) // Drive Strength Enable
225#define PORT_PCR_ODE ((uint32_t)0x00000020) // Open Drain Enable
226#define PORT_PCR_PFE ((uint32_t)0x00000010) // Passive Filter Enable
227#define PORT_PCR_SRE ((uint32_t)0x00000004) // Slew Rate Enable
228#define PORT_PCR_PE ((uint32_t)0x00000002) // Pull Enable
229#define PORT_PCR_PS ((uint32_t)0x00000001) // Pull Select
230#define PORTA_PCR1 (*(volatile uint32_t *)0x40049004) // Pin Control Register n
231#define PORTA_PCR2 (*(volatile uint32_t *)0x40049008) // Pin Control Register n
232#define PORTA_PCR3 (*(volatile uint32_t *)0x4004900C) // Pin Control Register n
233#define PORTA_PCR4 (*(volatile uint32_t *)0x40049010) // Pin Control Register n
234#define PORTA_PCR5 (*(volatile uint32_t *)0x40049014) // Pin Control Register n
235#define PORTA_PCR6 (*(volatile uint32_t *)0x40049018) // Pin Control Register n
236#define PORTA_PCR7 (*(volatile uint32_t *)0x4004901C) // Pin Control Register n
237#define PORTA_PCR8 (*(volatile uint32_t *)0x40049020) // Pin Control Register n
238#define PORTA_PCR9 (*(volatile uint32_t *)0x40049024) // Pin Control Register n
239#define PORTA_PCR10 (*(volatile uint32_t *)0x40049028) // Pin Control Register n
240#define PORTA_PCR11 (*(volatile uint32_t *)0x4004902C) // Pin Control Register n
241#define PORTA_PCR12 (*(volatile uint32_t *)0x40049030) // Pin Control Register n
242#define PORTA_PCR13 (*(volatile uint32_t *)0x40049034) // Pin Control Register n
243#define PORTA_PCR14 (*(volatile uint32_t *)0x40049038) // Pin Control Register n
244#define PORTA_PCR15 (*(volatile uint32_t *)0x4004903C) // Pin Control Register n
245#define PORTA_PCR16 (*(volatile uint32_t *)0x40049040) // Pin Control Register n
246#define PORTA_PCR17 (*(volatile uint32_t *)0x40049044) // Pin Control Register n
247#define PORTA_PCR18 (*(volatile uint32_t *)0x40049048) // Pin Control Register n
248#define PORTA_PCR19 (*(volatile uint32_t *)0x4004904C) // Pin Control Register n
249#define PORTA_PCR20 (*(volatile uint32_t *)0x40049050) // Pin Control Register n
250#define PORTA_PCR21 (*(volatile uint32_t *)0x40049054) // Pin Control Register n
251#define PORTA_PCR22 (*(volatile uint32_t *)0x40049058) // Pin Control Register n
252#define PORTA_PCR23 (*(volatile uint32_t *)0x4004905C) // Pin Control Register n
253#define PORTA_PCR24 (*(volatile uint32_t *)0x40049060) // Pin Control Register n
254#define PORTA_PCR25 (*(volatile uint32_t *)0x40049064) // Pin Control Register n
255#define PORTA_PCR26 (*(volatile uint32_t *)0x40049068) // Pin Control Register n
256#define PORTA_PCR27 (*(volatile uint32_t *)0x4004906C) // Pin Control Register n
257#define PORTA_PCR28 (*(volatile uint32_t *)0x40049070) // Pin Control Register n
258#define PORTA_PCR29 (*(volatile uint32_t *)0x40049074) // Pin Control Register n
259#define PORTA_PCR30 (*(volatile uint32_t *)0x40049078) // Pin Control Register n
260#define PORTA_PCR31 (*(volatile uint32_t *)0x4004907C) // Pin Control Register n
261#define PORTA_GPCLR (*(volatile uint32_t *)0x40049080) // Global Pin Control Low Register
262#define PORTA_GPCHR (*(volatile uint32_t *)0x40049084) // Global Pin Control High Register
263#define PORTA_ISFR (*(volatile uint32_t *)0x400490A0) // Interrupt Status Flag Register
264#define PORTB_PCR0 (*(volatile uint32_t *)0x4004A000) // Pin Control Register n
265#define PORTB_PCR1 (*(volatile uint32_t *)0x4004A004) // Pin Control Register n
266#define PORTB_PCR2 (*(volatile uint32_t *)0x4004A008) // Pin Control Register n
267#define PORTB_PCR3 (*(volatile uint32_t *)0x4004A00C) // Pin Control Register n
268#define PORTB_PCR4 (*(volatile uint32_t *)0x4004A010) // Pin Control Register n
269#define PORTB_PCR5 (*(volatile uint32_t *)0x4004A014) // Pin Control Register n
270#define PORTB_PCR6 (*(volatile uint32_t *)0x4004A018) // Pin Control Register n
271#define PORTB_PCR7 (*(volatile uint32_t *)0x4004A01C) // Pin Control Register n
272#define PORTB_PCR8 (*(volatile uint32_t *)0x4004A020) // Pin Control Register n
273#define PORTB_PCR9 (*(volatile uint32_t *)0x4004A024) // Pin Control Register n
274#define PORTB_PCR10 (*(volatile uint32_t *)0x4004A028) // Pin Control Register n
275#define PORTB_PCR11 (*(volatile uint32_t *)0x4004A02C) // Pin Control Register n
276#define PORTB_PCR12 (*(volatile uint32_t *)0x4004A030) // Pin Control Register n
277#define PORTB_PCR13 (*(volatile uint32_t *)0x4004A034) // Pin Control Register n
278#define PORTB_PCR14 (*(volatile uint32_t *)0x4004A038) // Pin Control Register n
279#define PORTB_PCR15 (*(volatile uint32_t *)0x4004A03C) // Pin Control Register n
280#define PORTB_PCR16 (*(volatile uint32_t *)0x4004A040) // Pin Control Register n
281#define PORTB_PCR17 (*(volatile uint32_t *)0x4004A044) // Pin Control Register n
282#define PORTB_PCR18 (*(volatile uint32_t *)0x4004A048) // Pin Control Register n
283#define PORTB_PCR19 (*(volatile uint32_t *)0x4004A04C) // Pin Control Register n
284#define PORTB_PCR20 (*(volatile uint32_t *)0x4004A050) // Pin Control Register n
285#define PORTB_PCR21 (*(volatile uint32_t *)0x4004A054) // Pin Control Register n
286#define PORTB_PCR22 (*(volatile uint32_t *)0x4004A058) // Pin Control Register n
287#define PORTB_PCR23 (*(volatile uint32_t *)0x4004A05C) // Pin Control Register n
288#define PORTB_PCR24 (*(volatile uint32_t *)0x4004A060) // Pin Control Register n
289#define PORTB_PCR25 (*(volatile uint32_t *)0x4004A064) // Pin Control Register n
290#define PORTB_PCR26 (*(volatile uint32_t *)0x4004A068) // Pin Control Register n
291#define PORTB_PCR27 (*(volatile uint32_t *)0x4004A06C) // Pin Control Register n
292#define PORTB_PCR28 (*(volatile uint32_t *)0x4004A070) // Pin Control Register n
293#define PORTB_PCR29 (*(volatile uint32_t *)0x4004A074) // Pin Control Register n
294#define PORTB_PCR30 (*(volatile uint32_t *)0x4004A078) // Pin Control Register n
295#define PORTB_PCR31 (*(volatile uint32_t *)0x4004A07C) // Pin Control Register n
296#define PORTB_GPCLR (*(volatile uint32_t *)0x4004A080) // Global Pin Control Low Register
297#define PORTB_GPCHR (*(volatile uint32_t *)0x4004A084) // Global Pin Control High Register
298#define PORTB_ISFR (*(volatile uint32_t *)0x4004A0A0) // Interrupt Status Flag Register
299#define PORTC_PCR0 (*(volatile uint32_t *)0x4004B000) // Pin Control Register n
300#define PORTC_PCR1 (*(volatile uint32_t *)0x4004B004) // Pin Control Register n
301#define PORTC_PCR2 (*(volatile uint32_t *)0x4004B008) // Pin Control Register n
302#define PORTC_PCR3 (*(volatile uint32_t *)0x4004B00C) // Pin Control Register n
303#define PORTC_PCR4 (*(volatile uint32_t *)0x4004B010) // Pin Control Register n
304#define PORTC_PCR5 (*(volatile uint32_t *)0x4004B014) // Pin Control Register n
305#define PORTC_PCR6 (*(volatile uint32_t *)0x4004B018) // Pin Control Register n
306#define PORTC_PCR7 (*(volatile uint32_t *)0x4004B01C) // Pin Control Register n
307#define PORTC_PCR8 (*(volatile uint32_t *)0x4004B020) // Pin Control Register n
308#define PORTC_PCR9 (*(volatile uint32_t *)0x4004B024) // Pin Control Register n
309#define PORTC_PCR10 (*(volatile uint32_t *)0x4004B028) // Pin Control Register n
310#define PORTC_PCR11 (*(volatile uint32_t *)0x4004B02C) // Pin Control Register n
311#define PORTC_PCR12 (*(volatile uint32_t *)0x4004B030) // Pin Control Register n
312#define PORTC_PCR13 (*(volatile uint32_t *)0x4004B034) // Pin Control Register n
313#define PORTC_PCR14 (*(volatile uint32_t *)0x4004B038) // Pin Control Register n
314#define PORTC_PCR15 (*(volatile uint32_t *)0x4004B03C) // Pin Control Register n
315#define PORTC_PCR16 (*(volatile uint32_t *)0x4004B040) // Pin Control Register n
316#define PORTC_PCR17 (*(volatile uint32_t *)0x4004B044) // Pin Control Register n
317#define PORTC_PCR18 (*(volatile uint32_t *)0x4004B048) // Pin Control Register n
318#define PORTC_PCR19 (*(volatile uint32_t *)0x4004B04C) // Pin Control Register n
319#define PORTC_PCR20 (*(volatile uint32_t *)0x4004B050) // Pin Control Register n
320#define PORTC_PCR21 (*(volatile uint32_t *)0x4004B054) // Pin Control Register n
321#define PORTC_PCR22 (*(volatile uint32_t *)0x4004B058) // Pin Control Register n
322#define PORTC_PCR23 (*(volatile uint32_t *)0x4004B05C) // Pin Control Register n
323#define PORTC_PCR24 (*(volatile uint32_t *)0x4004B060) // Pin Control Register n
324#define PORTC_PCR25 (*(volatile uint32_t *)0x4004B064) // Pin Control Register n
325#define PORTC_PCR26 (*(volatile uint32_t *)0x4004B068) // Pin Control Register n
326#define PORTC_PCR27 (*(volatile uint32_t *)0x4004B06C) // Pin Control Register n
327#define PORTC_PCR28 (*(volatile uint32_t *)0x4004B070) // Pin Control Register n
328#define PORTC_PCR29 (*(volatile uint32_t *)0x4004B074) // Pin Control Register n
329#define PORTC_PCR30 (*(volatile uint32_t *)0x4004B078) // Pin Control Register n
330#define PORTC_PCR31 (*(volatile uint32_t *)0x4004B07C) // Pin Control Register n
331#define PORTC_GPCLR (*(volatile uint32_t *)0x4004B080) // Global Pin Control Low Register
332#define PORTC_GPCHR (*(volatile uint32_t *)0x4004B084) // Global Pin Control High Register
333#define PORTC_ISFR (*(volatile uint32_t *)0x4004B0A0) // Interrupt Status Flag Register
334#define PORTD_PCR0 (*(volatile uint32_t *)0x4004C000) // Pin Control Register n
335#define PORTD_PCR1 (*(volatile uint32_t *)0x4004C004) // Pin Control Register n
336#define PORTD_PCR2 (*(volatile uint32_t *)0x4004C008) // Pin Control Register n
337#define PORTD_PCR3 (*(volatile uint32_t *)0x4004C00C) // Pin Control Register n
338#define PORTD_PCR4 (*(volatile uint32_t *)0x4004C010) // Pin Control Register n
339#define PORTD_PCR5 (*(volatile uint32_t *)0x4004C014) // Pin Control Register n
340#define PORTD_PCR6 (*(volatile uint32_t *)0x4004C018) // Pin Control Register n
341#define PORTD_PCR7 (*(volatile uint32_t *)0x4004C01C) // Pin Control Register n
342#define PORTD_PCR8 (*(volatile uint32_t *)0x4004C020) // Pin Control Register n
343#define PORTD_PCR9 (*(volatile uint32_t *)0x4004C024) // Pin Control Register n
344#define PORTD_PCR10 (*(volatile uint32_t *)0x4004C028) // Pin Control Register n
345#define PORTD_PCR11 (*(volatile uint32_t *)0x4004C02C) // Pin Control Register n
346#define PORTD_PCR12 (*(volatile uint32_t *)0x4004C030) // Pin Control Register n
347#define PORTD_PCR13 (*(volatile uint32_t *)0x4004C034) // Pin Control Register n
348#define PORTD_PCR14 (*(volatile uint32_t *)0x4004C038) // Pin Control Register n
349#define PORTD_PCR15 (*(volatile uint32_t *)0x4004C03C) // Pin Control Register n
350#define PORTD_PCR16 (*(volatile uint32_t *)0x4004C040) // Pin Control Register n
351#define PORTD_PCR17 (*(volatile uint32_t *)0x4004C044) // Pin Control Register n
352#define PORTD_PCR18 (*(volatile uint32_t *)0x4004C048) // Pin Control Register n
353#define PORTD_PCR19 (*(volatile uint32_t *)0x4004C04C) // Pin Control Register n
354#define PORTD_PCR20 (*(volatile uint32_t *)0x4004C050) // Pin Control Register n
355#define PORTD_PCR21 (*(volatile uint32_t *)0x4004C054) // Pin Control Register n
356#define PORTD_PCR22 (*(volatile uint32_t *)0x4004C058) // Pin Control Register n
357#define PORTD_PCR23 (*(volatile uint32_t *)0x4004C05C) // Pin Control Register n
358#define PORTD_PCR24 (*(volatile uint32_t *)0x4004C060) // Pin Control Register n
359#define PORTD_PCR25 (*(volatile uint32_t *)0x4004C064) // Pin Control Register n
360#define PORTD_PCR26 (*(volatile uint32_t *)0x4004C068) // Pin Control Register n
361#define PORTD_PCR27 (*(volatile uint32_t *)0x4004C06C) // Pin Control Register n
362#define PORTD_PCR28 (*(volatile uint32_t *)0x4004C070) // Pin Control Register n
363#define PORTD_PCR29 (*(volatile uint32_t *)0x4004C074) // Pin Control Register n
364#define PORTD_PCR30 (*(volatile uint32_t *)0x4004C078) // Pin Control Register n
365#define PORTD_PCR31 (*(volatile uint32_t *)0x4004C07C) // Pin Control Register n
366#define PORTD_GPCLR (*(volatile uint32_t *)0x4004C080) // Global Pin Control Low Register
367#define PORTD_GPCHR (*(volatile uint32_t *)0x4004C084) // Global Pin Control High Register
368#define PORTD_ISFR (*(volatile uint32_t *)0x4004C0A0) // Interrupt Status Flag Register
369#define PORTE_PCR0 (*(volatile uint32_t *)0x4004D000) // Pin Control Register n
370#define PORTE_PCR1 (*(volatile uint32_t *)0x4004D004) // Pin Control Register n
371#define PORTE_PCR2 (*(volatile uint32_t *)0x4004D008) // Pin Control Register n
372#define PORTE_PCR3 (*(volatile uint32_t *)0x4004D00C) // Pin Control Register n
373#define PORTE_PCR4 (*(volatile uint32_t *)0x4004D010) // Pin Control Register n
374#define PORTE_PCR5 (*(volatile uint32_t *)0x4004D014) // Pin Control Register n
375#define PORTE_PCR6 (*(volatile uint32_t *)0x4004D018) // Pin Control Register n
376#define PORTE_PCR7 (*(volatile uint32_t *)0x4004D01C) // Pin Control Register n
377#define PORTE_PCR8 (*(volatile uint32_t *)0x4004D020) // Pin Control Register n
378#define PORTE_PCR9 (*(volatile uint32_t *)0x4004D024) // Pin Control Register n
379#define PORTE_PCR10 (*(volatile uint32_t *)0x4004D028) // Pin Control Register n
380#define PORTE_PCR11 (*(volatile uint32_t *)0x4004D02C) // Pin Control Register n
381#define PORTE_PCR12 (*(volatile uint32_t *)0x4004D030) // Pin Control Register n
382#define PORTE_PCR13 (*(volatile uint32_t *)0x4004D034) // Pin Control Register n
383#define PORTE_PCR14 (*(volatile uint32_t *)0x4004D038) // Pin Control Register n
384#define PORTE_PCR15 (*(volatile uint32_t *)0x4004D03C) // Pin Control Register n
385#define PORTE_PCR16 (*(volatile uint32_t *)0x4004D040) // Pin Control Register n
386#define PORTE_PCR17 (*(volatile uint32_t *)0x4004D044) // Pin Control Register n
387#define PORTE_PCR18 (*(volatile uint32_t *)0x4004D048) // Pin Control Register n
388#define PORTE_PCR19 (*(volatile uint32_t *)0x4004D04C) // Pin Control Register n
389#define PORTE_PCR20 (*(volatile uint32_t *)0x4004D050) // Pin Control Register n
390#define PORTE_PCR21 (*(volatile uint32_t *)0x4004D054) // Pin Control Register n
391#define PORTE_PCR22 (*(volatile uint32_t *)0x4004D058) // Pin Control Register n
392#define PORTE_PCR23 (*(volatile uint32_t *)0x4004D05C) // Pin Control Register n
393#define PORTE_PCR24 (*(volatile uint32_t *)0x4004D060) // Pin Control Register n
394#define PORTE_PCR25 (*(volatile uint32_t *)0x4004D064) // Pin Control Register n
395#define PORTE_PCR26 (*(volatile uint32_t *)0x4004D068) // Pin Control Register n
396#define PORTE_PCR27 (*(volatile uint32_t *)0x4004D06C) // Pin Control Register n
397#define PORTE_PCR28 (*(volatile uint32_t *)0x4004D070) // Pin Control Register n
398#define PORTE_PCR29 (*(volatile uint32_t *)0x4004D074) // Pin Control Register n
399#define PORTE_PCR30 (*(volatile uint32_t *)0x4004D078) // Pin Control Register n
400#define PORTE_PCR31 (*(volatile uint32_t *)0x4004D07C) // Pin Control Register n
401#define PORTE_GPCLR (*(volatile uint32_t *)0x4004D080) // Global Pin Control Low Register
402#define PORTE_GPCHR (*(volatile uint32_t *)0x4004D084) // Global Pin Control High Register
403#define PORTE_ISFR (*(volatile uint32_t *)0x4004D0A0) // Interrupt Status Flag Register
404
405// Chapter 12: System Integration Module (SIM)
406#define SIM_SOPT1 (*(volatile uint32_t *)0x40047000) // System Options Register 1
407#define SIM_SOPT1CFG (*(volatile uint32_t *)0x40047004) // SOPT1 Configuration Register
408#define SIM_SOPT2 (*(volatile uint32_t *)0x40048004) // System Options Register 2
409#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) // 0=USB_CLKIN, 1=FFL/PLL
410#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) // 0=FLL, 1=PLL
411#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) // 0=MCGOUTCLK, 1=CPU
412#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) // 0=normal, 1=double drive PTD7
413#define SIM_SOPT2_CLKOUTSEL(n) ((uint32_t)(((n) & 7) << 5)) // Selects the clock to output on the CLKOUT pin.
414#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) // RTC clock out select
415#define SIM_SOPT4 (*(volatile uint32_t *)0x4004800C) // System Options Register 4
416#define SIM_SOPT5 (*(volatile uint32_t *)0x40048010) // System Options Register 5
417#define SIM_SOPT7 (*(volatile uint32_t *)0x40048018) // System Options Register 7
418#define SIM_SDID (*(const uint32_t *)0x40048024) // System Device Identification Register
419#define SIM_SCGC2 (*(volatile uint32_t *)0x4004802C) // System Clock Gating Control Register 2
420#define SIM_SCGC2_DAC0 ((uint32_t)0x00001000) // DAC0 Clock Gate Control
421#define SIM_SCGC3 (*(volatile uint32_t *)0x40048030) // System Clock Gating Control Register 3
422#define SIM_SCGC3_ADC1 ((uint32_t)0x08000000) // ADC1 Clock Gate Control
423#define SIM_SCGC3_FTM2 ((uint32_t)0x01000000) // FTM2 Clock Gate Control
424#define SIM_SCGC4 (*(volatile uint32_t *)0x40048034) // System Clock Gating Control Register 4
425#define SIM_SCGC4_VREF ((uint32_t)0x00100000) // VREF Clock Gate Control
426#define SIM_SCGC4_CMP ((uint32_t)0x00080000) // Comparator Clock Gate Control
427#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) // USB Clock Gate Control
428#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) // UART2 Clock Gate Control
429#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) // UART1 Clock Gate Control
430#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) // UART0 Clock Gate Control
431#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) // I2C1 Clock Gate Control
432#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) // I2C0 Clock Gate Control
433#define SIM_SCGC4_CMT ((uint32_t)0x00000004) // CMT Clock Gate Control
434#define SIM_SCGC4_EWM ((uint32_t)0x00000002) // EWM Clock Gate Control
435#define SIM_SCGC5 (*(volatile uint32_t *)0x40048038) // System Clock Gating Control Register 5
436#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) // Port E Clock Gate Control
437#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) // Port D Clock Gate Control
438#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) // Port C Clock Gate Control
439#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) // Port B Clock Gate Control
440#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) // Port A Clock Gate Control
441#define SIM_SCGC5_TSI ((uint32_t)0x00000020) // Touch Sense Input TSI Clock Gate Control
442#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) // Low Power Timer Access Control
443#define SIM_SCGC6 (*(volatile uint32_t *)0x4004803C) // System Clock Gating Control Register 6
444#define SIM_SCGC6_RTC ((uint32_t)0x20000000) // RTC Access
445#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) // ADC0 Clock Gate Control
446#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) // FTM1 Clock Gate Control
447#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) // FTM0 Clock Gate Control
448#define SIM_SCGC6_PIT ((uint32_t)0x00800000) // PIT Clock Gate Control
449#define SIM_SCGC6_PDB ((uint32_t)0x00400000) // PDB Clock Gate Control
450#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) // USB DCD Clock Gate Control
451#define SIM_SCGC6_CRC ((uint32_t)0x00040000) // CRC Clock Gate Control
452#define SIM_SCGC6_I2S ((uint32_t)0x00008000) // I2S Clock Gate Control
453#define SIM_SCGC6_SPI1 ((uint32_t)0x00002000) // SPI1 Clock Gate Control
454#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) // SPI0 Clock Gate Control
455#define SIM_SCGC6_FLEXCAN0 ((uint32_t)0x00000010) // FlexCAN0 Clock Gate Control
456#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) // DMA Mux Clock Gate Control
457#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) // Flash Memory Clock Gate Control
458#define SIM_SCGC7 (*(volatile uint32_t *)0x40048040) // System Clock Gating Control Register 7
459#define SIM_SCGC7_DMA ((uint32_t)0x00000002) // DMA Clock Gate Control
460#define SIM_CLKDIV1 (*(volatile uint32_t *)0x40048044) // System Clock Divider Register 1
461#define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)(((n) & 0x0F) << 28)) // divide value for the core/system clock
462#define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)(((n) & 0x0F) << 24)) // divide value for the peripheral clock
463#define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)(((n) & 0x0F) << 16)) // divide value for the flash clock
464#define SIM_CLKDIV2 (*(volatile uint32_t *)0x40048048) // System Clock Divider Register 2
465#define SIM_CLKDIV2_USBDIV(n) ((uint32_t)(((n) & 0x07) << 1))
466#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x01)
467#define SIM_FCFG1 (*(const uint32_t *)0x4004804C) // Flash Configuration Register 1
468#define SIM_FCFG2 (*(const uint32_t *)0x40048050) // Flash Configuration Register 2
469#define SIM_UIDH (*(const uint32_t *)0x40048054) // Unique Identification Register High
470#define SIM_UIDMH (*(const uint32_t *)0x40048058) // Unique Identification Register Mid-High
471#define SIM_UIDML (*(const uint32_t *)0x4004805C) // Unique Identification Register Mid Low
472#define SIM_UIDL (*(const uint32_t *)0x40048060) // Unique Identification Register Low
473
474// Chapter 13: Reset Control Module (RCM)
475#define RCM_SRS0 (*(volatile uint8_t *)0x4007F000) // System Reset Status Register 0
476#define RCM_SRS1 (*(volatile uint8_t *)0x4007F001) // System Reset Status Register 1
477#define RCM_RPFC (*(volatile uint8_t *)0x4007F004) // Reset Pin Filter Control Register
478#define RCM_RPFW (*(volatile uint8_t *)0x4007F005) // Reset Pin Filter Width Register
479#define RCM_MR (*(volatile uint8_t *)0x4007F007) // Mode Register
480
481// Chapter 14: System Mode Controller
482#define SMC_PMPROT (*(volatile uint8_t *)0x4007E000) // Power Mode Protection Register
483#define SMC_PMPROT_AVLP ((uint8_t)0x20) // Allow very low power modes
484#define SMC_PMPROT_ALLS ((uint8_t)0x08) // Allow low leakage stop mode
485#define SMC_PMPROT_AVLLS ((uint8_t)0x02) // Allow very low leakage stop mode
486#define SMC_PMCTRL (*(volatile uint8_t *)0x4007E001) // Power Mode Control Register
487#define SMC_PMCTRL_LPWUI ((uint8_t)0x80) // Low Power Wake Up on Interrupt
488#define SMC_PMCTRL_RUNM(n) ((uint8_t)(((n) & 0x03) << 5)) // Run Mode Control
489#define SMC_PMCTRL_STOPA ((uint8_t)0x08) // Stop Aborted
490#define SMC_PMCTRL_STOPM(n) ((uint8_t)((n) & 0x07)) // Stop Mode Control
491#define SMC_VLLSCTRL (*(volatile uint8_t *)0x4007E002) // VLLS Control Register
492#define SMC_VLLSCTRL_PORPO ((uint8_t)0x20) // POR Power Option
493#define SMC_VLLSCTRL_VLLSM(n) ((uint8_t)((n) & 0x07)) // VLLS Mode Control
494#define SMC_PMSTAT (*(volatile uint8_t *)0x4007E003) // Power Mode Status Register
495#define SMC_PMSTAT_RUN ((uint8_t)0x01) // Current power mode is RUN
496#define SMC_PMSTAT_STOP ((uint8_t)0x02) // Current power mode is STOP
497#define SMC_PMSTAT_VLPR ((uint8_t)0x04) // Current power mode is VLPR
498#define SMC_PMSTAT_VLPW ((uint8_t)0x08) // Current power mode is VLPW
499#define SMC_PMSTAT_VLPS ((uint8_t)0x10) // Current power mode is VLPS
500#define SMC_PMSTAT_LLS ((uint8_t)0x20) // Current power mode is LLS
501#define SMC_PMSTAT_VLLS ((uint8_t)0x40) // Current power mode is VLLS
502
503// Chapter 15: Power Management Controller
504#define PMC_LVDSC1 (*(volatile uint8_t *)0x4007D000) // Low Voltage Detect Status And Control 1 register
505#define PMC_LVDSC1_LVDF ((uint8_t)0x80) // Low-Voltage Detect Flag
506#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) // Low-Voltage Detect Acknowledge
507#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) // Low-Voltage Detect Interrupt Enable
508#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) // Low-Voltage Detect Reset Enable
509#define PMC_LVDSC1_LVDV(n) ((uint8_t)((n) & 0x03)) // Low-Voltage Detect Voltage Select
510#define PMC_LVDSC2 (*(volati(le uint8_t *)0x4007D001) // Low Voltage Detect Status And Control 2 register
511#define PMC_LVDSC2_LVWF ((uint8_t)0x80) // Low-Voltage Warning Flag
512#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) // Low-Voltage Warning Acknowledge
513#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) // Low-Voltage Warning Interrupt Enable
514#define PMC_LVDSC2_LVWV(n) ((uint8_t)((n) & 0x03)) // Low-Voltage Warning Voltage Select
515#define PMC_REGSC (*(volatile uint8_t *)0x4007D002) // Regulator Status And Control register
516#define PMC_REGSC_BGEN ((uint8_t)0x10) // Bandgap Enable In VLPx Operation
517#define PMC_REGSC_ACKISO ((uint8_t)0x08) // Acknowledge Isolation
518#define PMC_REGSC_REGONS ((uint8_t)0x04) // Regulator In Run Regulation Status
519#define PMC_REGSC_BGBE ((uint8_t)0x01) // Bandgap Buffer Enable
520
521// Chapter 16: Low-Leakage Wakeup Unit (LLWU)
522#define LLWU_PE1 (*(volatile uint8_t *)0x4007C000) // LLWU Pin Enable 1 register
523#define LLWU_PE2 (*(volatile uint8_t *)0x4007C001) // LLWU Pin Enable 2 register
524#define LLWU_PE3 (*(volatile uint8_t *)0x4007C002) // LLWU Pin Enable 3 register
525#define LLWU_PE4 (*(volatile uint8_t *)0x4007C003) // LLWU Pin Enable 4 register
526#define LLWU_ME (*(volatile uint8_t *)0x4007C004) // LLWU Module Enable register
527#define LLWU_F1 (*(volatile uint8_t *)0x4007C005) // LLWU Flag 1 register
528#define LLWU_F2 (*(volatile uint8_t *)0x4007C006) // LLWU Flag 2 register
529#define LLWU_F3 (*(volatile uint8_t *)0x4007C007) // LLWU Flag 3 register
530#define LLWU_FILT1 (*(volatile uint8_t *)0x4007C008) // LLWU Pin Filter 1 register
531#define LLWU_FILT2 (*(volatile uint8_t *)0x4007C009) // LLWU Pin Filter 2 register
532#define LLWU_RST (*(volatile uint8_t *)0x4007C00A) // LLWU Reset Enable register
533
534// Chapter 17: Miscellaneous Control Module (MCM)
535#define MCM_PLASC (*(volatile uint16_t *)0xE0080008) // Crossbar Switch (AXBS) Slave Configuration
536#define MCM_PLAMC (*(volatile uint16_t *)0xE008000A) // Crossbar Switch (AXBS) Master Configuration
537#define MCM_PLACR (*(volatile uint32_t *)0xE008000C) // Crossbar Switch (AXBS) Control Register (MK20DX128)
538#define MCM_PLACR_ARG ((uint32_t)0x00000200) // Arbitration select, 0=fixed, 1=round-robin
539#define MCM_CR (*(volatile uint32_t *)0xE008000C) // RAM arbitration control register (MK20DX256)
540#define MCM_CR_SRAMLWP ((uint32_t)0x40000000) // SRAM_L write protect
541#define MCM_CR_SRAMLAP(n) ((uint32_t)(((n) & 0x03) << 28)) // SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
542#define MCM_CR_SRAMUWP ((uint32_t)0x04000000) // SRAM_U write protect
543#define MCM_CR_SRAMUAP(n) ((uint32_t)(((n) & 0x03) << 24)) // SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
544
545// Crossbar Switch (AXBS) - only programmable on MK20DX256
546#define AXBS_PRS0 (*(volatile uint32_t *)0x40004000) // Priority Registers Slave 0
547#define AXBS_CRS0 (*(volatile uint32_t *)0x40004010) // Control Register 0
548#define AXBS_PRS1 (*(volatile uint32_t *)0x40004100) // Priority Registers Slave 1
549#define AXBS_CRS1 (*(volatile uint32_t *)0x40004110) // Control Register 1
550#define AXBS_PRS2 (*(volatile uint32_t *)0x40004200) // Priority Registers Slave 2
551#define AXBS_CRS2 (*(volatile uint32_t *)0x40004210) // Control Register 2
552#define AXBS_PRS3 (*(volatile uint32_t *)0x40004300) // Priority Registers Slave 3
553#define AXBS_CRS3 (*(volatile uint32_t *)0x40004310) // Control Register 3
554#define AXBS_PRS4 (*(volatile uint32_t *)0x40004400) // Priority Registers Slave 4
555#define AXBS_CRS4 (*(volatile uint32_t *)0x40004410) // Control Register 4
556#define AXBS_PRS5 (*(volatile uint32_t *)0x40004500) // Priority Registers Slave 5
557#define AXBS_CRS5 (*(volatile uint32_t *)0x40004510) // Control Register 5
558#define AXBS_PRS6 (*(volatile uint32_t *)0x40004600) // Priority Registers Slave 6
559#define AXBS_CRS6 (*(volatile uint32_t *)0x40004610) // Control Register 6
560#define AXBS_PRS7 (*(volatile uint32_t *)0x40004700) // Priority Registers Slave 7
561#define AXBS_CRS7 (*(volatile uint32_t *)0x40004710) // Control Register 7
562#define AXBS_MGPCR0 (*(volatile uint32_t *)0x40004800) // Master 0 General Purpose Control Register
563#define AXBS_MGPCR1 (*(volatile uint32_t *)0x40004900) // Master 1 General Purpose Control Register
564#define AXBS_MGPCR2 (*(volatile uint32_t *)0x40004A00) // Master 2 General Purpose Control Register
565#define AXBS_MGPCR3 (*(volatile uint32_t *)0x40004B00) // Master 3 General Purpose Control Register
566#define AXBS_MGPCR4 (*(volatile uint32_t *)0x40004C00) // Master 4 General Purpose Control Register
567#define AXBS_MGPCR5 (*(volatile uint32_t *)0x40004D00) // Master 5 General Purpose Control Register
568#define AXBS_MGPCR6 (*(volatile uint32_t *)0x40004E00) // Master 6 General Purpose Control Register
569#define AXBS_MGPCR7 (*(volatile uint32_t *)0x40004F00) // Master 7 General Purpose Control Register
570#define AXBS_CRS_READONLY ((uint32_t)0x80000000)
571#define AXBS_CRS_HALTLOWPRIORITY ((uint32_t)0x40000000)
572#define AXBS_CRS_ARB_FIXED ((uint32_t)0x00000000)
573#define AXBS_CRS_ARB_ROUNDROBIN ((uint32_t)0x00010000)
574#define AXBS_CRS_PARK_FIXED ((uint32_t)0x00000000)
575#define AXBS_CRS_PARK_PREVIOUS ((uint32_t)0x00000010)
576#define AXBS_CRS_PARK_NONE ((uint32_t)0x00000020)
577#define AXBS_CRS_PARK(n) ((uint32_t)(((n) & 7) << 0))
578
579
580
581// Chapter 20: Direct Memory Access Multiplexer (DMAMUX)
582#define DMAMUX0_CHCFG0 (*(volatile uint8_t *)0x40021000) // Channel Configuration register
583#define DMAMUX0_CHCFG1 (*(volatile uint8_t *)0x40021001) // Channel Configuration register
584#define DMAMUX0_CHCFG2 (*(volatile uint8_t *)0x40021002) // Channel Configuration register
585#define DMAMUX0_CHCFG3 (*(volatile uint8_t *)0x40021003) // Channel Configuration register
586#define DMAMUX0_CHCFG4 (*(volatile uint8_t *)0x40021004) // Channel Configuration register
587#define DMAMUX0_CHCFG5 (*(volatile uint8_t *)0x40021005) // Channel Configuration register
588#define DMAMUX0_CHCFG6 (*(volatile uint8_t *)0x40021006) // Channel Configuration register
589#define DMAMUX0_CHCFG7 (*(volatile uint8_t *)0x40021007) // Channel Configuration register
590#define DMAMUX0_CHCFG8 (*(volatile uint8_t *)0x40021008) // Channel Configuration register
591#define DMAMUX0_CHCFG9 (*(volatile uint8_t *)0x40021009) // Channel Configuration register
592#define DMAMUX0_CHCFG10 (*(volatile uint8_t *)0x4002100A) // Channel Configuration register
593#define DMAMUX0_CHCFG11 (*(volatile uint8_t *)0x4002100B) // Channel Configuration register
594#define DMAMUX0_CHCFG12 (*(volatile uint8_t *)0x4002100C) // Channel Configuration register
595#define DMAMUX0_CHCFG13 (*(volatile uint8_t *)0x4002100D) // Channel Configuration register
596#define DMAMUX0_CHCFG14 (*(volatile uint8_t *)0x4002100E) // Channel Configuration register
597#define DMAMUX0_CHCFG15 (*(volatile uint8_t *)0x4002100F) // Channel Configuration register
598#define DMAMUX_DISABLE 0
599#define DMAMUX_TRIG 64
600#define DMAMUX_ENABLE 128
601#define DMAMUX_SOURCE_UART0_RX 2
602#define DMAMUX_SOURCE_UART0_TX 3
603#define DMAMUX_SOURCE_UART1_RX 4
604#define DMAMUX_SOURCE_UART1_TX 5
605#define DMAMUX_SOURCE_UART2_RX 6
606#define DMAMUX_SOURCE_UART2_TX 7
607#define DMAMUX_SOURCE_I2S0_RX 14
608#define DMAMUX_SOURCE_I2S0_TX 15
609#define DMAMUX_SOURCE_SPI0_RX 16
610#define DMAMUX_SOURCE_SPI0_TX 17
611#define DMAMUX_SOURCE_I2C0 22
612#define DMAMUX_SOURCE_I2C1 23
613#define DMAMUX_SOURCE_FTM0_CH0 24
614#define DMAMUX_SOURCE_FTM0_CH1 25
615#define DMAMUX_SOURCE_FTM0_CH2 26
616#define DMAMUX_SOURCE_FTM0_CH3 27
617#define DMAMUX_SOURCE_FTM0_CH4 28
618#define DMAMUX_SOURCE_FTM0_CH5 29
619#define DMAMUX_SOURCE_FTM0_CH6 30
620#define DMAMUX_SOURCE_FTM0_CH7 31
621#define DMAMUX_SOURCE_FTM1_CH0 32
622#define DMAMUX_SOURCE_FTM1_CH1 33
623#define DMAMUX_SOURCE_FTM2_CH0 34
624#define DMAMUX_SOURCE_FTM2_CH1 35
625#define DMAMUX_SOURCE_ADC0 40
626#define DMAMUX_SOURCE_ADC1 41
627#define DMAMUX_SOURCE_CMP0 42
628#define DMAMUX_SOURCE_CMP1 43
629#define DMAMUX_SOURCE_CMP2 44
630#define DMAMUX_SOURCE_DAC0 45
631#define DMAMUX_SOURCE_CMT 47
632#define DMAMUX_SOURCE_PDB 48
633#define DMAMUX_SOURCE_PORTA 49
634#define DMAMUX_SOURCE_PORTB 50
635#define DMAMUX_SOURCE_PORTC 51
636#define DMAMUX_SOURCE_PORTD 52
637#define DMAMUX_SOURCE_PORTE 53
638#define DMAMUX_SOURCE_ALWAYS0 54
639#define DMAMUX_SOURCE_ALWAYS1 55
640#define DMAMUX_SOURCE_ALWAYS2 56
641#define DMAMUX_SOURCE_ALWAYS3 57
642#define DMAMUX_SOURCE_ALWAYS4 58
643#define DMAMUX_SOURCE_ALWAYS5 59
644#define DMAMUX_SOURCE_ALWAYS6 60
645#define DMAMUX_SOURCE_ALWAYS7 61
646#define DMAMUX_SOURCE_ALWAYS8 62
647#define DMAMUX_SOURCE_ALWAYS9 63
648#define DMAMUX_NUM_SOURCE_ALWAYS 10
649
650// Chapter 21: Direct Memory Access Controller (eDMA)
651#define DMA_CR (*(volatile uint32_t *)0x40008000) // Control Register
652#define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer
653#define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer
654#define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping
655#define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode
656#define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations
657#define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error
658#define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration
659#define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug
660#define DMA_ES (*(volatile uint32_t *)0x40008004) // Error Status Register
661#define DMA_ERQ (*(volatile uint32_t *)0x4000800C) // Enable Request Register
662#define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0
663#define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1
664#define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2
665#define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3
666#define DMA_ERQ_ERQ4 ((uint32_t)1<<4) // Enable DMA Request 4
667#define DMA_ERQ_ERQ5 ((uint32_t)1<<5) // Enable DMA Request 5
668#define DMA_ERQ_ERQ6 ((uint32_t)1<<6) // Enable DMA Request 6
669#define DMA_ERQ_ERQ7 ((uint32_t)1<<7) // Enable DMA Request 7
670#define DMA_ERQ_ERQ8 ((uint32_t)1<<8) // Enable DMA Request 8
671#define DMA_ERQ_ERQ9 ((uint32_t)1<<9) // Enable DMA Request 9
672#define DMA_ERQ_ERQ10 ((uint32_t)1<<10) // Enable DMA Request 10
673#define DMA_ERQ_ERQ11 ((uint32_t)1<<11) // Enable DMA Request 11
674#define DMA_ERQ_ERQ12 ((uint32_t)1<<12) // Enable DMA Request 12
675#define DMA_ERQ_ERQ13 ((uint32_t)1<<13) // Enable DMA Request 13
676#define DMA_ERQ_ERQ14 ((uint32_t)1<<14) // Enable DMA Request 14
677#define DMA_ERQ_ERQ15 ((uint32_t)1<<15) // Enable DMA Request 15
678#define DMA_EEI (*(volatile uint32_t *)0x40008014) // Enable Error Interrupt Register
679#define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0
680#define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1
681#define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2
682#define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3
683#define DMA_EEI_EEI4 ((uint32_t)1<<4) // Enable Error Interrupt 4
684#define DMA_EEI_EEI5 ((uint32_t)1<<5) // Enable Error Interrupt 5
685#define DMA_EEI_EEI6 ((uint32_t)1<<6) // Enable Error Interrupt 6
686#define DMA_EEI_EEI7 ((uint32_t)1<<7) // Enable Error Interrupt 7
687#define DMA_EEI_EEI8 ((uint32_t)1<<8) // Enable Error Interrupt 8
688#define DMA_EEI_EEI9 ((uint32_t)1<<9) // Enable Error Interrupt 9
689#define DMA_EEI_EEI10 ((uint32_t)1<<10) // Enable Error Interrupt 10
690#define DMA_EEI_EEI11 ((uint32_t)1<<11) // Enable Error Interrupt 11
691#define DMA_EEI_EEI12 ((uint32_t)1<<12) // Enable Error Interrupt 12
692#define DMA_EEI_EEI13 ((uint32_t)1<<13) // Enable Error Interrupt 13
693#define DMA_EEI_EEI14 ((uint32_t)1<<14) // Enable Error Interrupt 14
694#define DMA_EEI_EEI15 ((uint32_t)1<<15) // Enable Error Interrupt 15
695#define DMA_CEEI (*(volatile uint8_t *)0x40008018) // Clear Enable Error Interrupt Register
696#define DMA_CEEI_CEEI(n) ((uint8_t)(n & 15)<<0) // Clear Enable Error Interrupt
697#define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts
698#define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP
699#define DMA_SEEI (*(volatile uint8_t *)0x40008019) // Set Enable Error Interrupt Register
700#define DMA_SEEI_SEEI(n) ((uint8_t)(n & 15)<<0) // Set Enable Error Interrupt
701#define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts
702#define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP
703#define DMA_CERQ (*(volatile uint8_t *)0x4000801A) // Clear Enable Request Register
704#define DMA_CERQ_CERQ(n) ((uint8_t)(n & 15)<<0) // Clear Enable Request
705#define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests
706#define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP
707#define DMA_SERQ (*(volatile uint8_t *)0x4000801B) // Set Enable Request Register
708#define DMA_SERQ_SERQ(n) ((uint8_t)(n & 15)<<0) // Set Enable Request
709#define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests
710#define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP
711#define DMA_CDNE (*(volatile uint8_t *)0x4000801C) // Clear DONE Status Bit Register
712#define DMA_CDNE_CDNE(n) ((uint8_t)(n & 15)<<0) // Clear Done Bit
713#define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits
714#define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP
715#define DMA_SSRT (*(volatile uint8_t *)0x4000801D) // Set START Bit Register
716#define DMA_SSRT_SSRT(n) ((uint8_t)(n & 15)<<0) // Set Start Bit
717#define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits
718#define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP
719#define DMA_CERR (*(volatile uint8_t *)0x4000801E) // Clear Error Register
720#define DMA_CERR_CERR(n) ((uint8_t)(n & 15)<<0) // Clear Error Indicator
721#define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators
722#define DMA_CERR_NOP ((uint8_t)1<<7) // NOP
723#define DMA_CINT (*(volatile uint8_t *)0x4000801F) // Clear Interrupt Request Register
724#define DMA_CINT_CINT(n) ((uint8_t)(n & 15)<<0) // Clear Interrupt Request
725#define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests
726#define DMA_CINT_NOP ((uint8_t)1<<7) // NOP
727#define DMA_INT (*(volatile uint32_t *)0x40008024) // Interrupt Request Register
728#define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0
729#define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1
730#define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2
731#define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3
732#define DMA_INT_INT4 ((uint32_t)1<<4) // Interrupt Request 4
733#define DMA_INT_INT5 ((uint32_t)1<<5) // Interrupt Request 5
734#define DMA_INT_INT6 ((uint32_t)1<<6) // Interrupt Request 6
735#define DMA_INT_INT7 ((uint32_t)1<<7) // Interrupt Request 7
736#define DMA_INT_INT8 ((uint32_t)1<<8) // Interrupt Request 8
737#define DMA_INT_INT9 ((uint32_t)1<<9) // Interrupt Request 9
738#define DMA_INT_INT10 ((uint32_t)1<<10) // Interrupt Request 10
739#define DMA_INT_INT11 ((uint32_t)1<<11) // Interrupt Request 11
740#define DMA_INT_INT12 ((uint32_t)1<<12) // Interrupt Request 12
741#define DMA_INT_INT13 ((uint32_t)1<<13) // Interrupt Request 13
742#define DMA_INT_INT14 ((uint32_t)1<<14) // Interrupt Request 14
743#define DMA_INT_INT15 ((uint32_t)1<<15) // Interrupt Request 15
744#define DMA_ERR (*(volatile uint32_t *)0x4000802C) // Error Register
745#define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0
746#define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1
747#define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2
748#define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3
749#define DMA_ERR_ERR4 ((uint32_t)1<<4) // Error in Channel 4
750#define DMA_ERR_ERR5 ((uint32_t)1<<5) // Error in Channel 5
751#define DMA_ERR_ERR6 ((uint32_t)1<<6) // Error in Channel 6
752#define DMA_ERR_ERR7 ((uint32_t)1<<7) // Error in Channel 7
753#define DMA_ERR_ERR8 ((uint32_t)1<<8) // Error in Channel 8
754#define DMA_ERR_ERR9 ((uint32_t)1<<9) // Error in Channel 9
755#define DMA_ERR_ERR10 ((uint32_t)1<<10) // Error in Channel 10
756#define DMA_ERR_ERR11 ((uint32_t)1<<11) // Error in Channel 11
757#define DMA_ERR_ERR12 ((uint32_t)1<<12) // Error in Channel 12
758#define DMA_ERR_ERR13 ((uint32_t)1<<13) // Error in Channel 13
759#define DMA_ERR_ERR14 ((uint32_t)1<<14) // Error in Channel 14
760#define DMA_ERR_ERR15 ((uint32_t)1<<15) // Error in Channel 15
761#define DMA_HRS (*(volatile uint32_t *)0x40008034) // Hardware Request Status Register
762#define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0
763#define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1
764#define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2
765#define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3
766#define DMA_HRS_HRS4 ((uint32_t)1<<4) // Hardware Request Status Channel 4
767#define DMA_HRS_HRS5 ((uint32_t)1<<5) // Hardware Request Status Channel 5
768#define DMA_HRS_HRS6 ((uint32_t)1<<6) // Hardware Request Status Channel 6
769#define DMA_HRS_HRS7 ((uint32_t)1<<7) // Hardware Request Status Channel 7
770#define DMA_HRS_HRS8 ((uint32_t)1<<8) // Hardware Request Status Channel 8
771#define DMA_HRS_HRS9 ((uint32_t)1<<9) // Hardware Request Status Channel 9
772#define DMA_HRS_HRS10 ((uint32_t)1<<10) // Hardware Request Status Channel 10
773#define DMA_HRS_HRS11 ((uint32_t)1<<11) // Hardware Request Status Channel 11
774#define DMA_HRS_HRS12 ((uint32_t)1<<12) // Hardware Request Status Channel 12
775#define DMA_HRS_HRS13 ((uint32_t)1<<13) // Hardware Request Status Channel 13
776#define DMA_HRS_HRS14 ((uint32_t)1<<14) // Hardware Request Status Channel 14
777#define DMA_HRS_HRS15 ((uint32_t)1<<15) // Hardware Request Status Channel 15
778#define DMA_DCHPRI3 (*(volatile uint8_t *)0x40008100) // Channel n Priority Register
779#define DMA_DCHPRI2 (*(volatile uint8_t *)0x40008101) // Channel n Priority Register
780#define DMA_DCHPRI1 (*(volatile uint8_t *)0x40008102) // Channel n Priority Register
781#define DMA_DCHPRI0 (*(volatile uint8_t *)0x40008103) // Channel n Priority Register
782#define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 15)<<0) // Channel Arbitration Priority
783#define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability
784#define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption
785#define DMA_DCHPRI7 (*(volatile uint8_t *)0x40008104) // Channel n Priority Register
786#define DMA_DCHPRI6 (*(volatile uint8_t *)0x40008105) // Channel n Priority Register
787#define DMA_DCHPRI5 (*(volatile uint8_t *)0x40008106) // Channel n Priority Register
788#define DMA_DCHPRI4 (*(volatile uint8_t *)0x40008107) // Channel n Priority Register
789#define DMA_DCHPRI11 (*(volatile uint8_t *)0x40008108) // Channel n Priority Register
790#define DMA_DCHPRI10 (*(volatile uint8_t *)0x40008109) // Channel n Priority Register
791#define DMA_DCHPRI9 (*(volatile uint8_t *)0x4000810A) // Channel n Priority Register
792#define DMA_DCHPRI8 (*(volatile uint8_t *)0x4000810B) // Channel n Priority Register
793#define DMA_DCHPRI15 (*(volatile uint8_t *)0x4000810C) // Channel n Priority Register
794#define DMA_DCHPRI14 (*(volatile uint8_t *)0x4000810D) // Channel n Priority Register
795#define DMA_DCHPRI13 (*(volatile uint8_t *)0x4000810E) // Channel n Priority Register
796#define DMA_DCHPRI12 (*(volatile uint8_t *)0x4000810F) // Channel n Priority Register
797
798
799#define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11)
800#define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8)
801#define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3)
802#define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0)
803#define DMA_TCD_ATTR_SIZE_8BIT 0
804#define DMA_TCD_ATTR_SIZE_16BIT 1
805#define DMA_TCD_ATTR_SIZE_32BIT 2
806#define DMA_TCD_ATTR_SIZE_16BYTE 4
807#define DMA_TCD_ATTR_SIZE_32BYTE 5 // caution: this might not be supported in newer chips?
808#define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14)
809#define DMA_TCD_CSR_BWC_MASK 0xC000
810#define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0xF) << 8)
811#define DMA_TCD_CSR_MAJORLINKCH_MASK 0x0F00
812#define DMA_TCD_CSR_DONE 0x0080
813#define DMA_TCD_CSR_ACTIVE 0x0040
814#define DMA_TCD_CSR_MAJORELINK 0x0020
815#define DMA_TCD_CSR_ESG 0x0010
816#define DMA_TCD_CSR_DREQ 0x0008
817#define DMA_TCD_CSR_INTHALF 0x0004
818#define DMA_TCD_CSR_INTMAJOR 0x0002
819#define DMA_TCD_CSR_START 0x0001
820#define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask
821#define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
822#define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask
823#define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
824#define DMA_TCD_BITER_ELINKYES_ELINK 0x8000
825#define DMA_TCD_BITER_ELINKYES_LINKCH(n) (((n) & 0xF) << 9)
826#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK 0x1E00
827#define DMA_TCD_BITER_ELINKYES_BITER(n) (((n) & 0x1FF) << 0)
828#define DMA_TCD_BITER_ELINKYES_BITER_MASK 0x01FF
829#define DMA_TCD_CITER_ELINKYES_ELINK 0x8000
830#define DMA_TCD_CITER_ELINKYES_LINKCH(n) (((n) & 0xF) << 9)
831#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK 0x1E00
832#define DMA_TCD_CITER_ELINKYES_CITER(n) (((n) & 0x1FF) << 0)
833#define DMA_TCD_CITER_ELINKYES_CITER_MASK 0x01FF
834#define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable
835#define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable
836#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled
837#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled
838#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset
839
840#define DMA_TCD0_SADDR (*(volatile const void * volatile *)0x40009000) // TCD Source Address
841#define DMA_TCD0_SOFF (*(volatile int16_t *)0x40009004) // TCD Signed Source Address Offset
842#define DMA_TCD0_ATTR (*(volatile uint16_t *)0x40009006) // TCD Transfer Attributes
843#define DMA_TCD0_NBYTES_MLNO (*(volatile uint32_t *)0x40009008) // TCD Minor Byte Count (Minor Loop Disabled)
844#define DMA_TCD0_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009008) // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
845#define DMA_TCD0_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009008) // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
846#define DMA_TCD0_SLAST (*(volatile int32_t *)0x4000900C) // TCD Last Source Address Adjustment
847#define DMA_TCD0_DADDR (*(volatile void * volatile *)0x40009010) // TCD Destination Address
848#define DMA_TCD0_DOFF (*(volatile int16_t *)0x40009014) // TCD Signed Destination Address Offset
849#define DMA_TCD0_CITER_ELINKYES (*(volatile uint16_t *)0x40009016) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
850#define DMA_TCD0_CITER_ELINKNO (*(volatile uint16_t *)0x40009016) // ??
851#define DMA_TCD0_DLASTSGA (*(volatile int32_t *)0x40009018) // TCD Last Destination Address Adjustment/Scatter Gather Address
852#define DMA_TCD0_CSR (*(volatile uint16_t *)0x4000901C) // TCD Control and Status
853#define DMA_TCD0_BITER_ELINKYES (*(volatile uint16_t *)0x4000901E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
854#define DMA_TCD0_BITER_ELINKNO (*(volatile uint16_t *)0x4000901E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
855
856#define DMA_TCD1_SADDR (*(volatile const void * volatile *)0x40009020) // TCD Source Address
857#define DMA_TCD1_SOFF (*(volatile int16_t *)0x40009024) // TCD Signed Source Address Offset
858#define DMA_TCD1_ATTR (*(volatile uint16_t *)0x40009026) // TCD Transfer Attributes
859#define DMA_TCD1_NBYTES_MLNO (*(volatile uint32_t *)0x40009028) // TCD Minor Byte Count, Minor Loop Disabled
860#define DMA_TCD1_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009028) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
861#define DMA_TCD1_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009028) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
862#define DMA_TCD1_SLAST (*(volatile int32_t *)0x4000902C) // TCD Last Source Address Adjustment
863#define DMA_TCD1_DADDR (*(volatile void * volatile *)0x40009030) // TCD Destination Address
864#define DMA_TCD1_DOFF (*(volatile int16_t *)0x40009034) // TCD Signed Destination Address Offset
865#define DMA_TCD1_CITER_ELINKYES (*(volatile uint16_t *)0x40009036) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
866#define DMA_TCD1_CITER_ELINKNO (*(volatile uint16_t *)0x40009036) // ??
867#define DMA_TCD1_DLASTSGA (*(volatile int32_t *)0x40009038) // TCD Last Destination Address Adjustment/Scatter Gather Address
868#define DMA_TCD1_CSR (*(volatile uint16_t *)0x4000903C) // TCD Control and Status
869#define DMA_TCD1_BITER_ELINKYES (*(volatile uint16_t *)0x4000903E) // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled
870#define DMA_TCD1_BITER_ELINKNO (*(volatile uint16_t *)0x4000903E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
871
872#define DMA_TCD2_SADDR (*(volatile const void * volatile *)0x40009040) // TCD Source Address
873#define DMA_TCD2_SOFF (*(volatile int16_t *)0x40009044) // TCD Signed Source Address Offset
874#define DMA_TCD2_ATTR (*(volatile uint16_t *)0x40009046) // TCD Transfer Attributes
875#define DMA_TCD2_NBYTES_MLNO (*(volatile uint32_t *)0x40009048) // TCD Minor Byte Count, Minor Loop Disabled
876#define DMA_TCD2_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009048) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
877#define DMA_TCD2_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009048) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
878#define DMA_TCD2_SLAST (*(volatile int32_t *)0x4000904C) // TCD Last Source Address Adjustment
879#define DMA_TCD2_DADDR (*(volatile void * volatile *)0x40009050) // TCD Destination Address
880#define DMA_TCD2_DOFF (*(volatile int16_t *)0x40009054) // TCD Signed Destination Address Offset
881#define DMA_TCD2_CITER_ELINKYES (*(volatile uint16_t *)0x40009056) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
882#define DMA_TCD2_CITER_ELINKNO (*(volatile uint16_t *)0x40009056) // ??
883#define DMA_TCD2_DLASTSGA (*(volatile int32_t *)0x40009058) // TCD Last Destination Address Adjustment/Scatter Gather Address
884#define DMA_TCD2_CSR (*(volatile uint16_t *)0x4000905C) // TCD Control and Status
885#define DMA_TCD2_BITER_ELINKYES (*(volatile uint16_t *)0x4000905E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
886#define DMA_TCD2_BITER_ELINKNO (*(volatile uint16_t *)0x4000905E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
887
888#define DMA_TCD3_SADDR (*(volatile const void * volatile *)0x40009060) // TCD Source Address
889#define DMA_TCD3_SOFF (*(volatile int16_t *)0x40009064) // TCD Signed Source Address Offset
890#define DMA_TCD3_ATTR (*(volatile uint16_t *)0x40009066) // TCD Transfer Attributes
891#define DMA_TCD3_NBYTES_MLNO (*(volatile uint32_t *)0x40009068) // TCD Minor Byte Count, Minor Loop Disabled
892#define DMA_TCD3_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009068) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
893#define DMA_TCD3_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009068) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
894#define DMA_TCD3_SLAST (*(volatile int32_t *)0x4000906C) // TCD Last Source Address Adjustment
895#define DMA_TCD3_DADDR (*(volatile void * volatile *)0x40009070) // TCD Destination Address
896#define DMA_TCD3_DOFF (*(volatile int16_t *)0x40009074) // TCD Signed Destination Address Offset
897#define DMA_TCD3_CITER_ELINKYES (*(volatile uint16_t *)0x40009076) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
898#define DMA_TCD3_CITER_ELINKNO (*(volatile uint16_t *)0x40009076) // ??
899#define DMA_TCD3_DLASTSGA (*(volatile int32_t *)0x40009078) // TCD Last Destination Address Adjustment/Scatter Gather Address
900#define DMA_TCD3_CSR (*(volatile uint16_t *)0x4000907C) // TCD Control and Status
901#define DMA_TCD3_BITER_ELINKYES (*(volatile uint16_t *)0x4000907E) // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
902#define DMA_TCD3_BITER_ELINKNO (*(volatile uint16_t *)0x4000907E) // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
903
904#define DMA_TCD4_SADDR (*(volatile const void * volatile *)0x40009080) // TCD Source Addr
905#define DMA_TCD4_SOFF (*(volatile int16_t *)0x40009084) // TCD Signed Source Address Offset
906#define DMA_TCD4_ATTR (*(volatile uint16_t *)0x40009086) // TCD Transfer Attributes
907#define DMA_TCD4_NBYTES_MLNO (*(volatile uint32_t *)0x40009088) // TCD Minor Byte Count
908#define DMA_TCD4_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009088) // TCD Signed Minor Loop Offset
909#define DMA_TCD4_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009088) // TCD Signed Minor Loop Offset
910#define DMA_TCD4_SLAST (*(volatile int32_t *)0x4000908C) // TCD Last Source Addr Adj.
911#define DMA_TCD4_DADDR (*(volatile void * volatile *)0x40009090) // TCD Destination Address
912#define DMA_TCD4_DOFF (*(volatile int16_t *)0x40009094) // TCD Signed Dest Address Offset
913#define DMA_TCD4_CITER_ELINKYES (*(volatile uint16_t *)0x40009096) // TCD Current Minor Loop Link
914#define DMA_TCD4_CITER_ELINKNO (*(volatile uint16_t *)0x40009096) // ??
915#define DMA_TCD4_DLASTSGA (*(volatile int32_t *)0x40009098) // TCD Last Destination Addr Adj
916#define DMA_TCD4_CSR (*(volatile uint16_t *)0x4000909C) // TCD Control and Status
917#define DMA_TCD4_BITER_ELINKYES (*(volatile uint16_t *)0x4000909E) // TCD Beginning Minor Loop Link
918#define DMA_TCD4_BITER_ELINKNO (*(volatile uint16_t *)0x4000909E) // TCD Beginning Minor Loop Link
919
920#define DMA_TCD5_SADDR (*(volatile const void * volatile *)0x400090A0) // TCD Source Addr
921#define DMA_TCD5_SOFF (*(volatile int16_t *)0x400090A4) // TCD Signed Source Address Offset
922#define DMA_TCD5_ATTR (*(volatile uint16_t *)0x400090A6) // TCD Transfer Attributes
923#define DMA_TCD5_NBYTES_MLNO (*(volatile uint32_t *)0x400090A8) // TCD Minor Byte Count
924#define DMA_TCD5_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090A8) // TCD Signed Minor Loop Offset
925#define DMA_TCD5_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090A8) // TCD Signed Minor Loop Offset
926#define DMA_TCD5_SLAST (*(volatile int32_t *)0x400090AC) // TCD Last Source Addr Adj.
927#define DMA_TCD5_DADDR (*(volatile void * volatile *)0x400090B0) // TCD Destination Address
928#define DMA_TCD5_DOFF (*(volatile int16_t *)0x400090B4) // TCD Signed Dest Address Offset
929#define DMA_TCD5_CITER_ELINKYES (*(volatile uint16_t *)0x400090B6) // TCD Current Minor Loop Link
930#define DMA_TCD5_CITER_ELINKNO (*(volatile uint16_t *)0x400090B6) // ??
931#define DMA_TCD5_DLASTSGA (*(volatile int32_t *)0x400090B8) // TCD Last Destination Addr Adj
932#define DMA_TCD5_CSR (*(volatile uint16_t *)0x400090BC) // TCD Control and Status
933#define DMA_TCD5_BITER_ELINKYES (*(volatile uint16_t *)0x400090BE) // TCD Beginning Minor Loop Link
934#define DMA_TCD5_BITER_ELINKNO (*(volatile uint16_t *)0x400090BE) // TCD Beginning Minor Loop Link
935
936#define DMA_TCD6_SADDR (*(volatile const void * volatile *)0x400090C0) // TCD Source Addr
937#define DMA_TCD6_SOFF (*(volatile int16_t *)0x400090C4) // TCD Signed Source Address Offset
938#define DMA_TCD6_ATTR (*(volatile uint16_t *)0x400090C6) // TCD Transfer Attributes
939#define DMA_TCD6_NBYTES_MLNO (*(volatile uint32_t *)0x400090C8) // TCD Minor Byte Count
940#define DMA_TCD6_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090C8) // TCD Signed Minor Loop Offset
941#define DMA_TCD6_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090C8) // TCD Signed Minor Loop Offset
942#define DMA_TCD6_SLAST (*(volatile int32_t *)0x400090CC) // TCD Last Source Addr Adj.
943#define DMA_TCD6_DADDR (*(volatile void * volatile *)0x400090D0) // TCD Destination Address
944#define DMA_TCD6_DOFF (*(volatile int16_t *)0x400090D4) // TCD Signed Dest Address Offset
945#define DMA_TCD6_CITER_ELINKYES (*(volatile uint16_t *)0x400090D6) // TCD Current Minor Loop Link
946#define DMA_TCD6_CITER_ELINKNO (*(volatile uint16_t *)0x400090D6) // ??
947#define DMA_TCD6_DLASTSGA (*(volatile int32_t *)0x400090D8) // TCD Last Destination Addr Adj
948#define DMA_TCD6_CSR (*(volatile uint16_t *)0x400090DC) // TCD Control and Status
949#define DMA_TCD6_BITER_ELINKYES (*(volatile uint16_t *)0x400090DE) // TCD Beginning Minor Loop Link
950#define DMA_TCD6_BITER_ELINKNO (*(volatile uint16_t *)0x400090DE) // TCD Beginning Minor Loop Link
951
952#define DMA_TCD7_SADDR (*(volatile const void * volatile *)0x400090E0) // TCD Source Addr
953#define DMA_TCD7_SOFF (*(volatile int16_t *)0x400090E4) // TCD Signed Source Address Offset
954#define DMA_TCD7_ATTR (*(volatile uint16_t *)0x400090E6) // TCD Transfer Attributes
955#define DMA_TCD7_NBYTES_MLNO (*(volatile uint32_t *)0x400090E8) // TCD Minor Byte Count
956#define DMA_TCD7_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090E8) // TCD Signed Minor Loop Offset
957#define DMA_TCD7_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090E8) // TCD Signed Minor Loop Offset
958#define DMA_TCD7_SLAST (*(volatile int32_t *)0x400090EC) // TCD Last Source Addr Adj.
959#define DMA_TCD7_DADDR (*(volatile void * volatile *)0x400090F0) // TCD Destination Address
960#define DMA_TCD7_DOFF (*(volatile int16_t *)0x400090F4) // TCD Signed Dest Address Offset
961#define DMA_TCD7_CITER_ELINKYES (*(volatile uint16_t *)0x400090F6) // TCD Current Minor Loop Link
962#define DMA_TCD7_CITER_ELINKNO (*(volatile uint16_t *)0x400090F6) // ??
963#define DMA_TCD7_DLASTSGA (*(volatile int32_t *)0x400090F8) // TCD Last Destination Addr Adj
964#define DMA_TCD7_CSR (*(volatile uint16_t *)0x400090FC) // TCD Control and Status
965#define DMA_TCD7_BITER_ELINKYES (*(volatile uint16_t *)0x400090FE) // TCD Beginning Minor Loop Link
966#define DMA_TCD7_BITER_ELINKNO (*(volatile uint16_t *)0x400090FE) // TCD Beginning Minor Loop Link
967
968#define DMA_TCD8_SADDR (*(volatile const void * volatile *)0x40009100) // TCD Source Addr
969#define DMA_TCD8_SOFF (*(volatile int16_t *)0x40009104) // TCD Signed Source Address Offset
970#define DMA_TCD8_ATTR (*(volatile uint16_t *)0x40009106) // TCD Transfer Attributes
971#define DMA_TCD8_NBYTES_MLNO (*(volatile uint32_t *)0x40009108) // TCD Minor Byte Count
972#define DMA_TCD8_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009108) // TCD Signed Minor Loop Offset
973#define DMA_TCD8_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009108) // TCD Signed Minor Loop Offset
974#define DMA_TCD8_SLAST (*(volatile int32_t *)0x4000910C) // TCD Last Source Addr Adj.
975#define DMA_TCD8_DADDR (*(volatile void * volatile *)0x40009110) // TCD Destination Address
976#define DMA_TCD8_DOFF (*(volatile int16_t *)0x40009114) // TCD Signed Dest Address Offset
977#define DMA_TCD8_CITER_ELINKYES (*(volatile uint16_t *)0x40009116) // TCD Current Minor Loop Link
978#define DMA_TCD8_CITER_ELINKNO (*(volatile uint16_t *)0x40009116) // ??
979#define DMA_TCD8_DLASTSGA (*(volatile int32_t *)0x40009118) // TCD Last Destination Addr Adj
980#define DMA_TCD8_CSR (*(volatile uint16_t *)0x4000911C) // TCD Control and Status
981#define DMA_TCD8_BITER_ELINKYES (*(volatile uint16_t *)0x4000911E) // TCD Beginning Minor Loop Link
982#define DMA_TCD8_BITER_ELINKNO (*(volatile uint16_t *)0x4000911E) // TCD Beginning Minor Loop Link
983
984#define DMA_TCD9_SADDR (*(volatile const void * volatile *)0x40009120) // TCD Source Addr
985#define DMA_TCD9_SOFF (*(volatile int16_t *)0x40009124) // TCD Signed Source Address Offset
986#define DMA_TCD9_ATTR (*(volatile uint16_t *)0x40009126) // TCD Transfer Attributes
987#define DMA_TCD9_NBYTES_MLNO (*(volatile uint32_t *)0x40009128) // TCD Minor Byte Count
988#define DMA_TCD9_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009128) // TCD Signed Minor Loop Offset
989#define DMA_TCD9_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009128) // TCD Signed Minor Loop Offset
990#define DMA_TCD9_SLAST (*(volatile int32_t *)0x4000912C) // TCD Last Source Addr Adj.
991#define DMA_TCD9_DADDR (*(volatile void * volatile *)0x40009130) // TCD Destination Address
992#define DMA_TCD9_DOFF (*(volatile int16_t *)0x40009134) // TCD Signed Dest Address Offset
993#define DMA_TCD9_CITER_ELINKYES (*(volatile uint16_t *)0x40009136) // TCD Current Minor Loop Link
994#define DMA_TCD9_CITER_ELINKNO (*(volatile uint16_t *)0x40009136) // ??
995#define DMA_TCD9_DLASTSGA (*(volatile int32_t *)0x40009138) // TCD Last Destination Addr Adj
996#define DMA_TCD9_CSR (*(volatile uint16_t *)0x4000913C) // TCD Control and Status
997#define DMA_TCD9_BITER_ELINKYES (*(volatile uint16_t *)0x4000913E) // TCD Beginning Minor Loop Link
998#define DMA_TCD9_BITER_ELINKNO (*(volatile uint16_t *)0x4000913E) // TCD Beginning Minor Loop Link
999
1000#define DMA_TCD10_SADDR (*(volatile const void * volatile *)0x40009140) // TCD Source Addr
1001#define DMA_TCD10_SOFF (*(volatile int16_t *)0x40009144) // TCD Signed Source Address Offset
1002#define DMA_TCD10_ATTR (*(volatile uint16_t *)0x40009146) // TCD Transfer Attributes
1003#define DMA_TCD10_NBYTES_MLNO (*(volatile uint32_t *)0x40009148) // TCD Minor Byte Count
1004#define DMA_TCD10_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009148) // TCD Signed Minor Loop Offset
1005#define DMA_TCD10_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009148) // TCD Signed Minor Loop Offset
1006#define DMA_TCD10_SLAST (*(volatile int32_t *)0x4000914C) // TCD Last Source Addr Adj.
1007#define DMA_TCD10_DADDR (*(volatile void * volatile *)0x40009150) // TCD Destination Address
1008#define DMA_TCD10_DOFF (*(volatile int16_t *)0x40009154) // TCD Signed Dest Address Offset
1009#define DMA_TCD10_CITER_ELINKYES (*(volatile uint16_t *)0x40009156) // TCD Current Minor Loop Link
1010#define DMA_TCD10_CITER_ELINKNO (*(volatile uint16_t *)0x40009156) // ??
1011#define DMA_TCD10_DLASTSGA (*(volatile int32_t *)0x40009158) // TCD Last Destination Addr Adj
1012#define DMA_TCD10_CSR (*(volatile uint16_t *)0x4000915C) // TCD Control and Status
1013#define DMA_TCD10_BITER_ELINKYES (*(volatile uint16_t *)0x4000915E) // TCD Beginning Minor Loop Link
1014#define DMA_TCD10_BITER_ELINKNO (*(volatile uint16_t *)0x4000915E) // TCD Beginning Minor Loop Link
1015
1016#define DMA_TCD11_SADDR (*(volatile const void * volatile *)0x40009160) // TCD Source Addr
1017#define DMA_TCD11_SOFF (*(volatile int16_t *)0x40009164) // TCD Signed Source Address Offset
1018#define DMA_TCD11_ATTR (*(volatile uint16_t *)0x40009166) // TCD Transfer Attributes
1019#define DMA_TCD11_NBYTES_MLNO (*(volatile uint32_t *)0x40009168) // TCD Minor Byte Count
1020#define DMA_TCD11_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009168) // TCD Signed Minor Loop Offset
1021#define DMA_TCD11_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009168) // TCD Signed Minor Loop Offset
1022#define DMA_TCD11_SLAST (*(volatile int32_t *)0x4000916C) // TCD Last Source Addr Adj.
1023#define DMA_TCD11_DADDR (*(volatile void * volatile *)0x40009170) // TCD Destination Address
1024#define DMA_TCD11_DOFF (*(volatile int16_t *)0x40009174) // TCD Signed Dest Address Offset
1025#define DMA_TCD11_CITER_ELINKYES (*(volatile uint16_t *)0x40009176) // TCD Current Minor Loop Link
1026#define DMA_TCD11_CITER_ELINKNO (*(volatile uint16_t *)0x40009176) // ??
1027#define DMA_TCD11_DLASTSGA (*(volatile int32_t *)0x40009178) // TCD Last Destination Addr Adj
1028#define DMA_TCD11_CSR (*(volatile uint16_t *)0x4000917C) // TCD Control and Status
1029#define DMA_TCD11_BITER_ELINKYES (*(volatile uint16_t *)0x4000917E) // TCD Beginning Minor Loop Link
1030#define DMA_TCD11_BITER_ELINKNO (*(volatile uint16_t *)0x4000917E) // TCD Beginning Minor Loop Link
1031
1032#define DMA_TCD12_SADDR (*(volatile const void * volatile *)0x40009180) // TCD Source Addr
1033#define DMA_TCD12_SOFF (*(volatile int16_t *)0x40009184) // TCD Signed Source Address Offset
1034#define DMA_TCD12_ATTR (*(volatile uint16_t *)0x40009186) // TCD Transfer Attributes
1035#define DMA_TCD12_NBYTES_MLNO (*(volatile uint32_t *)0x40009188) // TCD Minor Byte Count
1036#define DMA_TCD12_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009188) // TCD Signed Minor Loop Offset
1037#define DMA_TCD12_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009188) // TCD Signed Minor Loop Offset
1038#define DMA_TCD12_SLAST (*(volatile int32_t *)0x4000918C) // TCD Last Source Addr Adj.
1039#define DMA_TCD12_DADDR (*(volatile void * volatile *)0x40009190) // TCD Destination Address
1040#define DMA_TCD12_DOFF (*(volatile int16_t *)0x40009194) // TCD Signed Dest Address Offset
1041#define DMA_TCD12_CITER_ELINKYES (*(volatile uint16_t *)0x40009196) // TCD Current Minor Loop Link
1042#define DMA_TCD12_CITER_ELINKNO (*(volatile uint16_t *)0x40009196) // ??
1043#define DMA_TCD12_DLASTSGA (*(volatile int32_t *)0x40009198) // TCD Last Destination Addr Adj
1044#define DMA_TCD12_CSR (*(volatile uint16_t *)0x4000919C) // TCD Control and Status
1045#define DMA_TCD12_BITER_ELINKYES (*(volatile uint16_t *)0x4000919E) // TCD Beginning Minor Loop Link
1046#define DMA_TCD12_BITER_ELINKNO (*(volatile uint16_t *)0x4000919E) // TCD Beginning Minor Loop Link
1047
1048#define DMA_TCD13_SADDR (*(volatile const void * volatile *)0x400091A0) // TCD Source Addr
1049#define DMA_TCD13_SOFF (*(volatile int16_t *)0x400091A4) // TCD Signed Source Address Offset
1050#define DMA_TCD13_ATTR (*(volatile uint16_t *)0x400091A6) // TCD Transfer Attributes
1051#define DMA_TCD13_NBYTES_MLNO (*(volatile uint32_t *)0x400091A8) // TCD Minor Byte Count
1052#define DMA_TCD13_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091A8) // TCD Signed Minor Loop Offset
1053#define DMA_TCD13_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091A8) // TCD Signed Minor Loop Offset
1054#define DMA_TCD13_SLAST (*(volatile int32_t *)0x400091AC) // TCD Last Source Addr Adj.
1055#define DMA_TCD13_DADDR (*(volatile void * volatile *)0x400091B0) // TCD Destination Address
1056#define DMA_TCD13_DOFF (*(volatile int16_t *)0x400091B4) // TCD Signed Dest Address Offset
1057#define DMA_TCD13_CITER_ELINKYES (*(volatile uint16_t *)0x400091B6) // TCD Current Minor Loop Link
1058#define DMA_TCD13_CITER_ELINKNO (*(volatile uint16_t *)0x400091B6) // ??
1059#define DMA_TCD13_DLASTSGA (*(volatile int32_t *)0x400091B8) // TCD Last Destination Addr Adj
1060#define DMA_TCD13_CSR (*(volatile uint16_t *)0x400091BC) // TCD Control and Status
1061#define DMA_TCD13_BITER_ELINKYES (*(volatile uint16_t *)0x400091BE) // TCD Beginning Minor Loop Link
1062#define DMA_TCD13_BITER_ELINKNO (*(volatile uint16_t *)0x400091BE) // TCD Beginning Minor Loop Link
1063
1064#define DMA_TCD14_SADDR (*(volatile const void * volatile *)0x400091C0) // TCD Source Addr
1065#define DMA_TCD14_SOFF (*(volatile int16_t *)0x400091C4) // TCD Signed Source Address Offset
1066#define DMA_TCD14_ATTR (*(volatile uint16_t *)0x400091C6) // TCD Transfer Attributes
1067#define DMA_TCD14_NBYTES_MLNO (*(volatile uint32_t *)0x400091C8) // TCD Minor Byte Count
1068#define DMA_TCD14_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091C8) // TCD Signed Minor Loop Offset
1069#define DMA_TCD14_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091C8) // TCD Signed Minor Loop Offset
1070#define DMA_TCD14_SLAST (*(volatile int32_t *)0x400091CC) // TCD Last Source Addr Adj.
1071#define DMA_TCD14_DADDR (*(volatile void * volatile *)0x400091D0) // TCD Destination Address
1072#define DMA_TCD14_DOFF (*(volatile int16_t *)0x400091D4) // TCD Signed Dest Address Offset
1073#define DMA_TCD14_CITER_ELINKYES (*(volatile uint16_t *)0x400091D6) // TCD Current Minor Loop Link
1074#define DMA_TCD14_CITER_ELINKNO (*(volatile uint16_t *)0x400091D6) // ??
1075#define DMA_TCD14_DLASTSGA (*(volatile int32_t *)0x400091D8) // TCD Last Destination Addr Adj
1076#define DMA_TCD14_CSR (*(volatile uint16_t *)0x400091DC) // TCD Control and Status
1077#define DMA_TCD14_BITER_ELINKYES (*(volatile uint16_t *)0x400091DE) // TCD Beginning Minor Loop Link
1078#define DMA_TCD14_BITER_ELINKNO (*(volatile uint16_t *)0x400091DE) // TCD Beginning Minor Loop Link
1079
1080#define DMA_TCD15_SADDR (*(volatile const void * volatile *)0x400091E0) // TCD Source Addr
1081#define DMA_TCD15_SOFF (*(volatile int16_t *)0x400091E4) // TCD Signed Source Address Offset
1082#define DMA_TCD15_ATTR (*(volatile uint16_t *)0x400091E6) // TCD Transfer Attributes
1083#define DMA_TCD15_NBYTES_MLNO (*(volatile uint32_t *)0x400091E8) // TCD Minor Byte Count
1084#define DMA_TCD15_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091E8) // TCD Signed Minor Loop Offset
1085#define DMA_TCD15_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091E8) // TCD Signed Minor Loop Offset
1086#define DMA_TCD15_SLAST (*(volatile int32_t *)0x400091EC) // TCD Last Source Addr Adj.
1087#define DMA_TCD15_DADDR (*(volatile void * volatile *)0x400091F0) // TCD Destination Address
1088#define DMA_TCD15_DOFF (*(volatile int16_t *)0x400091F4) // TCD Signed Dest Address Offset
1089#define DMA_TCD15_CITER_ELINKYES (*(volatile uint16_t *)0x400091F6) // TCD Current Minor Loop Link
1090#define DMA_TCD15_CITER_ELINKNO (*(volatile uint16_t *)0x400091F6) // ??
1091#define DMA_TCD15_DLASTSGA (*(volatile int32_t *)0x400091F8) // TCD Last Destination Addr Adj
1092#define DMA_TCD15_CSR (*(volatile uint16_t *)0x400091FC) // TCD Control and Status
1093#define DMA_TCD15_BITER_ELINKYES (*(volatile uint16_t *)0x400091FE) // TCD Beginning Minor Loop Link
1094#define DMA_TCD15_BITER_ELINKNO (*(volatile uint16_t *)0x400091FE) // TCD Beginning Minor Loop Link
1095
1096
1097// Chapter 22: External Watchdog Monitor (EWM)
1098#define EWM_CTRL (*(volatile uint8_t *)0x40061000) // Control Register
1099#define EWM_SERV (*(volatile uint8_t *)0x40061001) // Service Register
1100#define EWM_CMPL (*(volatile uint8_t *)0x40061002) // Compare Low Register
1101#define EWM_CMPH (*(volatile uint8_t *)0x40061003) // Compare High Register
1102
1103// Chapter 23: Watchdog Timer (WDOG)
1104#define WDOG_STCTRLH (*(volatile uint16_t *)0x40052000) // Watchdog Status and Control Register High
1105#define WDOG_STCTRLH_DISTESTWDOG ((uint16_t)0x4000) // Allows the WDOG's functional test mode to be disabled permanently.
1106#define WDOG_STCTRLH_BYTESEL(n) ((uint16_t)(((n) & 3) << 12)) // selects the byte to be tested when the watchdog is in the byte test mode.
1107#define WDOG_STCTRLH_TESTSEL ((uint16_t)0x0800)
1108#define WDOG_STCTRLH_TESTWDOG ((uint16_t)0x0400)
1109#define WDOG_STCTRLH_WAITEN ((uint16_t)0x0080)
1110#define WDOG_STCTRLH_STOPEN ((uint16_t)0x0040)
1111#define WDOG_STCTRLH_DBGEN ((uint16_t)0x0020)
1112#define WDOG_STCTRLH_ALLOWUPDATE ((uint16_t)0x0010)
1113#define WDOG_STCTRLH_WINEN ((uint16_t)0x0008)
1114#define WDOG_STCTRLH_IRQRSTEN ((uint16_t)0x0004)
1115#define WDOG_STCTRLH_CLKSRC ((uint16_t)0x0002)
1116#define WDOG_STCTRLH_WDOGEN ((uint16_t)0x0001)
1117#define WDOG_STCTRLL (*(volatile uint16_t *)0x40052002) // Watchdog Status and Control Register Low
1118#define WDOG_TOVALH (*(volatile uint16_t *)0x40052004) // Watchdog Time-out Value Register High
1119#define WDOG_TOVALL (*(volatile uint16_t *)0x40052006) // Watchdog Time-out Value Register Low
1120#define WDOG_WINH (*(volatile uint16_t *)0x40052008) // Watchdog Window Register High
1121#define WDOG_WINL (*(volatile uint16_t *)0x4005200A) // Watchdog Window Register Low
1122#define WDOG_REFRESH (*(volatile uint16_t *)0x4005200C) // Watchdog Refresh register
1123#define WDOG_UNLOCK (*(volatile uint16_t *)0x4005200E) // Watchdog Unlock register
1124#define WDOG_UNLOCK_SEQ1 ((uint16_t)0xC520)
1125#define WDOG_UNLOCK_SEQ2 ((uint16_t)0xD928)
1126#define WDOG_TMROUTH (*(volatile uint16_t *)0x40052010) // Watchdog Timer Output Register High
1127#define WDOG_TMROUTL (*(volatile uint16_t *)0x40052012) // Watchdog Timer Output Register Low
1128#define WDOG_RSTCNT (*(volatile uint16_t *)0x40052014) // Watchdog Reset Count register
1129#define WDOG_PRESC (*(volatile uint16_t *)0x40052016) // Watchdog Prescaler register
1130
1131// Chapter 24: Multipurpose Clock Generator (MCG)
1132#define MCG_C1 (*(volatile uint8_t *)0x40064000) // MCG Control 1 Register
1133#define MCG_C1_IREFSTEN ((uint8_t)0x01) // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
1134#define MCG_C1_IRCLKEN ((uint8_t)0x02) // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
1135#define MCG_C1_IREFS ((uint8_t)0x04) // Internal Reference Select, Selects the reference clock source for the FLL.
1136#define MCG_C1_FRDIV(n) ((uint8_t)(((n) & 0x07) << 3)) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
1137#define MCG_C1_CLKS(n) ((uint8_t)(((n) & 0x03) << 6)) // Clock Source Select, Selects the clock source for MCGOUTCLK
1138#define MCG_C2 (*(volatile uint8_t *)0x40064001) // MCG Control 2 Register
1139#define MCG_C2_IRCS ((uint8_t)0x01) // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
1140#define MCG_C2_LP ((uint8_t)0x02) // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
1141#define MCG_C2_EREFS ((uint8_t)0x04) // External Reference Select, Selects the source for the external reference clock.
1142#define MCG_C2_HGO0 ((uint8_t)0x08) // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
1143#define MCG_C2_RANGE0(n) ((uint8_t)(((n) & 0x03) << 4)) // Frequency Range Select, Selects the frequency range for the crystal oscillator
1144#define MCG_C2_LOCRE0 ((uint8_t)0x80) // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
1145#define MCG_C3 (*(volatile uint8_t *)0x40064002) // MCG Control 3 Register
1146#define MCG_C3_SCTRIM(n) ((uint8_t)(n)) // Slow Internal Reference Clock Trim Setting
1147#define MCG_C4 (*(volatile uint8_t *)0x40064003) // MCG Control 4 Register
1148#define MCG_C4_SCFTRIM ((uint8_t)0x01) // Slow Internal Reference Clock Fine Trim
1149#define MCG_C4_FCTRIM(n) ((uint8_t)(((n) & 0x0F) << 1)) // Fast Internal Reference Clock Trim Setting
1150#define MCG_C4_DRST_DRS(n) ((uint8_t)(((n) & 0x03) << 5)) // DCO Range Select
1151#define MCG_C4_DMX32 ((uint8_t)0x80) // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
1152#define MCG_C5 (*(volatile uint8_t *)0x40064004) // MCG Control 5 Register
1153#define MCG_C5_PRDIV0(n) ((uint8_t)((n) & 0x1F)) // PLL External Reference Divider
1154#define MCG_C5_PLLSTEN0 ((uint8_t)0x20) // PLL Stop Enable
1155#define MCG_C5_PLLCLKEN0 ((uint8_t)0x40) // PLL Clock Enable
1156#define MCG_C6 (*(volatile uint8_t *)0x40064005) // MCG Control 6 Register
1157#define MCG_C6_VDIV0(n) ((uint8_t)((n) & 0x1F)) // VCO 0 Divider
1158#define MCG_C6_CME0 ((uint8_t)0x20) // Clock Monitor Enable
1159#define MCG_C6_PLLS ((uint8_t)0x40) // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00.
1160#define MCG_C6_LOLIE0 ((uint8_t)0x80) // Loss of Lock Interrrupt Enable
1161#define MCG_S (*(volatile uint8_t *)0x40064006) // MCG Status Register
1162#define MCG_S_IRCST ((uint8_t)0x01) // Internal Reference Clock Status
1163#define MCG_S_OSCINIT0 ((uint8_t)0x02) // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
1164#define MCG_S_CLKST(n) ((uint8_t)(((n) & 0x03) << 2)) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
1165#define MCG_S_CLKST_MASK ((uint8_t)0x0C)
1166#define MCG_S_IREFST ((uint8_t)0x10) // Internal Reference Status
1167#define MCG_S_PLLST ((uint8_t)0x20) // PLL Select Status
1168#define MCG_S_LOCK0 ((uint8_t)0x40) // Lock Status, 0=PLL Unlocked, 1=PLL Locked
1169#define MCG_S_LOLS0 ((uint8_t)0x80) // Loss of Lock Status
1170#define MCG_SC (*(volatile uint8_t *)0x40064008) // MCG Status and Control Register
1171#define MCG_SC_LOCS0 ((uint8_t)0x01) // OSC0 Loss of Clock Status
1172#define MCG_SC_FCRDIV(n) ((uint8_t)(((n) & 0x07) << 1)) // Fast Clock Internal Reference Divider
1173#define MCG_SC_FLTPRSRV ((uint8_t)0x10) // FLL Filter Preserve Enable
1174#define MCG_SC_ATMF ((uint8_t)0x20) // Automatic Trim Machine Fail Flag
1175#define MCG_SC_ATMS ((uint8_t)0x40) // Automatic Trim Machine Select
1176#define MCG_SC_ATME ((uint8_t)0x80) // Automatic Trim Machine Enable
1177#define MCG_ATCVH (*(volatile uint8_t *)0x4006400A) // MCG Auto Trim Compare Value High Register
1178#define MCG_ATCVL (*(volatile uint8_t *)0x4006400B) // MCG Auto Trim Compare Value Low Register
1179#define MCG_C7 (*(volatile uint8_t *)0x4006400C) // MCG Control 7 Register
1180#define MCG_C8 (*(volatile uint8_t *)0x4006400D) // MCG Control 8 Register
1181
1182// Chapter 25: Oscillator (OSC)
1183#define OSC0_CR (*(volatile uint8_t *)0x40065000) // OSC Control Register
1184#define OSC_SC16P ((uint8_t)0x01) // Oscillator 16 pF Capacitor Load Configure
1185#define OSC_SC8P ((uint8_t)0x02) // Oscillator 8 pF Capacitor Load Configure
1186#define OSC_SC4P ((uint8_t)0x04) // Oscillator 4 pF Capacitor Load Configure
1187#define OSC_SC2P ((uint8_t)0x08) // Oscillator 2 pF Capacitor Load Configure
1188#define OSC_EREFSTEN ((uint8_t)0x20) // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
1189#define OSC_ERCLKEN ((uint8_t)0x80) // External Reference Enable, Enables external reference clock (OSCERCLK).
1190
1191// Chapter 27: Flash Memory Controller (FMC)
1192#define FMC_PFAPR (*(volatile uint32_t *)0x4001F000) // Flash Access Protection
1193#define FMC_PFB0CR (*(volatile uint32_t *)0x4001F004) // Flash Control
1194#define FMC_TAGVDW0S0 (*(volatile uint32_t *)0x4001F100) // Cache Tag Storage
1195#define FMC_TAGVDW0S1 (*(volatile uint32_t *)0x4001F104) // Cache Tag Storage
1196#define FMC_TAGVDW1S0 (*(volatile uint32_t *)0x4001F108)// Cache Tag Storage
1197#define FMC_TAGVDW1S1 (*(volatile uint32_t *)0x4001F10C)// Cache Tag Storage
1198#define FMC_TAGVDW2S0 (*(volatile uint32_t *)0x4001F110)// Cache Tag Storage
1199#define FMC_TAGVDW2S1 (*(volatile uint32_t *)0x4001F114)// Cache Tag Storage
1200#define FMC_TAGVDW3S0 (*(volatile uint32_t *)0x4001F118)// Cache Tag Storage
1201#define FMC_TAGVDW3S1 (*(volatile uint32_t *)0x4001F11C)// Cache Tag Storage
1202#define FMC_DATAW0S0 (*(volatile uint32_t *)0x4001F200)// Cache Data Storage
1203#define FMC_DATAW0S1 (*(volatile uint32_t *)0x4001F204)// Cache Data Storage
1204#define FMC_DATAW1S0 (*(volatile uint32_t *)0x4001F208)// Cache Data Storage
1205#define FMC_DATAW1S1 (*(volatile uint32_t *)0x4001F20C)// Cache Data Storage
1206#define FMC_DATAW2S0 (*(volatile uint32_t *)0x4001F210)// Cache Data Storage
1207#define FMC_DATAW2S1 (*(volatile uint32_t *)0x4001F214)// Cache Data Storage
1208#define FMC_DATAW3S0 (*(volatile uint32_t *)0x4001F218)// Cache Data Storage
1209#define FMC_DATAW3S1 (*(volatile uint32_t *)0x4001F21C)// Cache Data Storage
1210
1211// Chapter 28: Flash Memory Module (FTFL)
1212#define FTFL_FSTAT (*(volatile uint8_t *)0x40020000) // Flash Status Register
1213#define FTFL_FSTAT_CCIF ((uint8_t)0x80) // Command Complete Interrupt Flag
1214#define FTFL_FSTAT_RDCOLERR ((uint8_t)0x40) // Flash Read Collision Error Flag
1215#define FTFL_FSTAT_ACCERR ((uint8_t)0x20) // Flash Access Error Flag
1216#define FTFL_FSTAT_FPVIOL ((uint8_t)0x10) // Flash Protection Violation Flag
1217#define FTFL_FSTAT_MGSTAT0 ((uint8_t)0x01) // Memory Controller Command Completion Status Flag
1218#define FTFL_FCNFG (*(volatile uint8_t *)0x40020001) // Flash Configuration Register
1219#define FTFL_FCNFG_CCIE ((uint8_t)0x80) // Command Complete Interrupt Enable
1220#define FTFL_FCNFG_RDCOLLIE ((uint8_t)0x40) // Read Collision Error Interrupt Enable
1221#define FTFL_FCNFG_ERSAREQ ((uint8_t)0x20) // Erase All Request
1222#define FTFL_FCNFG_ERSSUSP ((uint8_t)0x10) // Erase Suspend
1223#define FTFL_FCNFG_PFLSH ((uint8_t)0x04) // Flash memory configuration
1224#define FTFL_FCNFG_RAMRDY ((uint8_t)0x02) // RAM Ready
1225#define FTFL_FCNFG_EEERDY ((uint8_t)0x01) // EEPROM Ready
1226#define FTFL_FSEC (*(const uint8_t *)0x40020002) // Flash Security Register
1227#define FTFL_FOPT (*(const uint8_t *)0x40020003) // Flash Option Register
1228#define FTFL_FCCOB3 (*(volatile uint8_t *)0x40020004) // Flash Common Command Object Registers
1229#define FTFL_FCCOB2 (*(volatile uint8_t *)0x40020005)
1230#define FTFL_FCCOB1 (*(volatile uint8_t *)0x40020006)
1231#define FTFL_FCCOB0 (*(volatile uint8_t *)0x40020007)
1232#define FTFL_FCCOB7 (*(volatile uint8_t *)0x40020008)
1233#define FTFL_FCCOB6 (*(volatile uint8_t *)0x40020009)
1234#define FTFL_FCCOB5 (*(volatile uint8_t *)0x4002000A)
1235#define FTFL_FCCOB4 (*(volatile uint8_t *)0x4002000B)
1236#define FTFL_FCCOBB (*(volatile uint8_t *)0x4002000C)
1237#define FTFL_FCCOBA (*(volatile uint8_t *)0x4002000D)
1238#define FTFL_FCCOB9 (*(volatile uint8_t *)0x4002000E)
1239#define FTFL_FCCOB8 (*(volatile uint8_t *)0x4002000F)
1240#define FTFL_FPROT3 (*(volatile uint8_t *)0x40020010) // Program Flash Protection Registers
1241#define FTFL_FPROT2 (*(volatile uint8_t *)0x40020011) // Program Flash Protection Registers
1242#define FTFL_FPROT1 (*(volatile uint8_t *)0x40020012) // Program Flash Protection Registers
1243#define FTFL_FPROT0 (*(volatile uint8_t *)0x40020013) // Program Flash Protection Registers
1244#define FTFL_FEPROT (*(volatile uint8_t *)0x40020016) // EEPROM Protection Register
1245#define FTFL_FDPROT (*(volatile uint8_t *)0x40020017) // Data Flash Protection Register
1246
1247// Chapter 30: Cyclic Redundancy Check (CRC)
1248#define CRC_CRC (*(volatile uint32_t *)0x40032000) // CRC Data register
1249#define CRC_GPOLY (*(volatile uint32_t *)0x40032004) // CRC Polynomial register
1250#define CRC_CTRL (*(volatile uint32_t *)0x40032008) // CRC Control register
1251
1252// Chapter 31: Analog-to-Digital Converter (ADC)
1253#define ADC0_SC1A (*(volatile uint32_t *)0x4003B000) // ADC status and control registers 1
1254#define ADC0_SC1B (*(volatile uint32_t *)0x4003B004) // ADC status and control registers 1
1255#define ADC_SC1_COCO ((uint32_t)0x80) // Conversion complete flag
1256#define ADC_SC1_AIEN ((uint32_t)0x40) // Interrupt enable
1257#define ADC_SC1_DIFF ((uint32_t)0x20) // Differential mode enable
1258#define ADC_SC1_ADCH(n) ((uint32_t)((n) & 0x1F)) // Input channel select
1259#define ADC0_CFG1 (*(volatile uint32_t *)0x4003B008) // ADC configuration register 1
1260#define ADC_CFG1_ADLPC ((uint32_t)0x80) // Low-power configuration
1261#define ADC_CFG1_ADIV(n) ((uint32_t)(((n) & 3) << 5)) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8
1262#define ADC_CFG1_ADLSMP ((uint32_t)0x10) // Sample time configuration, 0=Short, 1=Long
1263#define ADC_CFG1_MODE(n) ((uint32_t)(((n) & 3) << 2)) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit
1264#define ADC_CFG1_ADICLK(n) ((uint32_t)(((n) & 3) << 0)) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async
1265#define ADC0_CFG2 (*(volatile uint32_t *)0x4003B00C) // Configuration register 2
1266#define ADC_CFG2_MUXSEL ((uint32_t)0x10) // 0=a channels, 1=b channels
1267#define ADC_CFG2_ADACKEN ((uint32_t)0x08) // async clock enable
1268#define ADC_CFG2_ADHSC ((uint32_t)0x04) // High speed configuration
1269#define ADC_CFG2_ADLSTS(n) ((uint32_t)(((n) & 3) << 0)) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles
1270#define ADC0_RA (*(volatile uint32_t *)0x4003B010) // ADC data result register
1271#define ADC0_RB (*(volatile uint32_t *)0x4003B014) // ADC data result register
1272#define ADC0_CV1 (*(volatile uint32_t *)0x4003B018) // Compare value registers
1273#define ADC0_CV2 (*(volatile uint32_t *)0x4003B01C) // Compare value registers
1274#define ADC0_SC2 (*(volatile uint32_t *)0x4003B020) // Status and control register 2
1275#define ADC_SC2_ADACT ((uint32_t)0x80) // Conversion active
1276#define ADC_SC2_ADTRG ((uint32_t)0x40) // Conversion trigger select, 0=software, 1=hardware
1277#define ADC_SC2_ACFE ((uint32_t)0x20) // Compare function enable
1278#define ADC_SC2_ACFGT ((uint32_t)0x10) // Compare function greater than enable
1279#define ADC_SC2_ACREN ((uint32_t)0x08) // Compare function range enable
1280#define ADC_SC2_DMAEN ((uint32_t)0x04) // DMA enable
1281#define ADC_SC2_REFSEL(n) ((uint32_t)(((n) & 3) << 0)) // Voltage reference, 0=vcc/external, 1=1.2 volts
1282#define ADC0_SC3 (*(volatile uint32_t *)0x4003B024) // Status and control register 3
1283#define ADC_SC3_CAL ((uint32_t)0x80) // Calibration, 1=begin, stays set while cal in progress
1284#define ADC_SC3_CALF ((uint32_t)0x40) // Calibration failed flag
1285#define ADC_SC3_ADCO ((uint32_t)0x08) // Continuous conversion enable
1286#define ADC_SC3_AVGE ((uint32_t)0x04) // Hardware average enable
1287#define ADC_SC3_AVGS(n) ((uint32_t)(((n) & 3) << 0)) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples
1288#define ADC0_OFS (*(volatile uint32_t *)0x4003B028) // ADC offset correction register
1289#define ADC0_PG (*(volatile uint32_t *)0x4003B02C) // ADC plus-side gain register
1290#define ADC0_MG (*(volatile uint32_t *)0x4003B030) // ADC minus-side gain register
1291#define ADC0_CLPD (*(volatile uint32_t *)0x4003B034) // ADC plus-side general calibration value register
1292#define ADC0_CLPS (*(volatile uint32_t *)0x4003B038) // ADC plus-side general calibration value register
1293#define ADC0_CLP4 (*(volatile uint32_t *)0x4003B03C) // ADC plus-side general calibration value register
1294#define ADC0_CLP3 (*(volatile uint32_t *)0x4003B040) // ADC plus-side general calibration value register
1295#define ADC0_CLP2 (*(volatile uint32_t *)0x4003B044) // ADC plus-side general calibration value register
1296#define ADC0_CLP1 (*(volatile uint32_t *)0x4003B048) // ADC plus-side general calibration value register
1297#define ADC0_CLP0 (*(volatile uint32_t *)0x4003B04C) // ADC plus-side general calibration value register
1298#define ADC0_PGA (*(volatile uint32_t *)0x4003B050) // ADC Programmable Gain Amplifier
1299#define ADC_PGA_PGAEN ((uint32_t)0x00800000) // Enable
1300#define ADC_PGA_PGALPB ((uint32_t)0x00100000) // Low-Power Mode Control, 0=low power, 1=normal
1301#define ADC_PGA_PGAG(n) ((uint32_t)(((n) & 15) << 16)) // Gain, 0=1X, 1=2X, 2=4X, 3=8X, 4=16X, 5=32X, 6=64X
1302#define ADC0_CLMD (*(volatile uint32_t *)0x4003B054) // ADC minus-side general calibration value register
1303#define ADC0_CLMS (*(volatile uint32_t *)0x4003B058) // ADC minus-side general calibration value register
1304#define ADC0_CLM4 (*(volatile uint32_t *)0x4003B05C) // ADC minus-side general calibration value register
1305#define ADC0_CLM3 (*(volatile uint32_t *)0x4003B060) // ADC minus-side general calibration value register
1306#define ADC0_CLM2 (*(volatile uint32_t *)0x4003B064) // ADC minus-side general calibration value register
1307#define ADC0_CLM1 (*(volatile uint32_t *)0x4003B068) // ADC minus-side general calibration value register
1308#define ADC0_CLM0 (*(volatile uint32_t *)0x4003B06C) // ADC minus-side general calibration value register
1309
1310#define ADC1_SC1A (*(volatile uint32_t *)0x400BB000) // ADC status and control registers 1
1311#define ADC1_SC1B (*(volatile uint32_t *)0x400BB004) // ADC status and control registers 1
1312#define ADC1_CFG1 (*(volatile uint32_t *)0x400BB008) // ADC configuration register 1
1313#define ADC1_CFG2 (*(volatile uint32_t *)0x400BB00C) // Configuration register 2
1314#define ADC1_RA (*(volatile uint32_t *)0x400BB010) // ADC data result register
1315#define ADC1_RB (*(volatile uint32_t *)0x400BB014) // ADC data result register
1316#define ADC1_CV1 (*(volatile uint32_t *)0x400BB018) // Compare value registers
1317#define ADC1_CV2 (*(volatile uint32_t *)0x400BB01C) // Compare value registers
1318#define ADC1_SC2 (*(volatile uint32_t *)0x400BB020) // Status and control register 2
1319#define ADC1_SC3 (*(volatile uint32_t *)0x400BB024) // Status and control register 3
1320#define ADC1_OFS (*(volatile uint32_t *)0x400BB028) // ADC offset correction register
1321#define ADC1_PG (*(volatile uint32_t *)0x400BB02C) // ADC plus-side gain register
1322#define ADC1_MG (*(volatile uint32_t *)0x400BB030) // ADC minus-side gain register
1323#define ADC1_CLPD (*(volatile uint32_t *)0x400BB034) // ADC plus-side general calibration value register
1324#define ADC1_CLPS (*(volatile uint32_t *)0x400BB038) // ADC plus-side general calibration value register
1325#define ADC1_CLP4 (*(volatile uint32_t *)0x400BB03C) // ADC plus-side general calibration value register
1326#define ADC1_CLP3 (*(volatile uint32_t *)0x400BB040) // ADC plus-side general calibration value register
1327#define ADC1_CLP2 (*(volatile uint32_t *)0x400BB044) // ADC plus-side general calibration value register
1328#define ADC1_CLP1 (*(volatile uint32_t *)0x400BB048) // ADC plus-side general calibration value register
1329#define ADC1_CLP0 (*(volatile uint32_t *)0x400BB04C) // ADC plus-side general calibration value register
1330#define ADC1_PGA (*(volatile uint32_t *)0x400BB050) // ADC Programmable Gain Amplifier
1331#define ADC1_CLMD (*(volatile uint32_t *)0x400BB054) // ADC minus-side general calibration value register
1332#define ADC1_CLMS (*(volatile uint32_t *)0x400BB058) // ADC minus-side general calibration value register
1333#define ADC1_CLM4 (*(volatile uint32_t *)0x400BB05C) // ADC minus-side general calibration value register
1334#define ADC1_CLM3 (*(volatile uint32_t *)0x400BB060) // ADC minus-side general calibration value register
1335#define ADC1_CLM2 (*(volatile uint32_t *)0x400BB064) // ADC minus-side general calibration value register
1336#define ADC1_CLM1 (*(volatile uint32_t *)0x400BB068) // ADC minus-side general calibration value register
1337#define ADC1_CLM0 (*(volatile uint32_t *)0x400BB06C) // ADC minus-side general calibration value register
1338
1339#define DAC0_DAT0L (*(volatile uint8_t *)0x400CC000) // DAC Data Low Register
1340#define DAC0_DATH (*(volatile uint8_t *)0x400CC001) // DAC Data High Register
1341#define DAC0_DAT1L (*(volatile uint8_t *)0x400CC002) // DAC Data Low Register
1342#define DAC0_DAT2L (*(volatile uint8_t *)0x400CC004) // DAC Data Low Register
1343#define DAC0_DAT3L (*(volatile uint8_t *)0x400CC006) // DAC Data Low Register
1344#define DAC0_DAT4L (*(volatile uint8_t *)0x400CC008) // DAC Data Low Register
1345#define DAC0_DAT5L (*(volatile uint8_t *)0x400CC00A) // DAC Data Low Register
1346#define DAC0_DAT6L (*(volatile uint8_t *)0x400CC00C) // DAC Data Low Register
1347#define DAC0_DAT7L (*(volatile uint8_t *)0x400CC00E) // DAC Data Low Register
1348#define DAC0_DAT8L (*(volatile uint8_t *)0x400CC010) // DAC Data Low Register
1349#define DAC0_DAT9L (*(volatile uint8_t *)0x400CC012) // DAC Data Low Register
1350#define DAC0_DAT10L (*(volatile uint8_t *)0x400CC014) // DAC Data Low Register
1351#define DAC0_DAT11L (*(volatile uint8_t *)0x400CC016) // DAC Data Low Register
1352#define DAC0_DAT12L (*(volatile uint8_t *)0x400CC018) // DAC Data Low Register
1353#define DAC0_DAT13L (*(volatile uint8_t *)0x400CC01A) // DAC Data Low Register
1354#define DAC0_DAT14L (*(volatile uint8_t *)0x400CC01C) // DAC Data Low Register
1355#define DAC0_DAT15L (*(volatile uint8_t *)0x400CC01E) // DAC Data Low Register
1356#define DAC0_SR (*(volatile uint8_t *)0x400CC020) // DAC Status Register
1357#define DAC0_C0 (*(volatile uint8_t *)0x400CC021) // DAC Control Register
1358#define DAC_C0_DACEN 0x80 // DAC Enable
1359#define DAC_C0_DACRFS 0x40 // DAC Reference Select
1360#define DAC_C0_DACTRGSEL 0x20 // DAC Trigger Select
1361#define DAC_C0_DACSWTRG 0x10 // DAC Software Trigger
1362#define DAC_C0_LPEN 0x08 // DAC Low Power Control
1363#define DAC_C0_DACBWIEN 0x04 // DAC Buffer Watermark Interrupt Enable
1364#define DAC_C0_DACBTIEN 0x02 // DAC Buffer Read Pointer Top Flag Interrupt Enable
1365#define DAC_C0_DACBBIEN 0x01 // DAC Buffer Read Pointer Bottom Flag Interrupt Enable
1366#define DAC0_C1 (*(volatile uint8_t *)0x400CC022) // DAC Control Register 1
1367#define DAC_C1_DMAEN 0x80 // DMA Enable Select
1368#define DAC_C1_DACBFWM(n) ((((n) & 3) << 3)) // DAC Buffer Watermark Select
1369#define DAC_C1_DACBFMD(n) ((((n) & 3) << 1)) // DAC Buffer Work Mode Select
1370#define DAC_C1_DACBFEN 0x01 // DAC Buffer Enable
1371
1372#define DAC0_C2 (*(volatile uint8_t *)0x400CC023) // DAC Control Register 2
1373#define DAC_C2_DACBFRP(n) ((((n) & 15) << 4)) // DAC Buffer Read Pointer
1374#define DAC_C2_DACBFUP(n) ((((n) & 15) << 0)) // DAC Buffer Upper Limit
1375
1376
1377//#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
1378//#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
1379
1380// Chapter 32: Comparator (CMP)
1381#define CMP0_CR0 (*(volatile uint8_t *)0x40073000) // CMP Control Register 0
1382#define CMP0_CR1 (*(volatile uint8_t *)0x40073001) // CMP Control Register 1
1383#define CMP0_FPR (*(volatile uint8_t *)0x40073002) // CMP Filter Period Register
1384#define CMP0_SCR (*(volatile uint8_t *)0x40073003) // CMP Status and Control Register
1385#define CMP0_DACCR (*(volatile uint8_t *)0x40073004) // DAC Control Register
1386#define CMP0_MUXCR (*(volatile uint8_t *)0x40073005) // MUX Control Register
1387#define CMP1_CR0 (*(volatile uint8_t *)0x40073008) // CMP Control Register 0
1388#define CMP1_CR1 (*(volatile uint8_t *)0x40073009) // CMP Control Register 1
1389#define CMP1_FPR (*(volatile uint8_t *)0x4007300A) // CMP Filter Period Register
1390#define CMP1_SCR (*(volatile uint8_t *)0x4007300B) // CMP Status and Control Register
1391#define CMP1_DACCR (*(volatile uint8_t *)0x4007300C) // DAC Control Register
1392#define CMP1_MUXCR (*(volatile uint8_t *)0x4007300D) // MUX Control Register
1393
1394// Chapter 33: Voltage Reference (VREFV1)
1395#define VREF_TRM (*(volatile uint8_t *)0x40074000) // VREF Trim Register
1396#define VREF_TRM_CHOPEN ((uint8_t)0x40) // Chop oscillator enable
1397#define VREF_TRM_TRIM(n) ((n) & 0x3F) // Trim bits
1398#define VREF_SC (*(volatile uint8_t *)0x40074001) // VREF Status and Control Register
1399#define VREF_SC_VREFEN ((uint8_t)0x80) // Internal Voltage Reference enable
1400#define VREF_SC_REGEN ((uint8_t)0x40) // Regulator enable
1401#define VREF_SC_ICOMPEN ((uint8_t)0x20) // Second order curvature compensation enable
1402#define VREF_SC_VREFST ((uint8_t)0x04) // Internal Voltage Reference stable flag
1403#define VREF_SC_MODE_LV(n) (uint8_t)(((n) & 3) << 0) // Buffer Mode selection: 0=Bandgap on only
1404 // 1=High power buffer mode,
1405 // 2=Low-power buffer mode
1406
1407// Chapter 34: Programmable Delay Block (PDB)
1408#define PDB0_SC (*(volatile uint32_t *)0x40036000) // Status and Control Register
1409#define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select
1410#define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable
1411#define PDB_SC_SWTRIG 0x00010000 // Software Trigger
1412#define PDB_SC_DMAEN 0x00008000 // DMA Enable
1413#define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select
1414#define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select
1415#define PDB_SC_PDBEN 0x00000080 // PDB Enable
1416#define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag
1417#define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable.
1418#define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor
1419#define PDB_SC_CONT 0x00000002 // Continuous Mode Enable
1420#define PDB_SC_LDOK 0x00000001 // Load OK
1421#define PDB0_MOD (*(volatile uint32_t *)0x40036004) // Modulus Register
1422#define PDB0_CNT (*(volatile uint32_t *)0x40036008) // Counter Register
1423#define PDB0_IDLY (*(volatile uint32_t *)0x4003600C) // Interrupt Delay Register
1424#define PDB0_CH0C1 (*(volatile uint32_t *)0x40036010) // Channel n Control Register 1
1425#define PDB0_CH0S (*(volatile uint32_t *)0x40036014) // Channel n Status Register
1426#define PDB0_CH0DLY0 (*(volatile uint32_t *)0x40036018) // Channel n Delay 0 Register
1427#define PDB0_CH0DLY1 (*(volatile uint32_t *)0x4003601C) // Channel n Delay 1 Register
1428#define PDB0_POEN (*(volatile uint32_t *)0x40036190) // Pulse-Out n Enable Register
1429#define PDB0_PO0DLY (*(volatile uint32_t *)0x40036194) // Pulse-Out n Delay Register
1430#define PDB0_PO1DLY (*(volatile uint32_t *)0x40036198) // Pulse-Out n Delay Register
1431
1432// Chapter 35: FlexTimer Module (FTM)
1433#define FTM0_SC (*(volatile uint32_t *)0x40038000) // Status And Control
1434#define FTM_SC_TOF 0x80 // Timer Overflow Flag
1435#define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable
1436#define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select
1437#define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection
1438#define FTM_SC_CLKS_MASK 0x18
1439#define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection
1440#define FTM_SC_PS_MASK 0x07
1441#define FTM0_CNT (*(volatile uint32_t *)0x40038004) // Counter
1442#define FTM0_MOD (*(volatile uint32_t *)0x40038008) // Modulo
1443#define FTM0_C0SC (*(volatile uint32_t *)0x4003800C) // Channel 0 Status And Control
1444#define FTM_CSC_CHF 0x80 // Channel Flag
1445#define FTM_CSC_CHIE 0x40 // Channel Interrupt Enable
1446#define FTM_CSC_MSB 0x20 // Channel Mode Select
1447#define FTM_CSC_MSA 0x10 // Channel Mode Select
1448#define FTM_CSC_ELSB 0x08 // Edge or Level Select
1449#define FTM_CSC_ELSA 0x04 // Edge or Level Select
1450#define FTM_CSC_DMA 0x01 // DMA Enable
1451#define FTM0_C0V (*(volatile uint32_t *)0x40038010) // Channel 0 Value
1452#define FTM0_C1SC (*(volatile uint32_t *)0x40038014) // Channel 1 Status And Control
1453#define FTM0_C1V (*(volatile uint32_t *)0x40038018) // Channel 1 Value
1454#define FTM0_C2SC (*(volatile uint32_t *)0x4003801C) // Channel 2 Status And Control
1455#define FTM0_C2V (*(volatile uint32_t *)0x40038020) // Channel 2 Value
1456#define FTM0_C3SC (*(volatile uint32_t *)0x40038024) // Channel 3 Status And Control
1457#define FTM0_C3V (*(volatile uint32_t *)0x40038028) // Channel 3 Value
1458#define FTM0_C4SC (*(volatile uint32_t *)0x4003802C) // Channel 4 Status And Control
1459#define FTM0_C4V (*(volatile uint32_t *)0x40038030) // Channel 4 Value
1460#define FTM0_C5SC (*(volatile uint32_t *)0x40038034) // Channel 5 Status And Control
1461#define FTM0_C5V (*(volatile uint32_t *)0x40038038) // Channel 5 Value
1462#define FTM0_C6SC (*(volatile uint32_t *)0x4003803C) // Channel 6 Status And Control
1463#define FTM0_C6V (*(volatile uint32_t *)0x40038040) // Channel 6 Value
1464#define FTM0_C7SC (*(volatile uint32_t *)0x40038044) // Channel 7 Status And Control
1465#define FTM0_C7V (*(volatile uint32_t *)0x40038048) // Channel 7 Value
1466#define FTM0_CNTIN (*(volatile uint32_t *)0x4003804C) // Counter Initial Value
1467#define FTM0_STATUS (*(volatile uint32_t *)0x40038050) // Capture And Compare Status
1468#define FTM_STATUS_CH7F 0x80 //
1469#define FTM_STATUS_CH6F 0x40 //
1470#define FTM_STATUS_CH5F 0x20 //
1471#define FTM_STATUS_CH4F 0x10 //
1472#define FTM_STATUS_CH3F 0x08 //
1473#define FTM_STATUS_CH2F 0x04 //
1474#define FTM_STATUS_CH1F 0x02 //
1475#define FTM_STATUS_CH0F 0x01 //
1476#define FTM0_MODE (*(volatile uint32_t *)0x40038054) // Features Mode Selection
1477#define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable
1478#define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode
1479#define FTM_MODE_FAULTM_MASK 0x60
1480#define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable
1481#define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode
1482#define FTM_MODE_WPDIS 0x04 // Write Protection Disable
1483#define FTM_MODE_INIT 0x02 // Initialize The Channels Output
1484#define FTM_MODE_FTMEN 0x01 // FTM Enable
1485#define FTM0_SYNC (*(volatile uint32_t *)0x40038058) // Synchronization
1486#define FTM_SYNC_SWSYNC 0x80 //
1487#define FTM_SYNC_TRIG2 0x40 //
1488#define FTM_SYNC_TRIG1 0x20 //
1489#define FTM_SYNC_TRIG0 0x10 //
1490#define FTM_SYNC_SYNCHOM 0x08 //
1491#define FTM_SYNC_REINIT 0x04 //
1492#define FTM_SYNC_CNTMAX 0x02 //
1493#define FTM_SYNC_CNTMIN 0x01 //
1494#define FTM0_OUTINIT (*(volatile uint32_t *)0x4003805C) // Initial State For Channels Output
1495#define FTM_OUTINIT_CH7OI 0x80 //
1496#define FTM_OUTINIT_CH6OI 0x40 //
1497#define FTM_OUTINIT_CH5OI 0x20 //
1498#define FTM_OUTINIT_CH4OI 0x10 //
1499#define FTM_OUTINIT_CH3OI 0x08 //
1500#define FTM_OUTINIT_CH2OI 0x04 //
1501#define FTM_OUTINIT_CH1OI 0x02 //
1502#define FTM_OUTINIT_CH0OI 0x01 //
1503#define FTM0_OUTMASK (*(volatile uint32_t *)0x40038060) // Output Mask
1504#define FTM_OUTMASK_CH7OM 0x80 //
1505#define FTM_OUTMASK_CH6OM 0x40 //
1506#define FTM_OUTMASK_CH5OM 0x20 //
1507#define FTM_OUTMASK_CH4OM 0x10 //
1508#define FTM_OUTMASK_CH3OM 0x08 //
1509#define FTM_OUTMASK_CH2OM 0x04 //
1510#define FTM_OUTMASK_CH1OM 0x02 //
1511#define FTM_OUTMASK_CH0OM 0x01 //
1512#define FTM0_COMBINE (*(volatile uint32_t *)0x40038064) // Function For Linked Channels
1513#define FTM_COMBINE_FAULTEN3 0x40000000 // Enable the fault control, ch #6 & #7
1514#define FTM_COMBINE_SYNCEN3 0x20000000 // Enable PWM sync of C6V & C7V
1515#define FTM_COMBINE_DTEN3 0x10000000 // Enable deadtime insertion, ch #6 & #7
1516#define FTM_COMBINE_DECAP3 0x08000000 // Dual Edge Capture Mode
1517#define FTM_COMBINE_DECAPEN3 0x04000000 // Dual Edge Capture Mode Enable
1518#define FTM_COMBINE_COMP3 0x02000000 // Complement Of Channel #6 & #7
1519#define FTM_COMBINE_COMBINE3 0x01000000 // Combine Channels #6 & #7
1520#define FTM_COMBINE_FAULTEN2 0x00400000 // Enable the fault control, ch #4 & #5
1521#define FTM_COMBINE_SYNCEN2 0x00200000 // Enable PWM sync of C4V & C5V
1522#define FTM_COMBINE_DTEN2 0x00100000 // Enable deadtime insertion, ch #4 & #5
1523#define FTM_COMBINE_DECAP2 0x00080000 // Dual Edge Capture Mode
1524#define FTM_COMBINE_DECAPEN2 0x00040000 // Dual Edge Capture Mode Enable
1525#define FTM_COMBINE_COMP2 0x00020000 // Complement Of Channel #4 & #5
1526#define FTM_COMBINE_COMBINE2 0x00010000 // Combine Channels #4 & #5
1527#define FTM_COMBINE_FAULTEN1 0x00004000 // Enable the fault control, ch #2 & #3
1528#define FTM_COMBINE_SYNCEN1 0x00002000 // Enable PWM sync of C2V & C3V
1529#define FTM_COMBINE_DTEN1 0x00001000 // Enable deadtime insertion, ch #2 & #3
1530#define FTM_COMBINE_DECAP1 0x00000800 // Dual Edge Capture Mode
1531#define FTM_COMBINE_DECAPEN1 0x00000400 // Dual Edge Capture Mode Enable
1532#define FTM_COMBINE_COMP1 0x00000200 // Complement Of Channel #2 & #3
1533#define FTM_COMBINE_COMBINE1 0x00000100 // Combine Channels #2 & #3
1534#define FTM_COMBINE_FAULTEN0 0x00000040 // Enable the fault control, ch #0 & #1
1535#define FTM_COMBINE_SYNCEN0 0x00000020 // Enable PWM sync of C0V & C1V
1536#define FTM_COMBINE_DTEN0 0x00000010 // Enable deadtime insertion, ch #0 & #1
1537#define FTM_COMBINE_DECAP0 0x00000008 // Dual Edge Capture Mode
1538#define FTM_COMBINE_DECAPEN0 0x00000004 // Dual Edge Capture Mode Enable
1539#define FTM_COMBINE_COMP0 0x00000002 // Complement Of Channel #0 & #1
1540#define FTM_COMBINE_COMBINE0 0x00000001 // Combine Channels #0 & #1
1541#define FTM0_DEADTIME (*(volatile uint32_t *)0x40038068) // Deadtime Insertion Control
1542#define FTM_DEADTIME_DTPS(n) (((n) & 3) << 6) // Prescaler Value, 0=1x, 2=4x, 3=16x
1543#define FTM_DEADTIME_DTPS_MASK 0xC0
1544#define FTM_DEADTIME_DTVAL(n) (((n) & 63) << 0) // Deadtime Value
1545#define FTM_DEADTIME_DTVAL_MASK 0x3F
1546#define FTM0_EXTTRIG (*(volatile uint32_t *)0x4003806C) // FTM External Trigger
1547#define FTM_EXTTRIG_TRIGF 0x80 // Channel Trigger Flag
1548#define FTM_EXTTRIG_INITTRIGEN 0x40 // Initialization Trigger Enable
1549#define FTM_EXTTRIG_CH1TRIG 0x20 // Channel 1 Trigger Enable
1550#define FTM_EXTTRIG_CH0TRIG 0x10 // Channel 0 Trigger Enable
1551#define FTM_EXTTRIG_CH5TRIG 0x08 // Channel 5 Trigger Enable
1552#define FTM_EXTTRIG_CH4TRIG 0x04 // Channel 4 Trigger Enable
1553#define FTM_EXTTRIG_CH3TRIG 0x02 // Channel 3 Trigger Enable
1554#define FTM_EXTTRIG_CH2TRIG 0x01 // Channel 2 Trigger Enable
1555#define FTM0_POL (*(volatile uint32_t *)0x40038070) // Channels Polarity
1556#define FTM_POL_POL7 0x80 // Channel 7 Polarity, 0=active high, 1=active low
1557#define FTM_POL_POL6 0x40 // Channel 6 Polarity, 0=active high, 1=active low
1558#define FTM_POL_POL5 0x20 // Channel 5 Polarity, 0=active high, 1=active low
1559#define FTM_POL_POL4 0x10 // Channel 4 Polarity, 0=active high, 1=active low
1560#define FTM_POL_POL3 0x08 // Channel 3 Polarity, 0=active high, 1=active low
1561#define FTM_POL_POL2 0x04 // Channel 2 Polarity, 0=active high, 1=active low
1562#define FTM_POL_POL1 0x02 // Channel 1 Polarity, 0=active high, 1=active low
1563#define FTM_POL_POL0 0x01 // Channel 0 Polarity, 0=active high, 1=active low
1564#define FTM0_FMS (*(volatile uint32_t *)0x40038074) // Fault Mode Status
1565#define FTM_FMS_FAULTF 0x80 // Fault Detection Flag
1566#define FTM_FMS_WPEN 0x40 // Write Protection Enable
1567#define FTM_FMS_FAULTIN 0x20 // Fault Inputs
1568#define FTM_FMS_FAULTF3 0x08 // Fault Detection Flag 3
1569#define FTM_FMS_FAULTF2 0x04 // Fault Detection Flag 2
1570#define FTM_FMS_FAULTF1 0x02 // Fault Detection Flag 1
1571#define FTM_FMS_FAULTF0 0x01 // Fault Detection Flag 0
1572#define FTM0_FILTER (*(volatile uint32_t *)0x40038078) // Input Capture Filter Control
1573#define FTM_FILTER_CH3FVAL(n) (((n) & 15) << 12) // Channel 3 Input Filter
1574#define FTM_FILTER_CH2FVAL(n) (((n) & 15) << 8) // Channel 2 Input Filter
1575#define FTM_FILTER_CH1FVAL(n) (((n) & 15) << 4) // Channel 1 Input Filter
1576#define FTM_FILTER_CH0FVAL(n) (((n) & 15) << 0) // Channel 0 Input Filter
1577#define FTM_FILTER_CH3FVAL_MASK 0xF000
1578#define FTM_FILTER_CH2FVAL_MASK 0x0F00
1579#define FTM_FILTER_CH1FVAL_MASK 0x00F0
1580#define FTM_FILTER_CH0FVAL_MASK 0x000F
1581#define FTM0_FLTCTRL (*(volatile uint32_t *)0x4003807C) // Fault Control
1582#define FTM_FLTCTRL_FFVAL(n) (((n) & 15) << 8) // Fault Input Filter Value, 0=disable
1583#define FTM_FLTCTRL_FFVAL_MASK 0xF00
1584#define FTM_FLTCTRL_FFLTR3EN 0x80 // Fault Input 3 Filter Enable
1585#define FTM_FLTCTRL_FFLTR2EN 0x40 // Fault Input 2 Filter Enable
1586#define FTM_FLTCTRL_FFLTR1EN 0x20 // Fault Input 1 Filter Enable
1587#define FTM_FLTCTRL_FFLTR0EN 0x10 // Fault Input 0 Filter Enable
1588#define FTM_FLTCTRL_FAULT3EN 0x08 // Fault Input 3 Enable
1589#define FTM_FLTCTRL_FAULT2EN 0x04 // Fault Input 2 Enable
1590#define FTM_FLTCTRL_FAULT1EN 0x02 // Fault Input 1 Enable
1591#define FTM_FLTCTRL_FAULT0EN 0x01 // Fault Input 0 Enable
1592#define FTM0_QDCTRL (*(volatile uint32_t *)0x40038080) // Quadrature Decoder Control And Status
1593#define FTM_QDCTRL_PHAFLTREN 0x80 // Phase A Input Filter Enable
1594#define FTM_QDCTRL_PHBFLTREN 0x40 // Phase B Input Filter Enable
1595#define FTM_QDCTRL_PHAPOL 0x20 // Phase A Input Polarity
1596#define FTM_QDCTRL_PHBPOL 0x10 // Phase B Input Polarity
1597#define FTM_QDCTRL_QUADMODE 0x08 // Quadrature Decoder Mode
1598#define FTM_QDCTRL_QUADIR 0x04 // FTM Counter Direction In Quadrature Decoder Mode
1599#define FTM_QDCTRL_TOFDIR 0x02 // Timer Overflow Direction In Quadrature Decoder Mode
1600#define FTM_QDCTRL_QUADEN 0x01 // Quadrature Decoder Mode Enable
1601#define FTM0_CONF (*(volatile uint32_t *)0x40038084) // Configuration
1602#define FTM_CONF_GTBEOUT 0x400 // Global Time Base Output
1603#define FTM_CONF_GTBEEN 0x200 // Global Time Base Enable
1604#define FTM_CONF_BDMMODE (((n) & 3) << 6) // Behavior when in debug mode
1605#define FTM_CONF_NUMTOF (((n) & 31) << 0) // ratio of counter overflows to TOF bit set
1606#define FTM0_FLTPOL (*(volatile uint32_t *)0x40038088) // FTM Fault Input Polarity
1607#define FTM_FLTPOL_FLT3POL 0x08 // Fault Input 3 Polarity
1608#define FTM_FLTPOL_FLT2POL 0x04 // Fault Input 2 Polarity
1609#define FTM_FLTPOL_FLT1POL 0x02 // Fault Input 1 Polarity
1610#define FTM_FLTPOL_FLT0POL 0x01 // Fault Input 0 Polarity
1611#define FTM0_SYNCONF (*(volatile uint32_t *)0x4003808C) // Synchronization Configuration
1612#define FTM_SYNCONF_HWSOC 0x100000 // Software output control synchronization is activated by a hardware trigger.
1613#define FTM_SYNCONF_HWINVC 0x080000 // Inverting control synchronization is activated by a hardware trigger.
1614#define FTM_SYNCONF_HWOM 0x040000 // Output mask synchronization is activated by a hardware trigger.
1615#define FTM_SYNCONF_HWWRBUF 0x020000 // MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
1616#define FTM_SYNCONF_HWRSTCNT 0x010000 // FTM counter synchronization is activated by a hardware trigger.
1617#define FTM_SYNCONF_SWSOC 0x001000 // Software output control synchronization is activated by the software trigger.
1618#define FTM_SYNCONF_SWINVC 0x000800 // Inverting control synchronization is activated by the software trigger.
1619#define FTM_SYNCONF_SWOM 0x000400 // Output mask synchronization is activated by the software trigger.
1620#define FTM_SYNCONF_SWWRBUF 0x000200 // MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
1621#define FTM_SYNCONF_SWRSTCNT 0x000100 // FTM counter synchronization is activated by the software trigger.
1622#define FTM_SYNCONF_SYNCMODE 0x000080 // Synchronization Mode, 0=Legacy, 1=Enhanced PWM
1623#define FTM_SYNCONF_SWOC 0x000020 // SWOCTRL Register Synchronization
1624#define FTM_SYNCONF_INVC 0x000010 // INVCTRL Register Synchronization
1625#define FTM_SYNCONF_CNTINC 0x000004 // CNTIN Register Synchronization
1626#define FTM_SYNCONF_HWTRIGMODE 0x000001 // Hardware Trigger Mode
1627#define FTM0_INVCTRL (*(volatile uint32_t *)0x40038090) // FTM Inverting Control
1628#define FTM_INVCTRL_INV3EN 0x08 // Pair Channels 3 Inverting Enable
1629#define FTM_INVCTRL_INV2EN 0x04 // Pair Channels 2 Inverting Enable
1630#define FTM_INVCTRL_INV1EN 0x02 // Pair Channels 1 Inverting Enable
1631#define FTM_INVCTRL_INV0EN 0x01 // Pair Channels 0 Inverting Enable
1632#define FTM0_SWOCTRL (*(volatile uint32_t *)0x40038094) // FTM Software Output Control
1633#define FTM_SWOCTRL_CH7OCV 0x8000 // Channel 7 Software Output Control Value
1634#define FTM_SWOCTRL_CH6OCV 0x4000 // Channel 6 Software Output Control Value
1635#define FTM_SWOCTRL_CH5OCV 0x2000 // Channel 5 Software Output Control Value
1636#define FTM_SWOCTRL_CH4OCV 0x1000 // Channel 4 Software Output Control Value
1637#define FTM_SWOCTRL_CH3OCV 0x0800 // Channel 3 Software Output Control Value
1638#define FTM_SWOCTRL_CH2OCV 0x0400 // Channel 2 Software Output Control Value
1639#define FTM_SWOCTRL_CH1OCV 0x0200 // Channel 1 Software Output Control Value
1640#define FTM_SWOCTRL_CH0OCV 0x0100 // Channel 0 Software Output Control Value
1641#define FTM_SWOCTRL_CH7OC 0x0080 // Channel 7 Software Output Control Enable
1642#define FTM_SWOCTRL_CH6OC 0x0040 // Channel 6 Software Output Control Enable
1643#define FTM_SWOCTRL_CH5OC 0x0020 // Channel 5 Software Output Control Enable
1644#define FTM_SWOCTRL_CH4OC 0x0010 // Channel 4 Software Output Control Enable
1645#define FTM_SWOCTRL_CH3OC 0x0008 // Channel 3 Software Output Control Enable
1646#define FTM_SWOCTRL_CH2OC 0x0004 // Channel 2 Software Output Control Enable
1647#define FTM_SWOCTRL_CH1OC 0x0002 // Channel 1 Software Output Control Enable
1648#define FTM_SWOCTRL_CH0OC 0x0001 // Channel 0 Software Output Control Enable
1649#define FTM0_PWMLOAD (*(volatile uint32_t *)0x40038098) // FTM PWM Load
1650#define FTM_PWMLOAD_LDOK 0x200 // Enables the loading of the MOD, CNTIN, and CV registers with the values of their write buffers
1651#define FTM_PWMLOAD_CH7SEL 0x80 // Channel 7 Select
1652#define FTM_PWMLOAD_CH6SEL 0x40 // Channel 6 Select
1653#define FTM_PWMLOAD_CH5SEL 0x20 // Channel 5 Select
1654#define FTM_PWMLOAD_CH4SEL 0x10 // Channel 4 Select
1655#define FTM_PWMLOAD_CH3SEL 0x08 // Channel 4 Select
1656#define FTM_PWMLOAD_CH2SEL 0x04 // Channel 3 Select
1657#define FTM_PWMLOAD_CH1SEL 0x02 // Channel 2 Select
1658#define FTM_PWMLOAD_CH0SEL 0x01 // Channel 1 Select
1659#define FTM1_SC (*(volatile uint32_t *)0x40039000) // Status And Control
1660#define FTM1_CNT (*(volatile uint32_t *)0x40039004) // Counter
1661#define FTM1_MOD (*(volatile uint32_t *)0x40039008) // Modulo
1662#define FTM1_C0SC (*(volatile uint32_t *)0x4003900C) // Channel 0 Status And Control
1663#define FTM1_C0V (*(volatile uint32_t *)0x40039010) // Channel 0 Value
1664#define FTM1_C1SC (*(volatile uint32_t *)0x40039014) // Channel 1 Status And Control
1665#define FTM1_C1V (*(volatile uint32_t *)0x40039018) // Channel 1 Value
1666#define FTM1_CNTIN (*(volatile uint32_t *)0x4003904C) // Counter Initial Value
1667#define FTM1_STATUS (*(volatile uint32_t *)0x40039050) // Capture And Compare Status
1668#define FTM1_MODE (*(volatile uint32_t *)0x40039054) // Features Mode Selection
1669#define FTM1_SYNC (*(volatile uint32_t *)0x40039058) // Synchronization
1670#define FTM1_OUTINIT (*(volatile uint32_t *)0x4003905C) // Initial State For Channels Output
1671#define FTM1_OUTMASK (*(volatile uint32_t *)0x40039060) // Output Mask
1672#define FTM1_COMBINE (*(volatile uint32_t *)0x40039064) // Function For Linked Channels
1673#define FTM1_DEADTIME (*(volatile uint32_t *)0x40039068) // Deadtime Insertion Control
1674#define FTM1_EXTTRIG (*(volatile uint32_t *)0x4003906C) // FTM External Trigger
1675#define FTM1_POL (*(volatile uint32_t *)0x40039070) // Channels Polarity
1676#define FTM1_FMS (*(volatile uint32_t *)0x40039074) // Fault Mode Status
1677#define FTM1_FILTER (*(volatile uint32_t *)0x40039078) // Input Capture Filter Control
1678#define FTM1_FLTCTRL (*(volatile uint32_t *)0x4003907C) // Fault Control
1679#define FTM1_QDCTRL (*(volatile uint32_t *)0x40039080) // Quadrature Decoder Control And Status
1680#define FTM1_CONF (*(volatile uint32_t *)0x40039084) // Configuration
1681#define FTM1_FLTPOL (*(volatile uint32_t *)0x40039088) // FTM Fault Input Polarity
1682#define FTM1_SYNCONF (*(volatile uint32_t *)0x4003908C) // Synchronization Configuration
1683#define FTM1_INVCTRL (*(volatile uint32_t *)0x40039090) // FTM Inverting Control
1684#define FTM1_SWOCTRL (*(volatile uint32_t *)0x40039094) // FTM Software Output Control
1685#define FTM1_PWMLOAD (*(volatile uint32_t *)0x40039098) // FTM PWM Load
1686#define FTM2_SC (*(volatile uint32_t *)0x400B8000) // Status And Control
1687#define FTM2_CNT (*(volatile uint32_t *)0x400B8004) // Counter
1688#define FTM2_MOD (*(volatile uint32_t *)0x400B8008) // Modulo
1689#define FTM2_C0SC (*(volatile uint32_t *)0x400B800C) // Channel 0 Status And Control
1690#define FTM2_C0V (*(volatile uint32_t *)0x400B8010) // Channel 0 Value
1691#define FTM2_C1SC (*(volatile uint32_t *)0x400B8014) // Channel 1 Status And Control
1692#define FTM2_C1V (*(volatile uint32_t *)0x400B8018) // Channel 1 Value
1693#define FTM2_CNTIN (*(volatile uint32_t *)0x400B804C) // Counter Initial Value
1694#define FTM2_STATUS (*(volatile uint32_t *)0x400B8050) // Capture And Compare Status
1695#define FTM2_MODE (*(volatile uint32_t *)0x400B8054) // Features Mode Selection
1696#define FTM2_SYNC (*(volatile uint32_t *)0x400B8058) // Synchronization
1697#define FTM2_OUTINIT (*(volatile uint32_t *)0x400B805C) // Initial State For Channels Output
1698#define FTM2_OUTMASK (*(volatile uint32_t *)0x400B8060) // Output Mask
1699#define FTM2_COMBINE (*(volatile uint32_t *)0x400B8064) // Function For Linked Channels
1700#define FTM2_DEADTIME (*(volatile uint32_t *)0x400B8068) // Deadtime Insertion Control
1701#define FTM2_EXTTRIG (*(volatile uint32_t *)0x400B806C) // FTM External Trigger
1702#define FTM2_POL (*(volatile uint32_t *)0x400B8070) // Channels Polarity
1703#define FTM2_FMS (*(volatile uint32_t *)0x400B8074) // Fault Mode Status
1704#define FTM2_FILTER (*(volatile uint32_t *)0x400B8078) // Input Capture Filter Control
1705#define FTM2_FLTCTRL (*(volatile uint32_t *)0x400B807C) // Fault Control
1706#define FTM2_QDCTRL (*(volatile uint32_t *)0x400B8080) // Quadrature Decoder Control And Status
1707#define FTM2_CONF (*(volatile uint32_t *)0x400B8084) // Configuration
1708#define FTM2_FLTPOL (*(volatile uint32_t *)0x400B8088) // FTM Fault Input Polarity
1709#define FTM2_SYNCONF (*(volatile uint32_t *)0x400B808C) // Synchronization Configuration
1710#define FTM2_INVCTRL (*(volatile uint32_t *)0x400B8090) // FTM Inverting Control
1711#define FTM2_SWOCTRL (*(volatile uint32_t *)0x400B8094) // FTM Software Output Control
1712#define FTM2_PWMLOAD (*(volatile uint32_t *)0x400B8098) // FTM PWM Load
1713
1714// Chapter 36: Periodic Interrupt Timer (PIT)
1715#define PIT_MCR (*(volatile uint32_t *)0x40037000) // PIT Module Control Register
1716#define PIT_LDVAL0 (*(volatile uint32_t *)0x40037100) // Timer Load Value Register
1717#define PIT_CVAL0 (*(volatile uint32_t *)0x40037104) // Current Timer Value Register
1718#define PIT_TCTRL0 (*(volatile uint32_t *)0x40037108) // Timer Control Register
1719#define PIT_TFLG0 (*(volatile uint32_t *)0x4003710C) // Timer Flag Register
1720#define PIT_LDVAL1 (*(volatile uint32_t *)0x40037110) // Timer Load Value Register
1721#define PIT_CVAL1 (*(volatile uint32_t *)0x40037114) // Current Timer Value Register
1722#define PIT_TCTRL1 (*(volatile uint32_t *)0x40037118) // Timer Control Register
1723#define PIT_TFLG1 (*(volatile uint32_t *)0x4003711C) // Timer Flag Register
1724#define PIT_LDVAL2 (*(volatile uint32_t *)0x40037120) // Timer Load Value Register
1725#define PIT_CVAL2 (*(volatile uint32_t *)0x40037124) // Current Timer Value Register
1726#define PIT_TCTRL2 (*(volatile uint32_t *)0x40037128) // Timer Control Register
1727#define PIT_TFLG2 (*(volatile uint32_t *)0x4003712C) // Timer Flag Register
1728#define PIT_LDVAL3 (*(volatile uint32_t *)0x40037130) // Timer Load Value Register
1729#define PIT_CVAL3 (*(volatile uint32_t *)0x40037134) // Current Timer Value Register
1730#define PIT_TCTRL3 (*(volatile uint32_t *)0x40037138) // Timer Control Register
1731#define PIT_TFLG3 (*(volatile uint32_t *)0x4003713C) // Timer Flag Register
1732
1733// Chapter 37: Low-Power Timer (LPTMR)
1734#define LPTMR0_CSR (*(volatile uint32_t *)0x40040000) // Low Power Timer Control Status Register
1735#define LPTMR_CSR_TCF 0x80 // Compare Flag
1736#define LPTMR_CSR_TIE 0x40 // Interrupt Enable
1737#define LPTMR_CSR_TPS(n) (((n) & 3) << 4) // Pin: 0=CMP0, 1=xtal, 2=pin13
1738#define LPTMR_CSR_TPP 0x08 // Pin Polarity
1739#define LPTMR_CSR_TFC 0x04 // Free-Running Counter
1740#define LPTMR_CSR_TMS 0x02 // Mode Select, 0=timer, 1=counter
1741#define LPTMR_CSR_TEN 0x01 // Enable
1742#define LPTMR0_PSR (*(volatile uint32_t *)0x40040004) // Low Power Timer Prescale Register
1743#define LPTMR_PSR_PRESCALE(n) (((n) & 15) << 3) // Prescaler value
1744#define LPTMR_PSR_PBYP 0x04 // Prescaler bypass
1745#define LPTMR_PSR_PCS(n) (((n) & 3) << 0) // Clock: 0=MCGIRCLK, 1=LPO(1kHz), 2=ERCLK32K, 3=OSCERCLK
1746#define LPTMR0_CMR (*(volatile uint32_t *)0x40040008) // Low Power Timer Compare Register
1747#define LPTMR0_CNR (*(volatile uint32_t *)0x4004000C) // Low Power Timer Counter Register
1748
1749// Chapter 38: Carrier Modulator Transmitter (CMT)
1750#define CMT_CGH1 (*(volatile uint8_t *)0x40062000) // CMT Carrier Generator High Data Register 1
1751#define CMT_CGL1 (*(volatile uint8_t *)0x40062001) // CMT Carrier Generator Low Data Register 1
1752#define CMT_CGH2 (*(volatile uint8_t *)0x40062002) // CMT Carrier Generator High Data Register 2
1753#define CMT_CGL2 (*(volatile uint8_t *)0x40062003) // CMT Carrier Generator Low Data Register 2
1754#define CMT_OC (*(volatile uint8_t *)0x40062004) // CMT Output Control Register
1755#define CMT_MSC (*(volatile uint8_t *)0x40062005) // CMT Modulator Status and Control Register
1756#define CMT_CMD1 (*(volatile uint8_t *)0x40062006) // CMT Modulator Data Register Mark High
1757#define CMT_CMD2 (*(volatile uint8_t *)0x40062007) // CMT Modulator Data Register Mark Low
1758#define CMT_CMD3 (*(volatile uint8_t *)0x40062008) // CMT Modulator Data Register Space High
1759#define CMT_CMD4 (*(volatile uint8_t *)0x40062009) // CMT Modulator Data Register Space Low
1760#define CMT_PPS (*(volatile uint8_t *)0x4006200A) // CMT Primary Prescaler Register
1761#define CMT_DMA (*(volatile uint8_t *)0x4006200B) // CMT Direct Memory Access Register
1762
1763// Chapter 39: Real Time Clock (RTC)
1764#define RTC_TSR (*(volatile uint32_t *)0x4003D000) // RTC Time Seconds Register
1765#define RTC_TPR (*(volatile uint32_t *)0x4003D004) // RTC Time Prescaler Register
1766#define RTC_TAR (*(volatile uint32_t *)0x4003D008) // RTC Time Alarm Register
1767#define RTC_TCR (*(volatile uint32_t *)0x4003D00C) // RTC Time Compensation Register
1768#define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter
1769#define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value
1770#define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register
1771#define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register
1772#define RTC_CR (*(volatile uint32_t *)0x4003D010) // RTC Control Register
1773#define RTC_CR_SC2P ((uint32_t)0x00002000) //
1774#define RTC_CR_SC4P ((uint32_t)0x00001000) //
1775#define RTC_CR_SC8P ((uint32_t)0x00000800) //
1776#define RTC_CR_SC16P ((uint32_t)0x00000400) //
1777#define RTC_CR_CLKO ((uint32_t)0x00000200) //
1778#define RTC_CR_OSCE ((uint32_t)0x00000100) //
1779#define RTC_CR_UM ((uint32_t)0x00000008) //
1780#define RTC_CR_SUP ((uint32_t)0x00000004) //
1781#define RTC_CR_WPE ((uint32_t)0x00000002) //
1782#define RTC_CR_SWR ((uint32_t)0x00000001) //
1783#define RTC_SR (*(volatile uint32_t *)0x4003D014) // RTC Status Register
1784#define RTC_SR_TCE ((uint32_t)0x00000010) //
1785#define RTC_SR_TAF ((uint32_t)0x00000004) //
1786#define RTC_SR_TOF ((uint32_t)0x00000002) //
1787#define RTC_SR_TIF ((uint32_t)0x00000001) //
1788#define RTC_LR (*(volatile uint32_t *)0x4003D018) // RTC Lock Register
1789#define RTC_IER (*(volatile uint32_t *)0x4003D01C) // RTC Interrupt Enable Register
1790#define RTC_WAR (*(volatile uint32_t *)0x4003D800) // RTC Write Access Register
1791#define RTC_RAR (*(volatile uint32_t *)0x4003D804) // RTC Read Access Register
1792
1793// Chapter 40: Universal Serial Bus OTG Controller (USBOTG)
1794#define USB0_PERID (*(const uint8_t *)0x40072000) // Peripheral ID register
1795#define USB0_IDCOMP (*(const uint8_t *)0x40072004) // Peripheral ID Complement register
1796#define USB0_REV (*(const uint8_t *)0x40072008) // Peripheral Revision register
1797#define USB0_ADDINFO (*(volatile uint8_t *)0x4007200C) // Peripheral Additional Info register
1798#define USB0_OTGISTAT (*(volatile uint8_t *)0x40072010) // OTG Interrupt Status register
1799#define USB_OTGISTAT_IDCHG ((uint8_t)0x80) //
1800#define USB_OTGISTAT_ONEMSEC ((uint8_t)0x40) //
1801#define USB_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) //
1802#define USB_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) //
1803#define USB_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) //
1804#define USB_OTGISTAT_AVBUSCHG ((uint8_t)0x01) //
1805#define USB0_OTGICR (*(volatile uint8_t *)0x40072014) // OTG Interrupt Control Register
1806#define USB_OTGICR_IDEN ((uint8_t)0x80) //
1807#define USB_OTGICR_ONEMSECEN ((uint8_t)0x40) //
1808#define USB_OTGICR_LINESTATEEN ((uint8_t)0x20) //
1809#define USB_OTGICR_SESSVLDEN ((uint8_t)0x08) //
1810#define USB_OTGICR_BSESSEN ((uint8_t)0x04) //
1811#define USB_OTGICR_AVBUSEN ((uint8_t)0x01) //
1812#define USB0_OTGSTAT (*(volatile uint8_t *)0x40072018) // OTG Status register
1813#define USB_OTGSTAT_ID ((uint8_t)0x80) //
1814#define USB_OTGSTAT_ONEMSECEN ((uint8_t)0x40) //
1815#define USB_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) //
1816#define USB_OTGSTAT_SESS_VLD ((uint8_t)0x08) //
1817#define USB_OTGSTAT_BSESSEND ((uint8_t)0x04) //
1818#define USB_OTGSTAT_AVBUSVLD ((uint8_t)0x01) //
1819#define USB0_OTGCTL (*(volatile uint8_t *)0x4007201C) // OTG Control Register
1820#define USB_OTGCTL_DPHIGH ((uint8_t)0x80) //
1821#define USB_OTGCTL_DPLOW ((uint8_t)0x20) //
1822#define USB_OTGCTL_DMLOW ((uint8_t)0x10) //
1823#define USB_OTGCTL_OTGEN ((uint8_t)0x04) //
1824#define USB0_ISTAT (*(volatile uint8_t *)0x40072080) // Interrupt Status Register
1825#define USB_ISTAT_STALL ((uint8_t)0x80) //
1826#define USB_ISTAT_ATTACH ((uint8_t)0x40) //
1827#define USB_ISTAT_RESUME ((uint8_t)0x20) //
1828#define USB_ISTAT_SLEEP ((uint8_t)0x10) //
1829#define USB_ISTAT_TOKDNE ((uint8_t)0x08) //
1830#define USB_ISTAT_SOFTOK ((uint8_t)0x04) //
1831#define USB_ISTAT_ERROR ((uint8_t)0x02) //
1832#define USB_ISTAT_USBRST ((uint8_t)0x01) //
1833#define USB0_INTEN (*(volatile uint8_t *)0x40072084) // Interrupt Enable Register
1834#define USB_INTEN_STALLEN ((uint8_t)0x80) //
1835#define USB_INTEN_ATTACHEN ((uint8_t)0x40) //
1836#define USB_INTEN_RESUMEEN ((uint8_t)0x20) //
1837#define USB_INTEN_SLEEPEN ((uint8_t)0x10) //
1838#define USB_INTEN_TOKDNEEN ((uint8_t)0x08) //
1839#define USB_INTEN_SOFTOKEN ((uint8_t)0x04) //
1840#define USB_INTEN_ERROREN ((uint8_t)0x02) //
1841#define USB_INTEN_USBRSTEN ((uint8_t)0x01) //
1842#define USB0_ERRSTAT (*(volatile uint8_t *)0x40072088) // Error Interrupt Status Register
1843#define USB_ERRSTAT_BTSERR ((uint8_t)0x80) //
1844#define USB_ERRSTAT_DMAERR ((uint8_t)0x20) //
1845#define USB_ERRSTAT_BTOERR ((uint8_t)0x10) //
1846#define USB_ERRSTAT_DFN8 ((uint8_t)0x08) //
1847#define USB_ERRSTAT_CRC16 ((uint8_t)0x04) //
1848#define USB_ERRSTAT_CRC5EOF ((uint8_t)0x02) //
1849#define USB_ERRSTAT_PIDERR ((uint8_t)0x01) //
1850#define USB0_ERREN (*(volatile uint8_t *)0x4007208C) // Error Interrupt Enable Register
1851#define USB_ERREN_BTSERREN ((uint8_t)0x80) //
1852#define USB_ERREN_DMAERREN ((uint8_t)0x20) //
1853#define USB_ERREN_BTOERREN ((uint8_t)0x10) //
1854#define USB_ERREN_DFN8EN ((uint8_t)0x08) //
1855#define USB_ERREN_CRC16EN ((uint8_t)0x04) //
1856#define USB_ERREN_CRC5EOFEN ((uint8_t)0x02) //
1857#define USB_ERREN_PIDERREN ((uint8_t)0x01) //
1858#define USB0_STAT (*(volatile uint8_t *)0x40072090) // Status Register
1859#define USB_STAT_TX ((uint8_t)0x08) //
1860#define USB_STAT_ODD ((uint8_t)0x04) //
1861#define USB_STAT_ENDP(n) ((uint8_t)((n) >> 4)) //
1862#define USB0_CTL (*(volatile uint8_t *)0x40072094) // Control Register
1863#define USB_CTL_JSTATE ((uint8_t)0x80) //
1864#define USB_CTL_SE0 ((uint8_t)0x40) //
1865#define USB_CTL_TXSUSPENDTOKENBUSY ((uint8_t)0x20) //
1866#define USB_CTL_RESET ((uint8_t)0x10) //
1867#define USB_CTL_HOSTMODEEN ((uint8_t)0x08) //
1868#define USB_CTL_RESUME ((uint8_t)0x04) //
1869#define USB_CTL_ODDRST ((uint8_t)0x02) //
1870#define USB_CTL_USBENSOFEN ((uint8_t)0x01) //
1871#define USB0_ADDR (*(volatile uint8_t *)0x40072098) // Address Register
1872#define USB0_BDTPAGE1 (*(volatile uint8_t *)0x4007209C) // BDT Page Register 1
1873#define USB0_FRMNUML (*(volatile uint8_t *)0x400720A0) // Frame Number Register Low
1874#define USB0_FRMNUMH (*(volatile uint8_t *)0x400720A4) // Frame Number Register High
1875#define USB0_TOKEN (*(volatile uint8_t *)0x400720A8) // Token Register
1876#define USB0_SOFTHLD (*(volatile uint8_t *)0x400720AC) // SOF Threshold Register
1877#define USB0_BDTPAGE2 (*(volatile uint8_t *)0x400720B0) // BDT Page Register 2
1878#define USB0_BDTPAGE3 (*(volatile uint8_t *)0x400720B4) // BDT Page Register 3
1879#define USB0_ENDPT0 (*(volatile uint8_t *)0x400720C0) // Endpoint Control Register
1880#define USB_ENDPT_HOSTWOHUB ((uint8_t)0x80) // host only, enable low speed
1881#define USB_ENDPT_RETRYDIS ((uint8_t)0x40) // host only, set to disable NAK retry
1882#define USB_ENDPT_EPCTLDIS ((uint8_t)0x10) // 0=control, 1=bulk, interrupt, isync
1883#define USB_ENDPT_EPRXEN ((uint8_t)0x08) // enables the endpoint for RX transfers.
1884#define USB_ENDPT_EPTXEN ((uint8_t)0x04) // enables the endpoint for TX transfers.
1885#define USB_ENDPT_EPSTALL ((uint8_t)0x02) // set to stall endpoint
1886#define USB_ENDPT_EPHSHK ((uint8_t)0x01) // enable handshaking during a transaction, generally set unless Isochronous
1887#define USB0_ENDPT1 (*(volatile uint8_t *)0x400720C4) // Endpoint Control Register
1888#define USB0_ENDPT2 (*(volatile uint8_t *)0x400720C8) // Endpoint Control Register
1889#define USB0_ENDPT3 (*(volatile uint8_t *)0x400720CC) // Endpoint Control Register
1890#define USB0_ENDPT4 (*(volatile uint8_t *)0x400720D0) // Endpoint Control Register
1891#define USB0_ENDPT5 (*(volatile uint8_t *)0x400720D4) // Endpoint Control Register
1892#define USB0_ENDPT6 (*(volatile uint8_t *)0x400720D8) // Endpoint Control Register
1893#define USB0_ENDPT7 (*(volatile uint8_t *)0x400720DC) // Endpoint Control Register
1894#define USB0_ENDPT8 (*(volatile uint8_t *)0x400720E0) // Endpoint Control Register
1895#define USB0_ENDPT9 (*(volatile uint8_t *)0x400720E4) // Endpoint Control Register
1896#define USB0_ENDPT10 (*(volatile uint8_t *)0x400720E8) // Endpoint Control Register
1897#define USB0_ENDPT11 (*(volatile uint8_t *)0x400720EC) // Endpoint Control Register
1898#define USB0_ENDPT12 (*(volatile uint8_t *)0x400720F0) // Endpoint Control Register
1899#define USB0_ENDPT13 (*(volatile uint8_t *)0x400720F4) // Endpoint Control Register
1900#define USB0_ENDPT14 (*(volatile uint8_t *)0x400720F8) // Endpoint Control Register
1901#define USB0_ENDPT15 (*(volatile uint8_t *)0x400720FC) // Endpoint Control Register
1902#define USB0_USBCTRL (*(volatile uint8_t *)0x40072100) // USB Control Register
1903#define USB_USBCTRL_SUSP ((uint8_t)0x80) // Places the USB transceiver into the suspend state.
1904#define USB_USBCTRL_PDE ((uint8_t)0x40) // Enables the weak pulldowns on the USB transceiver.
1905#define USB0_OBSERVE (*(volatile uint8_t *)0x40072104) // USB OTG Observe Register
1906#define USB_OBSERVE_DPPU ((uint8_t)0x80) //
1907#define USB_OBSERVE_DPPD ((uint8_t)0x40) //
1908#define USB_OBSERVE_DMPD ((uint8_t)0x10) //
1909#define USB0_CONTROL (*(volatile uint8_t *)0x40072108) // USB OTG Control Register
1910#define USB_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
1911#define USB0_USBTRC0 (*(volatile uint8_t *)0x4007210C) // USB Transceiver Control Register 0
1912#define USB_USBTRC_USBRESET ((uint8_t)0x80) //
1913#define USB_USBTRC_USBRESMEN ((uint8_t)0x20) //
1914#define USB_USBTRC_SYNC_DET ((uint8_t)0x02) //
1915#define USB_USBTRC_USB_RESUME_INT ((uint8_t)0x01) //
1916#define USB0_USBFRMADJUST (*(volatile uint8_t *)0x40072114) // Frame Adjust Register
1917
1918// Chapter 41: USB Device Charger Detection Module (USBDCD)
1919#define USBDCD_CONTROL (*(volatile uint32_t *)0x40035000) // Control register
1920#define USBDCD_CLOCK (*(volatile uint32_t *)0x40035004) // Clock register
1921#define USBDCD_STATUS (*(volatile uint32_t *)0x40035008) // Status register
1922#define USBDCD_TIMER0 (*(volatile uint32_t *)0x40035010) // TIMER0 register
1923#define USBDCD_TIMER1 (*(volatile uint32_t *)0x40035014) // TIMER1 register
1924#define USBDCD_TIMER2 (*(volatile uint32_t *)0x40035018) // TIMER2 register
1925
1926// Chapter 43: SPI (DSPI)
1927typedef struct __attribute__((packed)) {
1928 volatile uint32_t MCR; // 0
1929 volatile uint32_t unused1;// 4
1930 volatile uint32_t TCR; // 8
1931 volatile uint32_t CTAR0; // c
1932 volatile uint32_t CTAR1; // 10
1933 volatile uint32_t CTAR2; // 14
1934 volatile uint32_t CTAR3; // 18
1935 volatile uint32_t CTAR4; // 1c
1936 volatile uint32_t CTAR5; // 20
1937 volatile uint32_t CTAR6; // 24
1938 volatile uint32_t CTAR7; // 28
1939 volatile uint32_t SR; // 2c
1940 volatile uint32_t RSER; // 30
1941 volatile uint32_t PUSHR; // 34
1942 volatile uint32_t POPR; // 38
1943 volatile uint32_t TXFR[16]; // 3c
1944 volatile uint32_t RXFR[16]; // 7c
1945} KINETISK_SPI_t;
1946#define SPI0 (*(KINETISK_SPI_t *)0x4002C000)
1947#define SPI0_MCR (*(volatile uint32_t *)0x4002C000) // DSPI Module Configuration Register
1948#define SPI_MCR_MSTR ((uint32_t)0x80000000) // Master/Slave Mode Select
1949#define SPI_MCR_CONT_SCKE ((uint32_t)0x40000000) //
1950#define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
1951#define SPI_MCR_FRZ ((uint32_t)0x08000000) //
1952#define SPI_MCR_MTFE ((uint32_t)0x04000000) //
1953#define SPI_MCR_ROOE ((uint32_t)0x01000000) //
1954#define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) //
1955#define SPI_MCR_DOZE ((uint32_t)0x00008000) //
1956#define SPI_MCR_MDIS ((uint32_t)0x00004000) //
1957#define SPI_MCR_DIS_TXF ((uint32_t)0x00002000) //
1958#define SPI_MCR_DIS_RXF ((uint32_t)0x00001000) //
1959#define SPI_MCR_CLR_TXF ((uint32_t)0x00000800) //
1960#define SPI_MCR_CLR_RXF ((uint32_t)0x00000400) //
1961#define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) //
1962#define SPI_MCR_HALT ((uint32_t)0x00000001) //
1963#define SPI0_TCR (*(volatile uint32_t *)0x4002C008) // DSPI Transfer Count Register
1964#define SPI0_CTAR0 (*(volatile uint32_t *)0x4002C00C) // DSPI Clock and Transfer Attributes Register, In Master Mode
1965#define SPI_CTAR_DBR ((uint32_t)0x80000000) // Double Baud Rate
1966#define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
1967#define SPI_CTAR_CPOL ((uint32_t)0x04000000) // Clock Polarity
1968#define SPI_CTAR_CPHA ((uint32_t)0x02000000) // Clock Phase
1969#define SPI_CTAR_LSBFE ((uint32_t)0x01000000) // LSB First
1970#define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
1971#define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
1972#define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
1973#define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
1974#define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
1975#define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
1976#define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
1977#define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
1978#define SPI0_CTAR0_SLAVE (*(volatile uint32_t *)0x4002C00C) // DSPI Clock and Transfer Attributes Register, In Slave Mode
1979#define SPI0_CTAR1 (*(volatile uint32_t *)0x4002C010) // DSPI Clock and Transfer Attributes Register, In Master Mode
1980#define SPI0_SR (*(volatile uint32_t *)0x4002C02C) // DSPI Status Register
1981#define SPI_SR_TCF ((uint32_t)0x80000000) // Transfer Complete Flag
1982#define SPI_SR_TXRXS ((uint32_t)0x40000000) // TX and RX Status
1983#define SPI_SR_EOQF ((uint32_t)0x10000000) // End of Queue Flag
1984#define SPI_SR_TFUF ((uint32_t)0x08000000) // Transmit FIFO Underflow Flag
1985#define SPI_SR_TFFF ((uint32_t)0x02000000) // Transmit FIFO Fill Flag
1986#define SPI_SR_RFOF ((uint32_t)0x00080000) // Receive FIFO Overflow Flag
1987#define SPI_SR_RFDF ((uint32_t)0x00020000) // Receive FIFO Drain Flag
1988#define SPI0_RSER (*(volatile uint32_t *)0x4002C030) // DSPI DMA/Interrupt Request Select and Enable Register
1989#define SPI_RSER_TCF_RE ((uint32_t)0x80000000) // Transmission Complete Request Enable
1990#define SPI_RSER_EOQF_RE ((uint32_t)0x10000000) // DSPI Finished Request Request Enable
1991#define SPI_RSER_TFUF_RE ((uint32_t)0x08000000) // Transmit FIFO Underflow Request Enable
1992#define SPI_RSER_TFFF_RE ((uint32_t)0x02000000) // Transmit FIFO Fill Request Enable
1993#define SPI_RSER_TFFF_DIRS ((uint32_t)0x01000000) // Transmit FIFO FIll Dma or Interrupt Request Select
1994#define SPI_RSER_RFOF_RE ((uint32_t)0x00080000) // Receive FIFO Overflow Request Enable
1995#define SPI_RSER_RFDF_RE ((uint32_t)0x00020000) // Receive FIFO Drain Request Enable
1996#define SPI_RSER_RFDF_DIRS ((uint32_t)0x00010000) // Receive FIFO Drain DMA or Interrupt Request Select
1997#define SPI0_PUSHR (*(volatile uint32_t *)0x4002C034) // DSPI PUSH TX FIFO Register In Master Mode
1998#define SPI_PUSHR_CONT ((uint32_t)0x80000000) //
1999#define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) //
2000#define SPI_PUSHR_EOQ ((uint32_t)0x08000000) //
2001#define SPI_PUSHR_CTCNT ((uint32_t)0x04000000) //
2002#define SPI_PUSHR_PCS(n) (((n) & 31) << 16) //
2003#define SPI0_PUSHR_SLAVE (*(volatile uint32_t *)0x4002C034) // DSPI PUSH TX FIFO Register In Slave Mode
2004#define SPI0_POPR (*(volatile uint32_t *)0x4002C038) // DSPI POP RX FIFO Register
2005#define SPI0_TXFR0 (*(volatile uint32_t *)0x4002C03C) // DSPI Transmit FIFO Registers
2006#define SPI0_TXFR1 (*(volatile uint32_t *)0x4002C040) // DSPI Transmit FIFO Registers
2007#define SPI0_TXFR2 (*(volatile uint32_t *)0x4002C044) // DSPI Transmit FIFO Registers
2008#define SPI0_TXFR3 (*(volatile uint32_t *)0x4002C048) // DSPI Transmit FIFO Registers
2009#define SPI0_RXFR0 (*(volatile uint32_t *)0x4002C07C) // DSPI Receive FIFO Registers
2010#define SPI0_RXFR1 (*(volatile uint32_t *)0x4002C080) // DSPI Receive FIFO Registers
2011#define SPI0_RXFR2 (*(volatile uint32_t *)0x4002C084) // DSPI Receive FIFO Registers
2012#define SPI0_RXFR3 (*(volatile uint32_t *)0x4002C088) // DSPI Receive FIFO Registers
2013
2014// Chapter 44: Inter-Integrated Circuit (I2C)
2015#define I2C0_A1 (*(volatile uint8_t *)0x40066000) // I2C Address Register 1
2016#define I2C0_F (*(volatile uint8_t *)0x40066001) // I2C Frequency Divider register
2017#define I2C0_C1 (*(volatile uint8_t *)0x40066002) // I2C Control Register 1
2018#define I2C_C1_IICEN ((uint8_t)0x80) // I2C Enable
2019#define I2C_C1_IICIE ((uint8_t)0x40) // I2C Interrupt Enable
2020#define I2C_C1_MST ((uint8_t)0x20) // Master Mode Select
2021#define I2C_C1_TX ((uint8_t)0x10) // Transmit Mode Select
2022#define I2C_C1_TXAK ((uint8_t)0x08) // Transmit Acknowledge Enable
2023#define I2C_C1_RSTA ((uint8_t)0x04) // Repeat START
2024#define I2C_C1_WUEN ((uint8_t)0x02) // Wakeup Enable
2025#define I2C_C1_DMAEN ((uint8_t)0x01) // DMA Enable
2026#define I2C0_S (*(volatile uint8_t *)0x40066003) // I2C Status register
2027#define I2C_S_TCF ((uint8_t)0x80) // Transfer Complete Flag
2028#define I2C_S_IAAS ((uint8_t)0x40) // Addressed As A Slave
2029#define I2C_S_BUSY ((uint8_t)0x20) // Bus Busy
2030#define I2C_S_ARBL ((uint8_t)0x10) // Arbitration Lost
2031#define I2C_S_RAM ((uint8_t)0x08) // Range Address Match
2032#define I2C_S_SRW ((uint8_t)0x04) // Slave Read/Write
2033#define I2C_S_IICIF ((uint8_t)0x02) // Interrupt Flag
2034#define I2C_S_RXAK ((uint8_t)0x01) // Receive Acknowledge
2035#define I2C0_D (*(volatile uint8_t *)0x40066004) // I2C Data I/O register
2036#define I2C0_C2 (*(volatile uint8_t *)0x40066005) // I2C Control Register 2
2037#define I2C_C2_GCAEN ((uint8_t)0x80) // General Call Address Enable
2038#define I2C_C2_ADEXT ((uint8_t)0x40) // Address Extension
2039#define I2C_C2_HDRS ((uint8_t)0x20) // High Drive Select
2040#define I2C_C2_SBRC ((uint8_t)0x10) // Slave Baud Rate Control
2041#define I2C_C2_RMEN ((uint8_t)0x08) // Range Address Matching Enable
2042#define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits
2043#define I2C0_FLT (*(volatile uint8_t *)0x40066006) // I2C Programmable Input Glitch Filter register
2044#define I2C0_RA (*(volatile uint8_t *)0x40066007) // I2C Range Address register
2045#define I2C0_SMB (*(volatile uint8_t *)0x40066008) // I2C SMBus Control and Status register
2046#define I2C0_A2 (*(volatile uint8_t *)0x40066009) // I2C Address Register 2
2047#define I2C0_SLTH (*(volatile uint8_t *)0x4006600A) // I2C SCL Low Timeout Register High
2048#define I2C0_SLTL (*(volatile uint8_t *)0x4006600B) // I2C SCL Low Timeout Register Low
2049
2050#define I2C1_A1 (*(volatile uint8_t *)0x40067000) // I2C Address Register 1
2051#define I2C1_F (*(volatile uint8_t *)0x40067001) // I2C Frequency Divider register
2052#define I2C1_C1 (*(volatile uint8_t *)0x40067002) // I2C Control Register 1
2053#define I2C1_S (*(volatile uint8_t *)0x40067003) // I2C Status register
2054#define I2C1_D (*(volatile uint8_t *)0x40067004) // I2C Data I/O register
2055#define I2C1_C2 (*(volatile uint8_t *)0x40067005) // I2C Control Register 2
2056#define I2C1_FLT (*(volatile uint8_t *)0x40067006) // I2C Programmable Input Glitch Filter register
2057#define I2C1_RA (*(volatile uint8_t *)0x40067007) // I2C Range Address register
2058#define I2C1_SMB (*(volatile uint8_t *)0x40067008) // I2C SMBus Control and Status register
2059#define I2C1_A2 (*(volatile uint8_t *)0x40067009) // I2C Address Register 2
2060#define I2C1_SLTH (*(volatile uint8_t *)0x4006700A) // I2C SCL Low Timeout Register High
2061#define I2C1_SLTL (*(volatile uint8_t *)0x4006700B) // I2C SCL Low Timeout Register Low
2062
2063// Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)
2064typedef struct __attribute__((packed)) {
2065 volatile uint8_t BDH;
2066 volatile uint8_t BDL;
2067 volatile uint8_t C1;
2068 volatile uint8_t C2;
2069 volatile uint8_t S1;
2070 volatile uint8_t S2;
2071 volatile uint8_t C3;
2072 volatile uint8_t D;
2073 volatile uint8_t MA1;
2074 volatile uint8_t MA2;
2075 volatile uint8_t C4;
2076 volatile uint8_t C5;
2077 volatile uint8_t ED;
2078 volatile uint8_t MODEM;
2079 volatile uint8_t IR;
2080 volatile uint8_t unused1;
2081 volatile uint8_t PFIFO;
2082 volatile uint8_t CFIFO;
2083 volatile uint8_t SFIFO;
2084 volatile uint8_t TWFIFO;
2085 volatile uint8_t TCFIFO;
2086 volatile uint8_t RWFIFO;
2087 volatile uint8_t RCFIFO;
2088 volatile uint8_t unused2;
2089 volatile uint8_t C7816;
2090 volatile uint8_t IE7816;
2091 volatile uint8_t IS7816;
2092 union { volatile uint8_t WP7816T0; volatile uint8_t WP7816T1; };
2093 volatile uint8_t WN7816;
2094 volatile uint8_t WF7816;
2095 volatile uint8_t ET7816;
2096 volatile uint8_t TL7816;
2097 volatile uint8_t unused3;
2098 volatile uint8_t C6;
2099 volatile uint8_t PCTH;
2100 volatile uint8_t PCTL;
2101 volatile uint8_t B1T;
2102 volatile uint8_t SDTH;
2103 volatile uint8_t SDTL;
2104 volatile uint8_t PRE;
2105 volatile uint8_t TPL;
2106 volatile uint8_t IE;
2107 volatile uint8_t WB;
2108 volatile uint8_t S3;
2109 volatile uint8_t S4;
2110 volatile uint8_t RPL;
2111 volatile uint8_t RPREL;
2112 volatile uint8_t CPW;
2113 volatile uint8_t RIDT;
2114 volatile uint8_t TIDT;
2115} KINETISK_UART_t;
2116#define UART0 (*(KINETISK_UART_t *)0x4006A000)
2117#define UART0_BDH (UART0.BDH) // UART Baud Rate Registers: High
2118#define UART0_BDL (UART0.BDL) // UART Baud Rate Registers: Low
2119#define UART0_C1 (UART0.C1) // UART Control Register 1
2120#define UART_C1_LOOPS 0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
2121#define UART_C1_UARTSWAI 0x40 // UART Stops in Wait Mode
2122#define UART_C1_RSRC 0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
2123#define UART_C1_M 0x10 // 9-bit or 8-bit Mode Select
2124#define UART_C1_WAKE 0x08 // Determines which condition wakes the UART
2125#define UART_C1_ILT 0x04 // Idle Line Type Select
2126#define UART_C1_PE 0x02 // Parity Enable
2127#define UART_C1_PT 0x01 // Parity Type, 0=even, 1=odd
2128#define UART0_C2 (UART0.C2) // UART Control Register 2
2129#define UART_C2_TIE 0x80 // Transmitter Interrupt or DMA Transfer Enable.
2130#define UART_C2_TCIE 0x40 // Transmission Complete Interrupt Enable
2131#define UART_C2_RIE 0x20 // Receiver Full Interrupt or DMA Transfer Enable
2132#define UART_C2_ILIE 0x10 // Idle Line Interrupt Enable
2133#define UART_C2_TE 0x08 // Transmitter Enable
2134#define UART_C2_RE 0x04 // Receiver Enable
2135#define UART_C2_RWU 0x02 // Receiver Wakeup Control
2136#define UART_C2_SBK 0x01 // Send Break
2137#define UART0_S1 (UART0.S1) // UART Status Register 1
2138#define UART_S1_TDRE 0x80 // Transmit Data Register Empty Flag
2139#define UART_S1_TC 0x40 // Transmit Complete Flag
2140#define UART_S1_RDRF 0x20 // Receive Data Register Full Flag
2141#define UART_S1_IDLE 0x10 // Idle Line Flag
2142#define UART_S1_OR 0x08 // Receiver Overrun Flag
2143#define UART_S1_NF 0x04 // Noise Flag
2144#define UART_S1_FE 0x02 // Framing Error Flag
2145#define UART_S1_PF 0x01 // Parity Error Flag
2146#define UART0_S2 (UART0.S2) // UART Status Register 2
2147#define UART0_C3 (UART0.C3) // UART Control Register 3
2148#define UART0_D (UART0.D) // UART Data Register
2149#define UART0_MA1 (UART0.MA1) // UART Match Address Registers 1
2150#define UART0_MA2 (UART0.MA2) // UART Match Address Registers 2
2151#define UART0_C4 (UART0.C4) // UART Control Register 4
2152#define UART0_C5 (UART0.C5) // UART Control Register 5
2153#define UART0_ED (UART0.ED) // UART Extended Data Register
2154#define UART0_MODEM (UART0.MODEM) // UART Modem Register
2155#define UART0_IR (UART0.IR) // UART Infrared Register
2156#define UART0_PFIFO (UART0.PFIFO) // UART FIFO Parameters
2157#define UART_PFIFO_TXFE 0x80 // Transmit FIFO Enable
2158#define UART_PFIFO_TXFIFOSIZE(n) (((n) & 7) << 4) // Transmit FIFO Size, 0=1, 1=4, 2=8, 3=16, 4=32, 5=64, 6=128
2159#define UART_PFIFO_RXFE 0x08 // Receive FIFO Enable
2160#define UART_PFIFO_RXFIFOSIZE(n) (((n) & 7) << 0) // Transmit FIFO Size, 0=1, 1=4, 2=8, 3=16, 4=32, 5=64, 6=128
2161#define UART0_CFIFO (UART0.CFIFO) // UART FIFO Control Register
2162#define UART_CFIFO_TXFLUSH 0x80 // Transmit FIFO/Buffer Flush
2163#define UART_CFIFO_RXFLUSH 0x40 // Receive FIFO/Buffer Flush
2164#define UART_CFIFO_RXOFE 0x04 // Receive FIFO Overflow Interrupt Enable
2165#define UART_CFIFO_TXOFE 0x02 // Transmit FIFO Overflow Interrupt Enable
2166#define UART_CFIFO_RXUFE 0x01 // Receive FIFO Underflow Interrupt Enable
2167#define UART0_SFIFO (UART0.SFIFO) // UART FIFO Status Register
2168#define UART_SFIFO_TXEMPT 0x80 // Transmit Buffer/FIFO Empty
2169#define UART_SFIFO_RXEMPT 0x40 // Receive Buffer/FIFO Empty
2170#define UART_SFIFO_RXOF 0x04 // Receiver Buffer Overflow Flag
2171#define UART_SFIFO_TXOF 0x02 // Transmitter Buffer Overflow Flag
2172#define UART_SFIFO_RXUF 0x01 // Receiver Buffer Underflow Flag
2173#define UART0_TWFIFO (UART0.TWFIFO) // UART FIFO Transmit Watermark
2174#define UART0_TCFIFO (UART0.TCFIFO) // UART FIFO Transmit Count
2175#define UART0_RWFIFO (UART0.RWFIFO) // UART FIFO Receive Watermark
2176#define UART0_RCFIFO (UART0.RCFIFO) // UART FIFO Receive Count
2177#define UART0_C7816 (UART0.C7816) // UART 7816 Control Register
2178#define UART_C7816_ONACK 0x10 // Generate NACK on Overflow
2179#define UART_C7816_ANACK 0x08 // Generate NACK on Error
2180#define UART_C7816_INIT 0x04 // Detect Initial Character
2181#define UART_C7816_TTYPE 0x02 // Transfer Type
2182#define UART_C7816_ISO_7816E 0x01 // ISO-7816 Functionality Enabled
2183#define UART0_IE7816 (UART0.IE7816) // UART 7816 Interrupt Enable Register
2184#define UART_IE7816_WTE 0x80 // Wait Timer Interrupt Enable
2185#define UART_IE7816_CWTE 0x40 // Character Wait Timer Interrupt Enable
2186#define UART_IE7816_BWTE 0x20 // Block Wait Timer Interrupt Enable
2187#define UART_IE7816_INITDE 0x10 // Initial Character Detected Interrupt Enable
2188#define UART_IE7816_GTVE 0x04 // Guard Timer Violated Interrupt Enable
2189#define UART_IE7816_TXTE 0x02 // Transmit Threshold Exceeded Interrupt Enable
2190#define UART_IE7816_RXTE 0x01 // Receive Threshold Exceeded Interrupt Enable
2191#define UART0_IS7816 (UART0.IS7816) // UART 7816 Interrupt Status Register
2192#define UART_IS7816_WT 0x80 // Wait Timer Interrupt
2193#define UART_IS7816_CWT 0x40 // Character Wait Timer Interrupt
2194#define UART_IS7816_BWT 0x20 // Block Wait Timer Interrupt
2195#define UART_IS7816_INITD 0x10 // Initial Character Detected Interrupt
2196#define UART_IS7816_GTV 0x04 // Guard Timer Violated Interrupt
2197#define UART_IS7816_TXT 0x02 // Transmit Threshold Exceeded Interrupt
2198#define UART_IS7816_RXT 0x01 // Receive Threshold Exceeded Interrupt
2199#define UART0_WP7816T0 (UART0.WP7816T0) // UART 7816 Wait Parameter Register
2200#define UART0_WP7816T1 (UART0.WP7816T1) // UART 7816 Wait Parameter Register
2201#define UART_WP7816T1_CWI(n) (((n) & 15) << 4) // Character Wait Time Integer (C7816[TTYPE] = 1)
2202#define UART_WP7816T1_BWI(n) (((n) & 15) << 0) // Block Wait Time Integer(C7816[TTYPE] = 1)
2203#define UART0_WN7816 (UART0.WN7816) // UART 7816 Wait N Register
2204#define UART0_WF7816 (UART0.WF7816) // UART 7816 Wait FD Register
2205#define UART0_ET7816 (UART0.ET7816) // UART 7816 Error Threshold Register
2206#define UART_ET7816_TXTHRESHOLD(n) (((n) & 15) << 4) // Transmit NACK Threshold
2207#define UART_ET7816_RXTHRESHOLD(n) (((n) & 15) << 0) // Receive NACK Threshold
2208#define UART0_TL7816 (UART0.TL7816) // UART 7816 Transmit Length Register
2209#define UART0_C6 (UART0.C6) // UART CEA709.1-B Control Register 6
2210#define UART_C6_EN709 0x80 // Enables the CEA709.1-B feature.
2211#define UART_C6_TX709 0x40 // Starts CEA709.1-B transmission.
2212#define UART_C6_CE 0x20 // Collision Enable
2213#define UART_C6_CP 0x10 // Collision Signal Polarity
2214#define UART0_PCTH (UART0.PCTH) // UART CEA709.1-B Packet Cycle Time Counter High
2215#define UART0_PCTL (UART0.PCTL) // UART CEA709.1-B Packet Cycle Time Counter Low
2216#define UART0_B1T (UART0.B1T) // UART CEA709.1-B Beta1 Timer
2217#define UART0_SDTH (UART0.SDTH) // UART CEA709.1-B Secondary Delay Timer High
2218#define UART0_SDTL (UART0.SDTL) // UART CEA709.1-B Secondary Delay Timer Low
2219#define UART0_PRE (UART0.PRE) // UART CEA709.1-B Preamble
2220#define UART0_TPL (UART0.TPL) // UART CEA709.1-B Transmit Packet Length
2221#define UART0_IE (UART0.IE) // UART CEA709.1-B Interrupt Enable Register
2222#define UART_IE_WBEIE 0x40 // WBASE Expired Interrupt Enable
2223#define UART_IE_ISDIE 0x20 // Initial Sync Detection Interrupt Enable
2224#define UART_IE_PRXIE 0x10 // Packet Received Interrupt Enable
2225#define UART_IE_PTXIE 0x08 // Packet Transmitted Interrupt Enable
2226#define UART_IE_PCTEIE 0x04 // Packet Cycle Timer Interrupt Enable
2227#define UART_IE_PSIE 0x02 // Preamble Start Interrupt Enable
2228#define UART_IE_TXFIE 0x01 // Transmission Fail Interrupt Enable
2229#define UART0_WB (UART0.WB) // UART CEA709.1-B WBASE
2230#define UART0_S3 (UART0.S3) // UART CEA709.1-B Status Register
2231#define UART_S3_PEF 0x80 // Preamble Error Flag
2232#define UART_S3_WBEF 0x40 // Wbase Expired Flag
2233#define UART_S3_ISD 0x20 // Initial Sync Detect
2234#define UART_S3_PRXF 0x10 // Packet Received Flag
2235#define UART_S3_PTXF 0x08 // Packet Transmitted Flag
2236#define UART_S3_PCTEF 0x04 // Packet Cycle Timer Expired Flag
2237#define UART_S3_PSF 0x02 // Preamble Start Flag
2238#define UART_S3_TXFF 0x01 // Transmission Fail Flag
2239#define UART0_S4 (UART0.S4) // UART CEA709.1-B Status Register
2240#define UART_S4_INITF 0x10 // Initial Synchronization Fail Flag
2241#define UART_S4_CDET(n) (((n) & 3) << 2) // Indicates collision: 0=none, 1=preamble, 2=data, 3=line code violation
2242#define UART_S4_ILCV 0x02 // Improper Line Code Violation
2243#define UART_S4_FE 0x01 // Framing Error
2244#define UART0_RPL (UART0.RPL) // UART CEA709.1-B Received Packet Length
2245#define UART0_RPREL (UART0.RPREL) // UART CEA709.1-B Received Preamble Length
2246#define UART0_CPW (UART0.CPW) // UART CEA709.1-B Collision Pulse Width
2247#define UART0_RIDT (UART0.RIDT) // UART CEA709.1-B Receive Indeterminate Time
2248#define UART0_TIDT (UART0.TIDT) // UART CEA709.1-B Transmit Indeterminate Time
2249#define UART1 (*(KINETISK_UART_t *)0x4006B000)
2250#define UART1_BDH (UART1.BDH) // UART Baud Rate Registers: High
2251#define UART1_BDL (UART1.BDL) // UART Baud Rate Registers: Low
2252#define UART1_C1 (UART1.C1) // UART Control Register 1
2253#define UART1_C2 (UART1.C2) // UART Control Register 2
2254#define UART1_S1 (UART1.S1) // UART Status Register 1
2255#define UART1_S2 (UART1.S2) // UART Status Register 2
2256#define UART1_C3 (UART1.C3) // UART Control Register 3
2257#define UART1_D (UART1.D) // UART Data Register
2258#define UART1_MA1 (UART1.MA1) // UART Match Address Registers 1
2259#define UART1_MA2 (UART1.MA2) // UART Match Address Registers 2
2260#define UART1_C4 (UART1.C4) // UART Control Register 4
2261#define UART1_C5 (UART1.C5) // UART Control Register 5
2262#define UART1_ED (UART1.ED) // UART Extended Data Register
2263#define UART1_MODEM (UART1.MODEM) // UART Modem Register
2264#define UART1_IR (UART1.IR) // UART Infrared Register
2265#define UART1_PFIFO (UART1.PFIFO) // UART FIFO Parameters
2266#define UART1_CFIFO (UART1.CFIFO) // UART FIFO Control Register
2267#define UART1_SFIFO (UART1.SFIFO) // UART FIFO Status Register
2268#define UART1_TWFIFO (UART1.TWFIFO) // UART FIFO Transmit Watermark
2269#define UART1_TCFIFO (UART1.TCFIFO) // UART FIFO Transmit Count
2270#define UART1_RWFIFO (UART1.RWFIFO) // UART FIFO Receive Watermark
2271#define UART1_RCFIFO (UART1.RCFIFO) // UART FIFO Receive Count
2272#define UART1_C7816 (UART1.C7816) // UART 7816 Control Register
2273#define UART1_IE7816 (UART1.IE7816) // UART 7816 Interrupt Enable Register
2274#define UART1_IS7816 (UART1.IS7816) // UART 7816 Interrupt Status Register
2275#define UART1_WP7816T0 (UART1.WP7816T0) // UART 7816 Wait Parameter Register
2276#define UART1_WP7816T1 (UART1.WP7816T1) // UART 7816 Wait Parameter Register
2277#define UART1_WN7816 (UART1.WN7816) // UART 7816 Wait N Register
2278#define UART1_WF7816 (UART1.WF7816) // UART 7816 Wait FD Register
2279#define UART1_ET7816 (UART1.ET7816) // UART 7816 Error Threshold Register
2280#define UART1_TL7816 (UART1.TL7816) // UART 7816 Transmit Length Register
2281#define UART1_C6 (UART1.C6) // UART CEA709.1-B Control Register 6
2282#define UART1_PCTH (UART1.PCTH) // UART CEA709.1-B Packet Cycle Time Counter High
2283#define UART1_PCTL (UART1.PCTL) // UART CEA709.1-B Packet Cycle Time Counter Low
2284#define UART1_B1T (UART1.B1T) // UART CEA709.1-B Beta1 Timer
2285#define UART1_SDTH (UART1.SDTH) // UART CEA709.1-B Secondary Delay Timer High
2286#define UART1_SDTL (UART1.SDTL) // UART CEA709.1-B Secondary Delay Timer Low
2287#define UART1_PRE (UART1.PRE) // UART CEA709.1-B Preamble
2288#define UART1_TPL (UART1.TPL) // UART CEA709.1-B Transmit Packet Length
2289#define UART1_IE (UART1.IE) // UART CEA709.1-B Interrupt Enable Register
2290#define UART1_WB (UART1.WB) // UART CEA709.1-B WBASE
2291#define UART1_S3 (UART1.S3) // UART CEA709.1-B Status Register
2292#define UART1_S4 (UART1.S4) // UART CEA709.1-B Status Register
2293#define UART1_RPL (UART1.RPL) // UART CEA709.1-B Received Packet Length
2294#define UART1_RPREL (UART1.RPREL) // UART CEA709.1-B Received Preamble Length
2295#define UART1_CPW (UART1.CPW) // UART CEA709.1-B Collision Pulse Width
2296#define UART1_RIDT (UART1.RIDT) // UART CEA709.1-B Receive Indeterminate Time
2297#define UART1_TIDT (UART1.TIDT) // UART CEA709.1-B Transmit Indeterminate Time
2298#define UART2 (*(KINETISK_UART_t *)0x4006C000)
2299#define UART2_BDH (UART2.BDH) // UART Baud Rate Registers: High
2300#define UART2_BDL (UART2.BDL) // UART Baud Rate Registers: Low
2301#define UART2_C1 (UART2.C1) // UART Control Register 1
2302#define UART2_C2 (UART2.C2) // UART Control Register 2
2303#define UART2_S1 (UART2.S1) // UART Status Register 1
2304#define UART2_S2 (UART2.S2) // UART Status Register 2
2305#define UART2_C3 (UART2.C3) // UART Control Register 3
2306#define UART2_D (UART2.D) // UART Data Register
2307#define UART2_MA1 (UART2.MA1) // UART Match Address Registers 1
2308#define UART2_MA2 (UART2.MA2) // UART Match Address Registers 2
2309#define UART2_C4 (UART2.C4) // UART Control Register 4
2310#define UART2_C5 (UART2.C5) // UART Control Register 5
2311#define UART2_ED (UART2.ED) // UART Extended Data Register
2312#define UART2_MODEM (UART2.MODEM) // UART Modem Register
2313#define UART2_IR (UART2.IR) // UART Infrared Register
2314#define UART2_PFIFO (UART2.PFIFO) // UART FIFO Parameters
2315#define UART2_CFIFO (UART2.CFIFO) // UART FIFO Control Register
2316#define UART2_SFIFO (UART2.SFIFO) // UART FIFO Status Register
2317#define UART2_TWFIFO (UART2.TWFIFO) // UART FIFO Transmit Watermark
2318#define UART2_TCFIFO (UART2.TCFIFO) // UART FIFO Transmit Count
2319#define UART2_RWFIFO (UART2.RWFIFO) // UART FIFO Receive Watermark
2320#define UART2_RCFIFO (UART2.RCFIFO) // UART FIFO Receive Count
2321#define UART2_C7816 (UART2.C7816) // UART 7816 Control Register
2322#define UART2_IE7816 (UART2.IE7816) // UART 7816 Interrupt Enable Register
2323#define UART2_IS7816 (UART2.IS7816) // UART 7816 Interrupt Status Register
2324#define UART2_WP7816T0 (UART2.WP7816T0) // UART 7816 Wait Parameter Register
2325#define UART2_WP7816T1 (UART2.WP7816T1) // UART 7816 Wait Parameter Register
2326#define UART2_WN7816 (UART2.WN7816) // UART 7816 Wait N Register
2327#define UART2_WF7816 (UART2.WF7816) // UART 7816 Wait FD Register
2328#define UART2_ET7816 (UART2.ET7816) // UART 7816 Error Threshold Register
2329#define UART2_TL7816 (UART2.TL7816) // UART 7816 Transmit Length Register
2330#define UART2_C6 (UART2.C6) // UART CEA709.1-B Control Register 6
2331#define UART2_PCTH (UART2.PCTH) // UART CEA709.1-B Packet Cycle Time Counter High
2332#define UART2_PCTL (UART2.PCTL) // UART CEA709.1-B Packet Cycle Time Counter Low
2333#define UART2_B1T (UART2.B1T) // UART CEA709.1-B Beta1 Timer
2334#define UART2_SDTH (UART2.SDTH) // UART CEA709.1-B Secondary Delay Timer High
2335#define UART2_SDTL (UART2.SDTL) // UART CEA709.1-B Secondary Delay Timer Low
2336#define UART2_PRE (UART2.PRE) // UART CEA709.1-B Preamble
2337#define UART2_TPL (UART2.TPL) // UART CEA709.1-B Transmit Packet Length
2338#define UART2_IE (UART2.IE) // UART CEA709.1-B Interrupt Enable Register
2339#define UART2_WB (UART2.WB) // UART CEA709.1-B WBASE
2340#define UART2_S3 (UART2.S3) // UART CEA709.1-B Status Register
2341#define UART2_S4 (UART2.S4) // UART CEA709.1-B Status Register
2342#define UART2_RPL (UART2.RPL) // UART CEA709.1-B Received Packet Length
2343#define UART2_RPREL (UART2.RPREL) // UART CEA709.1-B Received Preamble Length
2344#define UART2_CPW (UART2.CPW) // UART CEA709.1-B Collision Pulse Width
2345#define UART2_RIDT (UART2.RIDT) // UART CEA709.1-B Receive Indeterminate Time
2346#define UART2_TIDT (UART2.TIDT) // UART CEA709.1-B Transmit Indeterminate Time
2347
2348// Chapter 46: Synchronous Audio Interface (SAI)
2349#define I2S0_TCSR (*(volatile uint32_t *)0x4002F000) // SAI Transmit Control Register
2350#define I2S_TCSR_TE ((uint32_t)0x80000000) // Transmitter Enable
2351#define I2S_TCSR_STOPE ((uint32_t)0x40000000) // Transmitter Enable in Stop mode
2352#define I2S_TCSR_DBGE ((uint32_t)0x20000000) // Transmitter Enable in Debug mode
2353#define I2S_TCSR_BCE ((uint32_t)0x10000000) // Bit Clock Enable
2354#define I2S_TCSR_FR ((uint32_t)0x02000000) // FIFO Reset
2355#define I2S_TCSR_SR ((uint32_t)0x01000000) // Software Reset
2356#define I2S_TCSR_WSF ((uint32_t)0x00100000) // Word Start Flag
2357#define I2S_TCSR_SEF ((uint32_t)0x00080000) // Sync Error Flag
2358#define I2S_TCSR_FEF ((uint32_t)0x00040000) // FIFO Error Flag (underrun)
2359#define I2S_TCSR_FWF ((uint32_t)0x00020000) // FIFO Warning Flag (empty)
2360#define I2S_TCSR_FRF ((uint32_t)0x00010000) // FIFO Request Flag (Data Ready)
2361#define I2S_TCSR_WSIE ((uint32_t)0x00001000) // Word Start Interrupt Enable
2362#define I2S_TCSR_SEIE ((uint32_t)0x00000800) // Sync Error Interrupt Enable
2363#define I2S_TCSR_FEIE ((uint32_t)0x00000400) // FIFO Error Interrupt Enable
2364#define I2S_TCSR_FWIE ((uint32_t)0x00000200) // FIFO Warning Interrupt Enable
2365#define I2S_TCSR_FRIE ((uint32_t)0x00000100) // FIFO Request Interrupt Enable
2366#define I2S_TCSR_FWDE ((uint32_t)0x00000002) // FIFO Warning DMA Enable
2367#define I2S_TCSR_FRDE ((uint32_t)0x00000001) // FIFO Request DMA Enable
2368#define I2S0_TCR1 (*(volatile uint32_t *)0x4002F004) // SAI Transmit Configuration 1 Register
2369#define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark
2370#define I2S0_TCR2 (*(volatile uint32_t *)0x4002F008) // SAI Transmit Configuration 2 Register
2371#define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
2372#define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction
2373#define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
2374#define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
2375#define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input
2376#define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap
2377#define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
2378#define I2S0_TCR3 (*(volatile uint32_t *)0x4002F00C) // SAI Transmit Configuration 3 Register
2379#define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
2380#define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable
2381#define I2S0_TCR4 (*(volatile uint32_t *)0x4002F010) // SAI Transmit Configuration 4 Register
2382#define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction
2383#define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity
2384#define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early
2385#define I2S_TCR4_MF ((uint32_t)0x10) // MSB First
2386#define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
2387#define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
2388#define I2S0_TCR5 (*(volatile uint32_t *)0x4002F014) // SAI Transmit Configuration 5 Register
2389#define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
2390#define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
2391#define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
2392#define I2S0_TDR0 (*(volatile uint32_t *)0x4002F020) // SAI Transmit Data Register
2393#define I2S0_TDR1 (*(volatile uint32_t *)0x4002F024) // SAI Transmit Data Register
2394#define I2S0_TFR0 (*(volatile uint32_t *)0x4002F040) // SAI Transmit FIFO Register
2395#define I2S0_TFR1 (*(volatile uint32_t *)0x4002F044) // SAI Transmit FIFO Register
2396#define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
2397#define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
2398#define I2S0_TMR (*(volatile uint32_t *)0x4002F060) // SAI Transmit Mask Register
2399#define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF) //
2400#define I2S0_RCSR (*(volatile uint32_t *)0x4002F080) // SAI Receive Control Register
2401#define I2S_RCSR_RE ((uint32_t)0x80000000) // Receiver Enable
2402#define I2S_RCSR_STOPE ((uint32_t)0x40000000) // Receiver Enable in Stop mode
2403#define I2S_RCSR_DBGE ((uint32_t)0x20000000) // Receiver Enable in Debug mode
2404#define I2S_RCSR_BCE ((uint32_t)0x10000000) // Bit Clock Enable
2405#define I2S_RCSR_FR ((uint32_t)0x02000000) // FIFO Reset
2406#define I2S_RCSR_SR ((uint32_t)0x01000000) // Software Reset
2407#define I2S_RCSR_WSF ((uint32_t)0x00100000) // Word Start Flag
2408#define I2S_RCSR_SEF ((uint32_t)0x00080000) // Sync Error Flag
2409#define I2S_RCSR_FEF ((uint32_t)0x00040000) // FIFO Error Flag (underrun)
2410#define I2S_RCSR_FWF ((uint32_t)0x00020000) // FIFO Warning Flag (empty)
2411#define I2S_RCSR_FRF ((uint32_t)0x00010000) // FIFO Request Flag (Data Ready)
2412#define I2S_RCSR_WSIE ((uint32_t)0x00001000) // Word Start Interrupt Enable
2413#define I2S_RCSR_SEIE ((uint32_t)0x00000800) // Sync Error Interrupt Enable
2414#define I2S_RCSR_FEIE ((uint32_t)0x00000400) // FIFO Error Interrupt Enable
2415#define I2S_RCSR_FWIE ((uint32_t)0x00000200) // FIFO Warning Interrupt Enable
2416#define I2S_RCSR_FRIE ((uint32_t)0x00000100) // FIFO Request Interrupt Enable
2417#define I2S_RCSR_FWDE ((uint32_t)0x00000002) // FIFO Warning DMA Enable
2418#define I2S_RCSR_FRDE ((uint32_t)0x00000001) // FIFO Request DMA Enable
2419#define I2S0_RCR1 (*(volatile uint32_t *)0x4002F084) // SAI Receive Configuration 1 Register
2420#define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark
2421#define I2S0_RCR2 (*(volatile uint32_t *)0x4002F088) // SAI Receive Configuration 2 Register
2422#define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2
2423#define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction
2424#define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity
2425#define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK
2426#define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input
2427#define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap
2428#define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver
2429#define I2S0_RCR3 (*(volatile uint32_t *)0x4002F08C) // SAI Receive Configuration 3 Register
2430#define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration
2431#define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable
2432#define I2S0_RCR4 (*(volatile uint32_t *)0x4002F090) // SAI Receive Configuration 4 Register
2433#define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction
2434#define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity
2435#define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early
2436#define I2S_RCR4_MF ((uint32_t)0x10) // MSB First
2437#define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width
2438#define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size
2439#define I2S0_RCR5 (*(volatile uint32_t *)0x4002F094) // SAI Receive Configuration 5 Register
2440#define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted
2441#define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width
2442#define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width
2443#define I2S0_RDR0 (*(volatile uint32_t *)0x4002F0A0) // SAI Receive Data Register
2444#define I2S0_RDR1 (*(volatile uint32_t *)0x4002F0A4) // SAI Receive Data Register
2445#define I2S0_RFR0 (*(volatile uint32_t *)0x4002F0C0) // SAI Receive FIFO Register
2446#define I2S0_RFR1 (*(volatile uint32_t *)0x4002F0C4) // SAI Receive FIFO Register
2447#define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer
2448#define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer
2449#define I2S0_RMR (*(volatile uint32_t *)0x4002F0E0) // SAI Receive Mask Register
2450#define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF) //
2451#define I2S0_MCR (*(volatile uint32_t *)0x4002F100) // SAI MCLK Control Register
2452#define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag
2453#define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable
2454#define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select
2455#define I2S0_MDR (*(volatile uint32_t *)0x4002F104) // SAI MCLK Divide Register
2456#define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction
2457#define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide
2458
2459// Chapter 47: General-Purpose Input/Output (GPIO)
2460#define GPIOA_PDOR (*(volatile uint32_t *)0x400FF000) // Port Data Output Register
2461#define GPIOA_PSOR (*(volatile uint32_t *)0x400FF004) // Port Set Output Register
2462#define GPIOA_PCOR (*(volatile uint32_t *)0x400FF008) // Port Clear Output Register
2463#define GPIOA_PTOR (*(volatile uint32_t *)0x400FF00C) // Port Toggle Output Register
2464#define GPIOA_PDIR (*(volatile uint32_t *)0x400FF010) // Port Data Input Register
2465#define GPIOA_PDDR (*(volatile uint32_t *)0x400FF014) // Port Data Direction Register
2466#define GPIOB_PDOR (*(volatile uint32_t *)0x400FF040) // Port Data Output Register
2467#define GPIOB_PSOR (*(volatile uint32_t *)0x400FF044) // Port Set Output Register
2468#define GPIOB_PCOR (*(volatile uint32_t *)0x400FF048) // Port Clear Output Register
2469#define GPIOB_PTOR (*(volatile uint32_t *)0x400FF04C) // Port Toggle Output Register
2470#define GPIOB_PDIR (*(volatile uint32_t *)0x400FF050) // Port Data Input Register
2471#define GPIOB_PDDR (*(volatile uint32_t *)0x400FF054) // Port Data Direction Register
2472#define GPIOC_PDOR (*(volatile uint32_t *)0x400FF080) // Port Data Output Register
2473#define GPIOC_PSOR (*(volatile uint32_t *)0x400FF084) // Port Set Output Register
2474#define GPIOC_PCOR (*(volatile uint32_t *)0x400FF088) // Port Clear Output Register
2475#define GPIOC_PTOR (*(volatile uint32_t *)0x400FF08C) // Port Toggle Output Register
2476#define GPIOC_PDIR (*(volatile uint32_t *)0x400FF090) // Port Data Input Register
2477#define GPIOC_PDDR (*(volatile uint32_t *)0x400FF094) // Port Data Direction Register
2478#define GPIOD_PDOR (*(volatile uint32_t *)0x400FF0C0) // Port Data Output Register
2479#define GPIOD_PSOR (*(volatile uint32_t *)0x400FF0C4) // Port Set Output Register
2480#define GPIOD_PCOR (*(volatile uint32_t *)0x400FF0C8) // Port Clear Output Register
2481#define GPIOD_PTOR (*(volatile uint32_t *)0x400FF0CC) // Port Toggle Output Register
2482#define GPIOD_PDIR (*(volatile uint32_t *)0x400FF0D0) // Port Data Input Register
2483#define GPIOD_PDDR (*(volatile uint32_t *)0x400FF0D4) // Port Data Direction Register
2484#define GPIOE_PDOR (*(volatile uint32_t *)0x400FF100) // Port Data Output Register
2485#define GPIOE_PSOR (*(volatile uint32_t *)0x400FF104) // Port Set Output Register
2486#define GPIOE_PCOR (*(volatile uint32_t *)0x400FF108) // Port Clear Output Register
2487#define GPIOE_PTOR (*(volatile uint32_t *)0x400FF10C) // Port Toggle Output Register
2488#define GPIOE_PDIR (*(volatile uint32_t *)0x400FF110) // Port Data Input Register
2489#define GPIOE_PDDR (*(volatile uint32_t *)0x400FF114) // Port Data Direction Register
2490
2491// Chapter 48: Touch sense input (TSI)
2492#define TSI0_GENCS (*(volatile uint32_t *)0x40045000) // General Control and Status Register
2493#define TSI_GENCS_LPCLKS ((uint32_t)0x10000000) //
2494#define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
2495#define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
2496#define TSI_GENCS_PS(n) (((n) & 7) << 16) //
2497#define TSI_GENCS_EOSF ((uint32_t)0x00008000) //
2498#define TSI_GENCS_OUTRGF ((uint32_t)0x00004000) //
2499#define TSI_GENCS_EXTERF ((uint32_t)0x00002000) //
2500#define TSI_GENCS_OVRF ((uint32_t)0x00001000) //
2501#define TSI_GENCS_SCNIP ((uint32_t)0x00000200) //
2502#define TSI_GENCS_SWTS ((uint32_t)0x00000100) //
2503#define TSI_GENCS_TSIEN ((uint32_t)0x00000080) //
2504#define TSI_GENCS_TSIIE ((uint32_t)0x00000040) //
2505#define TSI_GENCS_ERIE ((uint32_t)0x00000020) //
2506#define TSI_GENCS_ESOR ((uint32_t)0x00000010) //
2507#define TSI_GENCS_STM ((uint32_t)0x00000002) //
2508#define TSI_GENCS_STPE ((uint32_t)0x00000001) //
2509#define TSI0_SCANC (*(volatile uint32_t *)0x40045004) // SCAN Control Register
2510#define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
2511#define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
2512#define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
2513#define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
2514#define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
2515#define TSI0_PEN (*(volatile uint32_t *)0x40045008) // Pin Enable Register
2516#define TSI0_WUCNTR (*(volatile uint32_t *)0x4004500C) // Wake-Up Channel Counter Register
2517#define TSI0_CNTR1 (*(volatile uint32_t *)0x40045100) // Counter Register
2518#define TSI0_CNTR3 (*(volatile uint32_t *)0x40045104) // Counter Register
2519#define TSI0_CNTR5 (*(volatile uint32_t *)0x40045108) // Counter Register
2520#define TSI0_CNTR7 (*(volatile uint32_t *)0x4004510C) // Counter Register
2521#define TSI0_CNTR9 (*(volatile uint32_t *)0x40045110) // Counter Register
2522#define TSI0_CNTR11 (*(volatile uint32_t *)0x40045114) // Counter Register
2523#define TSI0_CNTR13 (*(volatile uint32_t *)0x40045118) // Counter Register
2524#define TSI0_CNTR15 (*(volatile uint32_t *)0x4004511C) // Counter Register
2525#define TSI0_THRESHOLD (*(volatile uint32_t *)0x40045120) // Low Power Channel Threshold Register
2526
2527// Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)
2528#define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + ((n) >> 5)) = (1 << ((n) & 31)))
2529#define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + ((n) >> 5)) = (1 << ((n) & 31)))
2530#define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + ((n) >> 5)) = (1 << ((n) & 31)))
2531#define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + ((n) >> 5)) = (1 << ((n) & 31)))
2532
2533#define NVIC_ISER0 (*(volatile uint32_t *)0xE000E100)
2534#define NVIC_ISER1 (*(volatile uint32_t *)0xE000E104)
2535#define NVIC_ISER2 (*(volatile uint32_t *)0xE000E108)
2536#define NVIC_ISER3 (*(volatile uint32_t *)0xE000E10C)
2537#define NVIC_ICER0 (*(volatile uint32_t *)0xE000E180)
2538#define NVIC_ICER1 (*(volatile uint32_t *)0xE000E184)
2539#define NVIC_ICER2 (*(volatile uint32_t *)0xE000E188)
2540#define NVIC_ICER3 (*(volatile uint32_t *)0xE000E18C)
2541
2542// 0 = highest priority
2543// Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240
2544// Cortex-M0: 0,64,128,192
2545#define NVIC_SET_PRIORITY(irqnum, priority) (*((volatile uint8_t *)0xE000E400 + (irqnum)) = (uint8_t)(priority))
2546#define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum)))
2547
2548
2549
2550
2551#define __disable_irq() __asm__ volatile("CPSID i");
2552#define __enable_irq() __asm__ volatile("CPSIE i");
2553
1ad7d1dd 2554/* only mask default irqs, see NVIC_SET_PRIORITY users
2555 * note: usb code uses 112 priority */
2556#define __mask_irq() do { \
2557 int basepri_ = 128 - 16; \
2558 __asm__ volatile("msr BASEPRI, %0" :: "r"(basepri_)); \
2559} while (0)
2560#define __unmask_irq() do { \
2561 int basepri_ = 0; \
2562 __asm__ volatile("msr BASEPRI, %0" :: "r"(basepri_)); \
2563} while (0)
2564
a773ac06 2565// System Control Space (SCS), ARMv7 ref manual, B3.2, page 708
2566#define SCB_CPUID (*(const uint32_t *)0xE000ED00) // CPUID Base Register
2567#define SCB_ICSR (*(volatile uint32_t *)0xE000ED04) // Interrupt Control and State
2568#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)
2569#define SCB_VTOR (*(volatile uint32_t *)0xE000ED08) // Vector Table Offset
2570#define SCB_AIRCR (*(volatile uint32_t *)0xE000ED0C) // Application Interrupt and Reset Control
2571#define SCB_SCR (*(volatile uint32_t *)0xE000ED10) // System Control Register
2572#define SCB_CCR (*(volatile uint32_t *)0xE000ED14) // Configuration and Control
2573#define SCB_SHPR1 (*(volatile uint32_t *)0xE000ED18) // System Handler Priority Register 1
2574#define SCB_SHPR2 (*(volatile uint32_t *)0xE000ED1C) // System Handler Priority Register 2
2575#define SCB_SHPR3 (*(volatile uint32_t *)0xE000ED20) // System Handler Priority Register 3
2576#define SCB_SHCSR (*(volatile uint32_t *)0xE000ED24) // System Handler Control and State
2577#define SCB_CFSR (*(volatile uint32_t *)0xE000ED28) // Configurable Fault Status Register
2578#define SCB_HFSR (*(volatile uint32_t *)0xE000ED2C) // HardFault Status
2579#define SCB_DFSR (*(volatile uint32_t *)0xE000ED30) // Debug Fault Status
2580#define SCB_MMFAR (*(volatile uint32_t *)0xE000ED34) // MemManage Fault Address
2581
2582#define SYST_CSR (*(volatile uint32_t *)0xE000E010) // SysTick Control and Status
2583#define SYST_CSR_COUNTFLAG ((uint32_t)0x00010000)
2584#define SYST_CSR_CLKSOURCE ((uint32_t)0x00000004)
2585#define SYST_CSR_TICKINT ((uint32_t)0x00000002)
2586#define SYST_CSR_ENABLE ((uint32_t)0x00000001)
2587#define SYST_RVR (*(volatile uint32_t *)0xE000E014) // SysTick Reload Value Register
2588#define SYST_CVR (*(volatile uint32_t *)0xE000E018) // SysTick Current Value Register
2589#define SYST_CALIB (*(const uint32_t *)0xE000E01C) // SysTick Calibration Value
2590
2591
2592#define ARM_DEMCR (*(volatile uint32_t *)0xE000EDFC) // Debug Exception and Monitor Control
2593#define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks
2594#define ARM_DWT_CTRL (*(volatile uint32_t *)0xE0001000) // DWT control register
2595#define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count
2596#define ARM_DWT_CYCCNT (*(volatile uint32_t *)0xE0001004) // Cycle count register
2597
2598
2599
2600#ifdef __cplusplus
2601extern "C" {
2602#endif
2603extern int nvic_execution_priority(void);
2604
2605extern void nmi_isr(void);
2606extern void hard_fault_isr(void);
2607extern void memmanage_fault_isr(void);
2608extern void bus_fault_isr(void);
2609extern void usage_fault_isr(void);
2610extern void svcall_isr(void);
2611extern void debugmonitor_isr(void);
2612extern void pendablesrvreq_isr(void);
2613extern void systick_isr(void);
2614extern void dma_ch0_isr(void);
2615extern void dma_ch1_isr(void);
2616extern void dma_ch2_isr(void);
2617extern void dma_ch3_isr(void);
2618extern void dma_ch4_isr(void);
2619extern void dma_ch5_isr(void);
2620extern void dma_ch6_isr(void);
2621extern void dma_ch7_isr(void);
2622extern void dma_ch8_isr(void);
2623extern void dma_ch9_isr(void);
2624extern void dma_ch10_isr(void);
2625extern void dma_ch11_isr(void);
2626extern void dma_ch12_isr(void);
2627extern void dma_ch13_isr(void);
2628extern void dma_ch14_isr(void);
2629extern void dma_ch15_isr(void);
2630extern void dma_error_isr(void);
2631extern void mcm_isr(void);
2632extern void flash_cmd_isr(void);
2633extern void flash_error_isr(void);
2634extern void low_voltage_isr(void);
2635extern void wakeup_isr(void);
2636extern void watchdog_isr(void);
2637extern void i2c0_isr(void);
2638extern void i2c1_isr(void);
2639extern void i2c2_isr(void);
2640extern void spi0_isr(void);
2641extern void spi1_isr(void);
2642extern void spi2_isr(void);
2643extern void sdhc_isr(void);
2644extern void can0_message_isr(void);
2645extern void can0_bus_off_isr(void);
2646extern void can0_error_isr(void);
2647extern void can0_tx_warn_isr(void);
2648extern void can0_rx_warn_isr(void);
2649extern void can0_wakeup_isr(void);
2650extern void i2s0_tx_isr(void);
2651extern void i2s0_rx_isr(void);
2652extern void uart0_lon_isr(void);
2653extern void uart0_status_isr(void);
2654extern void uart0_error_isr(void);
2655extern void uart1_status_isr(void);
2656extern void uart1_error_isr(void);
2657extern void uart2_status_isr(void);
2658extern void uart2_error_isr(void);
2659extern void uart3_status_isr(void);
2660extern void uart3_error_isr(void);
2661extern void uart4_status_isr(void);
2662extern void uart4_error_isr(void);
2663extern void uart5_status_isr(void);
2664extern void uart5_error_isr(void);
2665extern void adc0_isr(void);
2666extern void adc1_isr(void);
2667extern void cmp0_isr(void);
2668extern void cmp1_isr(void);
2669extern void cmp2_isr(void);
2670extern void ftm0_isr(void);
2671extern void ftm1_isr(void);
2672extern void ftm2_isr(void);
2673extern void ftm3_isr(void);
2674extern void cmt_isr(void);
2675extern void rtc_alarm_isr(void);
2676extern void rtc_seconds_isr(void);
2677extern void pit0_isr(void);
2678extern void pit1_isr(void);
2679extern void pit2_isr(void);
2680extern void pit3_isr(void);
2681extern void pdb_isr(void);
2682extern void usb_isr(void);
2683extern void usb_charge_isr(void);
2684extern void dac0_isr(void);
2685extern void dac1_isr(void);
2686extern void tsi0_isr(void);
2687extern void mcg_isr(void);
2688extern void lptmr_isr(void);
2689extern void porta_isr(void);
2690extern void portb_isr(void);
2691extern void portc_isr(void);
2692extern void portd_isr(void);
2693extern void porte_isr(void);
2694extern void software_isr(void);
2695
2696extern void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);
2697extern void (* const _VectorsFlash[NVIC_NUM_INTERRUPTS+16])(void);
2698
2699#ifdef __cplusplus
2700}
2701#endif
2702
2703#undef BEGIN_ENUM
2704#undef END_ENUM
2705#endif
Teensy based tool assisted speedrun input file player for MegaDrive