5c129565 |
1 | #define EMIT(x) *tcache_ptr++ = x |
2 | |
e807ac75 |
3 | #define A_R4M (1 << 4) |
4 | #define A_R5M (1 << 5) |
5 | #define A_R6M (1 << 6) |
6 | #define A_R7M (1 << 7) |
7 | #define A_R8M (1 << 8) |
8 | #define A_R9M (1 << 9) |
9 | #define A_R10M (1 << 10) |
10 | #define A_R11M (1 << 11) |
5c129565 |
11 | #define A_R14M (1 << 14) |
12 | |
13 | #define A_COND_AL 0xe |
b9c1d012 |
14 | #define A_COND_EQ 0x0 |
bad5731d |
15 | #define A_COND_NE 0x1 |
16 | #define A_COND_MI 0x4 |
17 | #define A_COND_PL 0x5 |
5c129565 |
18 | |
19 | /* addressing mode 1 */ |
20 | #define A_AM1_LSL 0 |
21 | #define A_AM1_LSR 1 |
22 | #define A_AM1_ASR 2 |
23 | #define A_AM1_ROR 3 |
24 | |
25 | #define A_AM1_IMM(ror2,imm8) (((ror2)<<8) | (imm8) | 0x02000000) |
26 | #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm)) |
89fea1e9 |
27 | #define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm)) |
5c129565 |
28 | |
29 | /* data processing op */ |
5d817c91 |
30 | #define A_OP_AND 0x0 |
89fea1e9 |
31 | #define A_OP_EOR 0x1 |
5d817c91 |
32 | #define A_OP_SUB 0x2 |
89fea1e9 |
33 | #define A_OP_RSB 0x3 |
f48f5e3b |
34 | #define A_OP_ADD 0x4 |
b9c1d012 |
35 | #define A_OP_TST 0x8 |
5c129565 |
36 | #define A_OP_ORR 0xc |
37 | #define A_OP_MOV 0xd |
5d817c91 |
38 | #define A_OP_BIC 0xe |
5c129565 |
39 | |
40 | #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \ |
41 | EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op)) |
42 | |
89fea1e9 |
43 | #define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8)) |
44 | #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm)) |
45 | #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm)) |
5c129565 |
46 | |
5d817c91 |
47 | #define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8) |
48 | #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8) |
49 | #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8) |
50 | #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8) |
51 | #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8) |
d274c33b |
52 | #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8) |
bad5731d |
53 | #define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8) |
89fea1e9 |
54 | #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8) |
5c129565 |
55 | |
89fea1e9 |
56 | #define EOP_MOV_REG(s, rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm) |
57 | #define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm) |
58 | #define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm) |
59 | #define EOP_TST_REG( rn, shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm) |
60 | |
61 | #define EOP_MOV_REG2(s, rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm) |
62 | #define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm) |
63 | #define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm) |
5c129565 |
64 | |
5d817c91 |
65 | #define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm) |
66 | #define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm) |
67 | #define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm) |
68 | #define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm) |
69 | #define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm) |
5c129565 |
70 | |
5d817c91 |
71 | #define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm) |
72 | #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm) |
73 | #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm) |
74 | #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm) |
75 | #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm) |
76 | |
77 | #define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm) |
78 | #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm) |
79 | #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm) |
f48f5e3b |
80 | |
b9c1d012 |
81 | #define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG( rn, 0,A_AM1_LSL,rm) |
82 | |
89fea1e9 |
83 | #define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_LSL,rm) |
84 | #define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_ROR,rm) |
85 | #define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm) |
86 | #define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm) |
87 | |
f48f5e3b |
88 | /* addressing mode 2 */ |
89 | #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \ |
5c129565 |
90 | EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12)) |
91 | |
f48f5e3b |
92 | /* addressing mode 3 */ |
93 | #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) \ |
94 | EMIT(((cond)<<28) | 0x01400090 | ((u)<<23) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (((offset_8)&0xf0)<<4) | \ |
95 | ((s)<<6) | ((h)<<5) | ((offset_8)&0xf)) |
96 | |
97 | /* ldr and str */ |
98 | #define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12) |
99 | #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12) |
100 | #define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0) |
101 | #define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12) |
102 | #define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0) |
103 | |
5d817c91 |
104 | #define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8) |
105 | #define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0) |
106 | #define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8) |
107 | #define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0) |
5c129565 |
108 | |
109 | /* ldm and stm */ |
110 | #define EOP_XXM(cond,p,u,s,w,l,rn,list) \ |
111 | EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list)) |
112 | |
113 | #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list) |
114 | #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list) |
115 | |
116 | /* branches */ |
117 | #define EOP_C_BX(cond,rm) \ |
118 | EMIT(((cond)<<28) | 0x012fff10 | (rm)) |
119 | |
120 | #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm) |
121 | |
e807ac75 |
122 | #define EOP_C_B(cond,l,signed_immed_24) \ |
123 | EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24)) |
124 | |
125 | #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24) |
126 | #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24) |
127 | |
d274c33b |
128 | /* misc */ |
129 | #define EOP_C_MUL(cond,s,rd,rs,rm) \ |
130 | EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm)) |
131 | |
132 | #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm |
133 | |
bad5731d |
134 | #define EOP_C_MRS(cond,rd) \ |
89fea1e9 |
135 | EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12)) |
5c129565 |
136 | |
bad5731d |
137 | #define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd) |
138 | |
139 | |
140 | static void emit_mov_const(int cond, int d, unsigned int val) |
5c129565 |
141 | { |
142 | int need_or = 0; |
259ed0ea |
143 | if (val & 0xff000000) { |
bad5731d |
144 | EOP_C_DOP_IMM(cond, A_OP_MOV, 0, 0, d, 8/2, (val>>24)&0xff); |
5c129565 |
145 | need_or = 1; |
146 | } |
259ed0ea |
147 | if (val & 0x00ff0000) { |
bad5731d |
148 | EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff); |
259ed0ea |
149 | need_or = 1; |
150 | } |
151 | if (val & 0x0000ff00) { |
bad5731d |
152 | EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff); |
259ed0ea |
153 | need_or = 1; |
154 | } |
155 | if ((val &0x000000ff) || !need_or) |
bad5731d |
156 | EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff); |
259ed0ea |
157 | } |
158 | |
e807ac75 |
159 | /* |
259ed0ea |
160 | static void check_offset_12(unsigned int val) |
161 | { |
162 | if (!(val & ~0xfff)) return; |
163 | printf("offset_12 overflow %04x\n", val); |
164 | exit(1); |
5c129565 |
165 | } |
e807ac75 |
166 | */ |
5c129565 |
167 | |
e807ac75 |
168 | static void check_offset_24(int val) |
5c129565 |
169 | { |
e807ac75 |
170 | if (val >= (int)0xff000000 && val <= 0x00ffffff) return; |
171 | printf("offset_24 overflow %08x\n", val); |
172 | exit(1); |
5c129565 |
173 | } |
174 | |
e807ac75 |
175 | static void emit_call(void *target) |
5c129565 |
176 | { |
e807ac75 |
177 | int val = (unsigned int *)target - tcache_ptr - 2; |
178 | check_offset_24(val); |
259ed0ea |
179 | |
e807ac75 |
180 | EOP_BL(val & 0xffffff); // bl target |
181 | } |
5c129565 |
182 | |
e807ac75 |
183 | static void emit_block_prologue(void) |
184 | { |
185 | // stack regs |
186 | EOP_STMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // stmfd r13!, {r4-r11,lr} |
187 | emit_call(regfile_load); |
b9c1d012 |
188 | EOP_MOV_IMM(11, 0, 0); // mov r11, #0 |
5c129565 |
189 | } |
190 | |
e807ac75 |
191 | static void emit_block_epilogue(int icount) |
5c129565 |
192 | { |
b9c1d012 |
193 | if (icount > 0xff) { printf("large icount: %i\n", icount); icount = 0xff; } |
e807ac75 |
194 | emit_call(regfile_store); |
b9c1d012 |
195 | EOP_ADD_IMM(0,11,0,icount); // add r0, r11, #icount |
e807ac75 |
196 | EOP_LDMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // ldmfd r13!, {r4-r11,lr} |
e807ac75 |
197 | EOP_BX(14); // bx r14 |
198 | } |
259ed0ea |
199 | |
e807ac75 |
200 | static void emit_pc_dump(int pc) |
201 | { |
bad5731d |
202 | emit_mov_const(A_COND_AL, 3, pc<<16); |
e807ac75 |
203 | EOP_STR_IMM(3,7,0x400+6*4); // str r3, [r7, #(0x400+6*8)] |
5c129565 |
204 | } |
205 | |
259ed0ea |
206 | static void handle_caches() |
207 | { |
208 | #ifdef ARM |
209 | extern void flush_inval_caches(const void *start_addr, const void *end_addr); |
210 | flush_inval_caches(tcache, tcache_ptr); |
259ed0ea |
211 | #endif |
212 | } |
213 | |
5c129565 |
214 | |