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1 | #define EMIT(x) *tcache_ptr++ = x |
2 | |
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3 | #define A_R4M (1 << 4) |
4 | #define A_R5M (1 << 5) |
5 | #define A_R6M (1 << 6) |
6 | #define A_R7M (1 << 7) |
7 | #define A_R8M (1 << 8) |
8 | #define A_R9M (1 << 9) |
9 | #define A_R10M (1 << 10) |
10 | #define A_R11M (1 << 11) |
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11 | #define A_R14M (1 << 14) |
12 | |
13 | #define A_COND_AL 0xe |
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14 | #define A_COND_EQ 0x0 |
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15 | #define A_COND_NE 0x1 |
16 | #define A_COND_MI 0x4 |
17 | #define A_COND_PL 0x5 |
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18 | |
19 | /* addressing mode 1 */ |
20 | #define A_AM1_LSL 0 |
21 | #define A_AM1_LSR 1 |
22 | #define A_AM1_ASR 2 |
23 | #define A_AM1_ROR 3 |
24 | |
25 | #define A_AM1_IMM(ror2,imm8) (((ror2)<<8) | (imm8) | 0x02000000) |
26 | #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm)) |
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27 | #define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm)) |
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28 | |
29 | /* data processing op */ |
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30 | #define A_OP_AND 0x0 |
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31 | #define A_OP_EOR 0x1 |
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32 | #define A_OP_SUB 0x2 |
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33 | #define A_OP_RSB 0x3 |
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34 | #define A_OP_ADD 0x4 |
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35 | #define A_OP_TST 0x8 |
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36 | #define A_OP_CMP 0xa |
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37 | #define A_OP_ORR 0xc |
38 | #define A_OP_MOV 0xd |
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39 | #define A_OP_BIC 0xe |
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40 | |
41 | #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \ |
42 | EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op)) |
43 | |
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44 | #define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8)) |
45 | #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm)) |
46 | #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm)) |
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47 | |
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48 | #define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8) |
49 | #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8) |
50 | #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8) |
51 | #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8) |
52 | #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8) |
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53 | #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8) |
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54 | #define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8) |
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55 | #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8) |
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56 | |
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57 | #define EOP_MOV_REG(s, rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm) |
58 | #define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm) |
59 | #define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm) |
60 | #define EOP_TST_REG( rn, shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm) |
61 | |
62 | #define EOP_MOV_REG2(s, rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm) |
63 | #define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm) |
64 | #define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm) |
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65 | |
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66 | #define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm) |
67 | #define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm) |
68 | #define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm) |
69 | #define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm) |
70 | #define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm) |
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71 | |
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72 | #define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm) |
73 | #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm) |
74 | #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm) |
75 | #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm) |
76 | #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm) |
77 | |
78 | #define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm) |
79 | #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm) |
80 | #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm) |
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81 | |
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82 | #define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG( rn, 0,A_AM1_LSL,rm) |
83 | |
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84 | #define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_LSL,rm) |
85 | #define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_ROR,rm) |
86 | #define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm) |
87 | #define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm) |
88 | |
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89 | /* addressing mode 2 */ |
90 | #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \ |
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91 | EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12)) |
92 | |
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93 | /* addressing mode 3 */ |
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94 | #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \ |
95 | EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \ |
96 | ((s)<<6) | ((h)<<5) | (immed_reg)) |
97 | |
98 | #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf)) |
99 | |
100 | #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm) |
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101 | |
102 | /* ldr and str */ |
103 | #define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12) |
104 | #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12) |
105 | #define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0) |
106 | #define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12) |
107 | #define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0) |
108 | |
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109 | #define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8) |
110 | #define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0) |
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111 | #define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm) |
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112 | #define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8) |
113 | #define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0) |
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114 | #define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm) |
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115 | |
116 | /* ldm and stm */ |
117 | #define EOP_XXM(cond,p,u,s,w,l,rn,list) \ |
118 | EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list)) |
119 | |
120 | #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list) |
121 | #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list) |
122 | |
123 | /* branches */ |
124 | #define EOP_C_BX(cond,rm) \ |
125 | EMIT(((cond)<<28) | 0x012fff10 | (rm)) |
126 | |
127 | #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm) |
128 | |
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129 | #define EOP_C_B(cond,l,signed_immed_24) \ |
130 | EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24)) |
131 | |
132 | #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24) |
133 | #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24) |
134 | |
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135 | /* misc */ |
136 | #define EOP_C_MUL(cond,s,rd,rs,rm) \ |
137 | EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm)) |
138 | |
139 | #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm |
140 | |
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141 | #define EOP_C_MRS(cond,rd) \ |
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142 | EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12)) |
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143 | |
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144 | #define EOP_C_MSR_IMM(cond,ror2,imm) \ |
145 | EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f |
146 | |
147 | #define EOP_C_MSR_REG(cond,rm) \ |
148 | EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f |
149 | |
150 | #define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd) |
151 | #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm) |
152 | #define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm) |
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153 | |
154 | |
155 | static void emit_mov_const(int cond, int d, unsigned int val) |
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156 | { |
157 | int need_or = 0; |
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158 | if (val & 0xff000000) { |
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159 | EOP_C_DOP_IMM(cond, A_OP_MOV, 0, 0, d, 8/2, (val>>24)&0xff); |
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160 | need_or = 1; |
161 | } |
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162 | if (val & 0x00ff0000) { |
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163 | EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff); |
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164 | need_or = 1; |
165 | } |
166 | if (val & 0x0000ff00) { |
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167 | EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff); |
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168 | need_or = 1; |
169 | } |
170 | if ((val &0x000000ff) || !need_or) |
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171 | EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff); |
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172 | } |
173 | |
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174 | /* |
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175 | static void check_offset_12(unsigned int val) |
176 | { |
177 | if (!(val & ~0xfff)) return; |
178 | printf("offset_12 overflow %04x\n", val); |
179 | exit(1); |
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180 | } |
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181 | */ |
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182 | |
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183 | static void check_offset_24(int val) |
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184 | { |
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185 | if (val >= (int)0xff000000 && val <= 0x00ffffff) return; |
186 | printf("offset_24 overflow %08x\n", val); |
187 | exit(1); |
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188 | } |
189 | |
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190 | static void emit_call(void *target) |
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191 | { |
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192 | int val = (unsigned int *)target - tcache_ptr - 2; |
193 | check_offset_24(val); |
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194 | |
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195 | EOP_BL(val & 0xffffff); // bl target |
196 | } |
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197 | |
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198 | static void emit_block_prologue(void) |
199 | { |
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200 | // nothing |
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201 | } |
202 | |
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203 | static void emit_block_epilogue(int cycles) |
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204 | { |
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205 | if (cycles > 0xff) { printf("large cycle count: %i\n", cycles); cycles = 0xff; } |
206 | EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles |
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207 | #ifdef ARM |
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208 | emit_call(ssp_drc_next); |
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209 | #endif |
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210 | } |
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211 | |
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212 | static void emit_pc_dump(int pc) |
213 | { |
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214 | emit_mov_const(A_COND_AL, 3, pc<<16); |
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215 | EOP_STR_IMM(3,7,0x400+6*4); // str r3, [r7, #(0x400+6*8)] |
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216 | } |
217 | |
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218 | static void handle_caches() |
219 | { |
220 | #ifdef ARM |
221 | extern void flush_inval_caches(const void *start_addr, const void *end_addr); |
222 | flush_inval_caches(tcache, tcache_ptr); |
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223 | #endif |
224 | } |
225 | |
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226 | |