[picodrive.git] / Pico / cd / LC89510.c

/***********************************************************\r
 *                                                         *\r
 * This source is taken from the Gens project              *\r
 * Written by Stéphane Dallongeville                       *\r
 * Copyright (c) 2002 by Stéphane Dallongeville            *\r
 * Modified/adapted for Picodrive by notaz, 2007           *\r
 *                                                         *\r
 ***********************************************************/\r
\r
#include "../PicoInt.h"\r
\r
#define cdprintf dprintf\r
//#define cdprintf(x...)\r
\r
\r
#define CDC_DMA_SPEED 256\r
\r
\r
static void CDD_Reset(void)\r
{\r
	// Reseting CDD\r
\r
	memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
	Pico_mcd->cdd.Status = 0;\r
	Pico_mcd->cdd.Minute = 0;\r
	Pico_mcd->cdd.Seconde = 0;\r
	Pico_mcd->cdd.Frame = 0;\r
	Pico_mcd->cdd.Ext = 0;\r
\r
	// clear receive status and transfer command\r
	memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
	Pico_mcd->s68k_regs[0x38+9] = 0xF;		// Default checksum\r
}\r
\r
\r
static void CDC_Reset(void)\r
{\r
	// Reseting CDC\r
\r
	memset(Pico_mcd->cdc.Buffer, 0, (16 * 1024 * 2) + 2352);\r
\r
	CDC_Update_Header();\r
\r
	Pico_mcd->cdc.COMIN = 0;\r
	Pico_mcd->cdc.IFSTAT = 0xFF;\r
	Pico_mcd->cdc.DAC.N = 0;\r
	Pico_mcd->cdc.DBC.N = 0;\r
	Pico_mcd->cdc.HEAD.N = 0x01000000;\r
	Pico_mcd->cdc.PT.N = 0;\r
	Pico_mcd->cdc.WA.N = 2352 * 2;\r
	Pico_mcd->cdc.STAT.N = 0x00000080;\r
	Pico_mcd->cdc.SBOUT = 0;\r
	Pico_mcd->cdc.IFCTRL = 0;\r
	Pico_mcd->cdc.CTRL.N = 0;\r
\r
	Pico_mcd->cdc.Decode_Reg_Read = 0;\r
	Pico_mcd->scd.Status_CDC &= ~0x08;\r
}\r
\r
\r
void LC89510_Reset(void)\r
{\r
	CDD_Reset();\r
	CDC_Reset();\r
\r
	// clear DMA_Adr & Stop_Watch\r
	memset(Pico_mcd->s68k_regs + 0xA, 0, 4);\r
}\r
\r
\r
void Update_CDC_TRansfer(int which)\r
{\r
	unsigned int DMA_Adr, dep, length, len;\r
	unsigned short *dest;\r
	unsigned char  *src;\r
\r
	if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
	{\r
		length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
		Pico_mcd->scd.Status_CDC &= ~0x08;	// Last transfer\r
		Pico_mcd->s68k_regs[4] |=  0x80;	// End data transfer\r
		Pico_mcd->s68k_regs[4] &= ~0x40;	// no more data ready\r
		Pico_mcd->cdc.IFSTAT |= 0x08;		// No more data transfer in progress\r
\r
		if (Pico_mcd->cdc.IFCTRL & 0x40)	// DTEIEN = Data Trasnfer End Interrupt Enable ?\r
		{\r
			Pico_mcd->cdc.IFSTAT &= ~0x40;\r
\r
			if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
			{\r
				dprintf("cdc DTE irq 5");\r
				SekInterruptS68k(5);\r
			}\r
		}\r
	}\r
	else length = CDC_DMA_SPEED;\r
\r
\r
	// TODO: dst bounds checking? DAC.N alignment?\r
	src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
	DMA_Adr = (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB];\r
\r
	if (which == 7) // WORD RAM\r
	{\r
		if (Pico_mcd->s68k_regs[3] & 4)\r
		{\r
			dep = ((DMA_Adr & 0x3FFF) << 3);\r
			cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
					Pico_mcd->cdc.DAC.N, dep, length);\r
\r
			dep = ((DMA_Adr & 0x3FFF) << 4);\r
			if (!(Pico_mcd->s68k_regs[3]&1)) dep += 2;\r
			dest = (unsigned short *) (Pico_mcd->word_ram + dep);\r
\r
			for (len = length; len > 0; len--, src+=2, dest+=2)\r
				*dest = (src[0]<<8) | src[1];\r
\r
			{ // debug\r
				unsigned char *b1 = Pico_mcd->word_ram + dep;\r
				unsigned char *b2 = (unsigned char *)dest - 8;\r
				dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
					b1[0], b1[1], b1[4], b1[5], b2[0], b2[1], b2[4], b2[5]);\r
			}\r
		}\r
		else\r
		{\r
			dep = ((DMA_Adr & 0x7FFF) << 3);\r
			cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
					Pico_mcd->cdc.DAC.N, dep, length);\r
			dest = (unsigned short *) (Pico_mcd->word_ram + dep);\r
\r
			for (len = length; len > 0; len--, src+=2, dest++)\r
				*dest = (src[0]<<8) | src[1];\r
\r
			{ // debug\r
				unsigned char *b1 = Pico_mcd->word_ram + dep;\r
				unsigned char *b2 = (unsigned char *)dest - 4;\r
				dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
					b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
			}\r
		}\r
	}\r
	else if (which == 4) // PCM RAM\r
	{\r
#if 0\r
			dest = (unsigned char *) Ram_PCM;\r
			dep = ((DMA_Adr & 0x03FF) << 2) + PCM_Chip.Bank;\r
#else\r
			cdprintf("CD DMA # %04x -> PCM TODO", Pico_mcd->cdc.DAC.N);\r
#endif\r
	}\r
	else if (which == 5) // PRG RAM\r
	{\r
		dep = DMA_Adr << 3;\r
		dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
		cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
				Pico_mcd->cdc.DAC.N, dep, length);\r
\r
		for (len = length; len > 0; len--, src+=2, dest++)\r
			*dest = (src[0]<<8) | src[1];\r
\r
		{ // debug\r
			unsigned char *b1 = Pico_mcd->prg_ram + dep;\r
			unsigned char *b2 = (unsigned char *)dest - 4;\r
			dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
				b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
		}\r
	}\r
\r
	length <<= 1;\r
	Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
	if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
	else Pico_mcd->cdc.DBC.N = 0;\r
\r
	// update DMA_Adr\r
	length >>= 2;\r
	if (which != 4) length >>= 1;\r
	DMA_Adr += length;\r
	Pico_mcd->s68k_regs[0xA] = DMA_Adr >> 8;\r
	Pico_mcd->s68k_regs[0xB] = DMA_Adr;\r
}\r
\r
\r
unsigned short Read_CDC_Host(int is_sub)\r
{\r
	int addr;\r
\r
	if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
	{\r
		// Transfer data disabled\r
		cdprintf("Read_CDC_Host: Transfer data disabled");\r
		return 0;\r
	}\r
\r
	if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) ||\r
		(!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
	{\r
		// Wrong setting\r
		cdprintf("Read_CDC_Host: Wrong setting");\r
		return 0;\r
	}\r
\r
	Pico_mcd->cdc.DBC.N -= 2;\r
\r
	if (Pico_mcd->cdc.DBC.N <= 0)\r
	{\r
		Pico_mcd->cdc.DBC.N = 0;\r
		Pico_mcd->scd.Status_CDC &= ~0x08;		// Last transfer\r
		Pico_mcd->s68k_regs[4] |=  0x80;		// End data transfer\r
		Pico_mcd->s68k_regs[4] &= ~0x40;		// no more data ready\r
		Pico_mcd->cdc.IFSTAT |= 0x08;			// No more data transfer in progress\r
\r
		if (Pico_mcd->cdc.IFCTRL & 0x40)		// DTEIEN = Data Transfer End Interrupt Enable ?\r
		{\r
			Pico_mcd->cdc.IFSTAT &= ~0x40;\r
\r
			if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
				dprintf("m68k: s68k irq 5");\r
				SekInterruptS68k(5);\r
			}\r
\r
			cdprintf("CDC - DTE interrupt");\r
		}\r
	}\r
\r
	addr = Pico_mcd->cdc.DAC.N;\r
	Pico_mcd->cdc.DAC.N += 2;\r
\r
	cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
		(Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
\r
	return (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1];\r
\r
#if 0\r
	__asm\r
	{\r
		mov esi, Pico_mcd->cdc.DAC.N\r
		lea ebx, Pico_mcd->cdc.Buffer\r
//				and esi, 0x3FFF\r
		mov ax, [ebx + esi]\r
		add esi, 2\r
		rol ax, 8\r
		mov Pico_mcd->cdc.DAC.N, esi\r
		mov val, ax\r
	}\r
#endif\r
}\r
\r
\r
void CDC_Update_Header(void)\r
{\r
	if (Pico_mcd->cdc.CTRL.B.B1 & 0x01)		// Sub-Header wanted ?\r
	{\r
		Pico_mcd->cdc.HEAD.B.B0 = 0;\r
		Pico_mcd->cdc.HEAD.B.B1 = 0;\r
		Pico_mcd->cdc.HEAD.B.B2 = 0;\r
		Pico_mcd->cdc.HEAD.B.B3 = 0;\r
	}\r
	else\r
	{\r
		_msf MSF;\r
\r
		LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
\r
		Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
		Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
		Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
		Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
	}\r
}\r
\r
\r
unsigned char CDC_Read_Reg(void)\r
{\r
	unsigned char ret;\r
\r
	switch(Pico_mcd->s68k_regs[5] & 0xF)\r
	{\r
		case 0x0: // COMIN\r
			cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
\r
			Pico_mcd->s68k_regs[5] = 0x1;\r
			return Pico_mcd->cdc.COMIN;\r
\r
		case 0x1: // IFSTAT\r
			cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 1);		// Reg 1 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x2;\r
			return Pico_mcd->cdc.IFSTAT;\r
\r
		case 0x2: // DBCL\r
			cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
\r
			Pico_mcd->s68k_regs[5] = 0x3;\r
			return Pico_mcd->cdc.DBC.B.L;\r
\r
		case 0x3: // DBCH\r
			cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
\r
			Pico_mcd->s68k_regs[5] = 0x4;\r
			return Pico_mcd->cdc.DBC.B.H;\r
\r
		case 0x4: // HEAD0\r
			cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 4);		// Reg 4 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x5;\r
			return Pico_mcd->cdc.HEAD.B.B0;\r
\r
		case 0x5: // HEAD1\r
			cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 5);		// Reg 5 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x6;\r
			return Pico_mcd->cdc.HEAD.B.B1;\r
\r
		case 0x6: // HEAD2\r
			cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 6);		// Reg 6 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x7;\r
			return Pico_mcd->cdc.HEAD.B.B2;\r
\r
		case 0x7: // HEAD3\r
			cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 7);		// Reg 7 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x8;\r
			return Pico_mcd->cdc.HEAD.B.B3;\r
\r
		case 0x8: // PTL\r
			cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 8);		// Reg 8 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x9;\r
			return Pico_mcd->cdc.PT.B.L;\r
\r
		case 0x9: // PTH\r
			cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 9);		// Reg 9 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xA;\r
			return Pico_mcd->cdc.PT.B.H;\r
\r
		case 0xA: // WAL\r
			cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
\r
			Pico_mcd->s68k_regs[5] = 0xB;\r
			return Pico_mcd->cdc.WA.B.L;\r
\r
		case 0xB: // WAH\r
			cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
\r
			Pico_mcd->s68k_regs[5] = 0xC;\r
			return Pico_mcd->cdc.WA.B.H;\r
\r
		case 0xC: // STAT0\r
			cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 12);		// Reg 12 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xD;\r
			return Pico_mcd->cdc.STAT.B.B0;\r
\r
		case 0xD: // STAT1\r
			cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 13);		// Reg 13 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xE;\r
			return Pico_mcd->cdc.STAT.B.B1;\r
\r
		case 0xE: // STAT2\r
			cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 14);		// Reg 14 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xF;\r
			return Pico_mcd->cdc.STAT.B.B2;\r
\r
		case 0xF: // STAT3\r
			cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
\r
			ret = Pico_mcd->cdc.STAT.B.B3;\r
			Pico_mcd->cdc.IFSTAT |= 0x20;			// decoding interrupt flag cleared\r
			if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
			{\r
				if ((Pico_mcd->cdc.Decode_Reg_Read & 0x73F2) == 0x73F2)\r
					Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
			}\r
			return ret;\r
	}\r
\r
	return 0;\r
}\r
\r
\r
void CDC_Write_Reg(unsigned char Data)\r
{\r
	cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
\r
	switch (Pico_mcd->s68k_regs[5] & 0xF)\r
	{\r
		case 0x0: // SBOUT\r
			Pico_mcd->s68k_regs[5] = 0x1;\r
			Pico_mcd->cdc.SBOUT = Data;\r
\r
			break;\r
\r
		case 0x1: // IFCTRL\r
			Pico_mcd->s68k_regs[5] = 0x2;\r
			Pico_mcd->cdc.IFCTRL = Data;\r
\r
			if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0)		// Stop data transfer\r
			{\r
				Pico_mcd->cdc.DBC.N = 0;\r
				Pico_mcd->scd.Status_CDC &= ~0x08;\r
				Pico_mcd->cdc.IFSTAT |= 0x08;		// No more data transfer in progress\r
			}\r
			break;\r
\r
		case 0x2: // DBCL\r
			Pico_mcd->s68k_regs[5] = 0x3;\r
			Pico_mcd->cdc.DBC.B.L = Data;\r
\r
			break;\r
\r
		case 0x3: // DBCH\r
			Pico_mcd->s68k_regs[5] = 0x4;\r
			Pico_mcd->cdc.DBC.B.H = Data;\r
\r
			break;\r
\r
		case 0x4: // DACL\r
			Pico_mcd->s68k_regs[5] = 0x5;\r
			Pico_mcd->cdc.DAC.B.L = Data;\r
\r
			break;\r
\r
		case 0x5: // DACH\r
			Pico_mcd->s68k_regs[5] = 0x6;\r
			Pico_mcd->cdc.DAC.B.H = Data;\r
\r
			break;\r
\r
		case 0x6: // DTTRG\r
			if (Pico_mcd->cdc.IFCTRL & 0x02)		// Data transfer enable ?\r
			{\r
				Pico_mcd->cdc.IFSTAT &= ~0x08;		// Data transfer in progress\r
				Pico_mcd->scd.Status_CDC |= 0x08;	// Data transfer in progress\r
				Pico_mcd->s68k_regs[4] &= 0x7F;		// A data transfer start\r
\r
				cdprintf("************** Starting Data Transfer ***********");\r
				cdprintf("RS0 = %.4X  DAC = %.4X  DBC = %.4X  DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
					Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB]);\r
			}\r
			break;\r
\r
		case 0x7: // DTACK\r
			Pico_mcd->cdc.IFSTAT |= 0x40;			// end data transfer interrupt flag cleared\r
			break;\r
\r
		case 0x8: // WAL\r
			Pico_mcd->s68k_regs[5] = 0x9;\r
			Pico_mcd->cdc.WA.B.L = Data;\r
\r
			break;\r
\r
		case 0x9: // WAH\r
			Pico_mcd->s68k_regs[5] = 0xA;\r
			Pico_mcd->cdc.WA.B.H = Data;\r
\r
			break;\r
\r
		case 0xA: // CTRL0\r
			Pico_mcd->s68k_regs[5] = 0xB;\r
			Pico_mcd->cdc.CTRL.B.B0 = Data;\r
\r
			break;\r
\r
		case 0xB: // CTRL1\r
			Pico_mcd->s68k_regs[5] = 0xC;\r
			Pico_mcd->cdc.CTRL.B.B1 = Data;\r
\r
			break;\r
\r
		case 0xC: // PTL\r
			Pico_mcd->s68k_regs[5] = 0xD;\r
			Pico_mcd->cdc.PT.B.L = Data;\r
\r
			break;\r
\r
		case 0xD: // PTH\r
			Pico_mcd->s68k_regs[5] = 0xE;\r
			Pico_mcd->cdc.PT.B.H = Data;\r
\r
			break;\r
\r
		case 0xE: // CTRL2\r
			Pico_mcd->cdc.CTRL.B.B2 = Data;\r
			break;\r
\r
		case 0xF: // RESET\r
			CDC_Reset();\r
			break;\r
	}\r
}\r
\r
\r
static int bswapwrite(int a, unsigned short d)\r
{\r
	*(unsigned short *)(Pico_mcd->s68k_regs + a) = (d>>8)|(d<<8);\r
	return d + (d >> 8);\r
}\r
\r
void CDD_Export_Status(void)\r
{\r
	unsigned int csum;\r
\r
	csum  = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
	csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
	csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
	csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
	Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
	csum += Pico_mcd->cdd.Ext;\r
	Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
\r
	Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
\r
	if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
	{\r
		dprintf("cdd export irq 4");\r
		SekInterruptS68k(4);\r
	}\r
\r
//	cdprintf("CDD exported status\n");\r
	cdprintf("out:  Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X  Checksum=%.4X",\r
		(Pico_mcd->s68k_regs[0x38+0] << 8) | Pico_mcd->s68k_regs[0x38+1],\r
		(Pico_mcd->s68k_regs[0x38+2] << 8) | Pico_mcd->s68k_regs[0x38+3],\r
		(Pico_mcd->s68k_regs[0x38+4] << 8) | Pico_mcd->s68k_regs[0x38+5],\r
		(Pico_mcd->s68k_regs[0x38+6] << 8) | Pico_mcd->s68k_regs[0x38+7],\r
		(Pico_mcd->s68k_regs[0x38+8] << 8) | Pico_mcd->s68k_regs[0x38+9]);\r
}\r
\r
\r
void CDD_Import_Command(void)\r
{\r
//	cdprintf("CDD importing command\n");\r
	cdprintf("in:  Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X  Checksum=%.4X",\r
		(Pico_mcd->s68k_regs[0x38+10+0] << 8) | Pico_mcd->s68k_regs[0x38+10+1],\r
		(Pico_mcd->s68k_regs[0x38+10+2] << 8) | Pico_mcd->s68k_regs[0x38+10+3],\r
		(Pico_mcd->s68k_regs[0x38+10+4] << 8) | Pico_mcd->s68k_regs[0x38+10+5],\r
		(Pico_mcd->s68k_regs[0x38+10+6] << 8) | Pico_mcd->s68k_regs[0x38+10+7],\r
		(Pico_mcd->s68k_regs[0x38+10+8] << 8) | Pico_mcd->s68k_regs[0x38+10+9]);\r
\r
	switch (Pico_mcd->s68k_regs[0x38+10+0])\r
	{\r
		case 0x0:	// STATUS (?)\r
			Get_Status_CDD_c0();\r
			break;\r
\r
		case 0x1:	// STOP ALL (?)\r
			Stop_CDD_c1();\r
			break;\r
\r
		case 0x2:	// GET TOC INFORMATIONS\r
			switch(Pico_mcd->s68k_regs[0x38+10+3])\r
			{\r
				case 0x0:	// get current position (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
					Get_Pos_CDD_c20();\r
					break;\r
\r
				case 0x1:	// get elapsed time of current track played/scanned (relative MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 1;\r
					Get_Track_Pos_CDD_c21();\r
					break;\r
\r
				case 0x2:	// get current track in RS2-RS3\r
					Pico_mcd->cdd.Status =  (Pico_mcd->cdd.Status & 0xFF00) | 2;\r
					Get_Current_Track_CDD_c22();\r
					break;\r
\r
				case 0x3:	// get total length (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 3;\r
					Get_Total_Lenght_CDD_c23();\r
					break;\r
\r
				case 0x4:	// first & last track number\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 4;\r
					Get_First_Last_Track_CDD_c24();\r
					break;\r
\r
				case 0x5:	// get track addresse (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 5;\r
					Get_Track_Adr_CDD_c25();\r
					break;\r
\r
				default :	// invalid, then we return status\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 0xF;\r
					Get_Status_CDD_c0();\r
					break;\r
			}\r
			break;\r
\r
		case 0x3:	// READ\r
			Play_CDD_c3();\r
			break;\r
\r
		case 0x4:	// SEEK\r
			Seek_CDD_c4();\r
			break;\r
\r
		case 0x6:	// PAUSE/STOP\r
			Pause_CDD_c6();\r
			break;\r
\r
		case 0x7:	// RESUME\r
			Resume_CDD_c7();\r
			break;\r
\r
		case 0x8:	// FAST FOWARD\r
			Fast_Foward_CDD_c8();\r
			break;\r
\r
		case 0x9:	// FAST REWIND\r
			Fast_Rewind_CDD_c9();\r
			break;\r
\r
		case 0xA:	// RECOVER INITIAL STATE (?)\r
			CDD_cA();\r
			break;\r
\r
		case 0xC:	// CLOSE TRAY\r
			Close_Tray_CDD_cC();\r
			break;\r
\r
		case 0xD:	// OPEN TRAY\r
			Open_Tray_CDD_cD();\r
			break;\r
\r
		default:	// UNKNOWN\r
			CDD_Def();\r
			break;\r
	}\r
}\r
\r
Commit	Line	Data
bf098bc5	1	/***********************************************************\r
	2	* *\r
	3	* This source is taken from the Gens project *\r
	4	* Written by Stéphane Dallongeville *\r
	5	* Copyright (c) 2002 by Stéphane Dallongeville *\r
	6	* Modified/adapted for Picodrive by notaz, 2007 *\r
	7	* *\r
	8	***********************************************************/\r
cc68a136	9	\r
	10	#include "../PicoInt.h"\r
	11	\r
c459aefd	12	#define cdprintf dprintf\r
cc68a136	13	//#define cdprintf(x...)\r
	14	\r
	15	\r
	16	#define CDC_DMA_SPEED 256\r
	17	\r
cc68a136	18	\r
	19	static void CDD_Reset(void)\r
	20	{\r
	21	// Reseting CDD\r
	22	\r
	23	memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
	24	Pico_mcd->cdd.Status = 0;\r
	25	Pico_mcd->cdd.Minute = 0;\r
	26	Pico_mcd->cdd.Seconde = 0;\r
	27	Pico_mcd->cdd.Frame = 0;\r
	28	Pico_mcd->cdd.Ext = 0;\r
	29	\r
	30	// clear receive status and transfer command\r
	31	memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
	32	Pico_mcd->s68k_regs[0x38+9] = 0xF; // Default checksum\r
	33	}\r
	34	\r
	35	\r
	36	static void CDC_Reset(void)\r
	37	{\r
	38	// Reseting CDC\r
	39	\r
	40	memset(Pico_mcd->cdc.Buffer, 0, (16 * 1024 * 2) + 2352);\r
	41	\r
	42	CDC_Update_Header();\r
	43	\r
	44	Pico_mcd->cdc.COMIN = 0;\r
	45	Pico_mcd->cdc.IFSTAT = 0xFF;\r
	46	Pico_mcd->cdc.DAC.N = 0;\r
	47	Pico_mcd->cdc.DBC.N = 0;\r
	48	Pico_mcd->cdc.HEAD.N = 0x01000000;\r
	49	Pico_mcd->cdc.PT.N = 0;\r
	50	Pico_mcd->cdc.WA.N = 2352 * 2;\r
	51	Pico_mcd->cdc.STAT.N = 0x00000080;\r
	52	Pico_mcd->cdc.SBOUT = 0;\r
	53	Pico_mcd->cdc.IFCTRL = 0;\r
	54	Pico_mcd->cdc.CTRL.N = 0;\r
	55	\r
75736070	56	Pico_mcd->cdc.Decode_Reg_Read = 0;\r
c459aefd	57	Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136	58	}\r
	59	\r
	60	\r
	61	void LC89510_Reset(void)\r
	62	{\r
	63	CDD_Reset();\r
	64	CDC_Reset();\r
	65	\r
cb4a513a	66	// clear DMA_Adr & Stop_Watch\r
cb4a513a	67	memset(Pico_mcd->s68k_regs + 0xA, 0, 4);\r
cc68a136	68	}\r
cc68a136	69	\r
cc68a136	70	\r
bf098bc5	71	void Update_CDC_TRansfer(int which)\r
bf098bc5	72	{\r
cb4a513a	73	unsigned int DMA_Adr, dep, length, len;\r
bf098bc5	74	unsigned short *dest;\r
bf098bc5	75	unsigned char *src;\r
cc68a136	76	\r
	77	if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
	78	{\r
bf098bc5	79	length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
c459aefd	80	Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
bf098bc5	81	Pico_mcd->s68k_regs[4] \|= 0x80; // End data transfer\r
	82	Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
	83	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
cc68a136	84	\r
bf098bc5	85	if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Trasnfer End Interrupt Enable ?\r
cc68a136	86	{\r
	87	Pico_mcd->cdc.IFSTAT &= ~0x40;\r
	88	\r
bf098bc5	89	if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
	90	{\r
	91	dprintf("cdc DTE irq 5");\r
	92	SekInterruptS68k(5);\r
	93	}\r
cc68a136	94	}\r
cc68a136	95	}\r
bf098bc5	96	else length = CDC_DMA_SPEED;\r
bf098bc5	97	\r
cc68a136	98	\r
bf098bc5	99	// TODO: dst bounds checking? DAC.N alignment?\r
bf098bc5	100	src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
cb4a513a	101	DMA_Adr = (Pico_mcd->s68k_regs[0xA]<<8) \| Pico_mcd->s68k_regs[0xB];\r
cc68a136	102	\r
bf098bc5	103	if (which == 7) // WORD RAM\r
cc68a136	104	{\r
bf098bc5	105	if (Pico_mcd->s68k_regs[3] & 4)\r
cc68a136	106	{\r
cb4a513a	107	dep = ((DMA_Adr & 0x3FFF) << 3);\r
bf098bc5	108	cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
	109	Pico_mcd->cdc.DAC.N, dep, length);\r
	110	\r
cb4a513a	111	dep = ((DMA_Adr & 0x3FFF) << 4);\r
bf098bc5	112	if (!(Pico_mcd->s68k_regs[3]&1)) dep += 2;\r
	113	dest = (unsigned short *) (Pico_mcd->word_ram + dep);\r
	114	\r
	115	for (len = length; len > 0; len--, src+=2, dest+=2)\r
	116	*dest = (src[0]<<8) \| src[1];\r
1cd356a3	117	\r
	118	{ // debug\r
	119	unsigned char *b1 = Pico_mcd->word_ram + dep;\r
	120	unsigned char b2 = (unsigned char )dest - 8;\r
	121	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
	122	b1[0], b1[1], b1[4], b1[5], b2[0], b2[1], b2[4], b2[5]);\r
	123	}\r
cc68a136	124	}\r
bf098bc5	125	else\r
bf098bc5	126	{\r
cb4a513a	127	dep = ((DMA_Adr & 0x7FFF) << 3);\r
bf098bc5	128	cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
	129	Pico_mcd->cdc.DAC.N, dep, length);\r
	130	dest = (unsigned short *) (Pico_mcd->word_ram + dep);\r
cc68a136	131	\r
bf098bc5	132	for (len = length; len > 0; len--, src+=2, dest++)\r
bf098bc5	133	*dest = (src[0]<<8) \| src[1];\r
1cd356a3	134	\r
	135	{ // debug\r
	136	unsigned char *b1 = Pico_mcd->word_ram + dep;\r
	137	unsigned char b2 = (unsigned char )dest - 4;\r
	138	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
	139	b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
	140	}\r
bf098bc5	141	}\r
cc68a136	142	}\r
bf098bc5	143	else if (which == 4) // PCM RAM\r
cc68a136	144	{\r
bf098bc5	145	#if 0\r
bf098bc5	146	dest = (unsigned char *) Ram_PCM;\r
cb4a513a	147	dep = ((DMA_Adr & 0x03FF) << 2) + PCM_Chip.Bank;\r
bf098bc5	148	#else\r
1cd356a3	149	cdprintf("CD DMA # %04x -> PCM TODO", Pico_mcd->cdc.DAC.N);\r
bf098bc5	150	#endif\r
	151	}\r
	152	else if (which == 5) // PRG RAM\r
	153	{\r
cb4a513a	154	dep = DMA_Adr << 3;\r
bf098bc5	155	dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
	156	cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
	157	Pico_mcd->cdc.DAC.N, dep, length);\r
cc68a136	158	\r
bf098bc5	159	for (len = length; len > 0; len--, src+=2, dest++)\r
bf098bc5	160	*dest = (src[0]<<8) \| src[1];\r
1cd356a3	161	\r
	162	{ // debug\r
	163	unsigned char *b1 = Pico_mcd->prg_ram + dep;\r
	164	unsigned char b2 = (unsigned char )dest - 4;\r
	165	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
	166	b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
	167	}\r
cc68a136	168	}\r
cc68a136	169	\r
bf098bc5	170	length <<= 1;\r
bf098bc5	171	Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
c459aefd	172	if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
cc68a136	173	else Pico_mcd->cdc.DBC.N = 0;\r
1cd356a3	174	\r
	175	// update DMA_Adr\r
	176	length >>= 2;\r
	177	if (which != 4) length >>= 1;\r
	178	DMA_Adr += length;\r
	179	Pico_mcd->s68k_regs[0xA] = DMA_Adr >> 8;\r
	180	Pico_mcd->s68k_regs[0xB] = DMA_Adr;\r
cc68a136	181	}\r
cc68a136	182	\r
	183	\r
	184	unsigned short Read_CDC_Host(int is_sub)\r
	185	{\r
	186	int addr;\r
	187	\r
c459aefd	188	if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
cc68a136	189	{\r
cc68a136	190	// Transfer data disabled\r
c459aefd	191	cdprintf("Read_CDC_Host: Transfer data disabled");\r
cc68a136	192	return 0;\r
	193	}\r
	194	\r
	195	if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) \|\|\r
	196	(!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
	197	{\r
	198	// Wrong setting\r
c459aefd	199	cdprintf("Read_CDC_Host: Wrong setting");\r
cc68a136	200	return 0;\r
	201	}\r
	202	\r
	203	Pico_mcd->cdc.DBC.N -= 2;\r
	204	\r
	205	if (Pico_mcd->cdc.DBC.N <= 0)\r
	206	{\r
	207	Pico_mcd->cdc.DBC.N = 0;\r
c459aefd	208	Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
cc68a136	209	Pico_mcd->s68k_regs[4] \|= 0x80; // End data transfer\r
	210	Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
	211	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
	212	\r
	213	if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Transfer End Interrupt Enable ?\r
	214	{\r
	215	Pico_mcd->cdc.IFSTAT &= ~0x40;\r
	216	\r
	217	if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
	218	dprintf("m68k: s68k irq 5");\r
	219	SekInterruptS68k(5);\r
	220	}\r
	221	\r
c459aefd	222	cdprintf("CDC - DTE interrupt");\r
cc68a136	223	}\r
	224	}\r
	225	\r
	226	addr = Pico_mcd->cdc.DAC.N;\r
	227	Pico_mcd->cdc.DAC.N += 2;\r
c459aefd	228	\r
	229	cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
	230	(Pico_mcd->cdc.Buffer[addr]<<8) \| Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
	231	\r
cc68a136	232	return (Pico_mcd->cdc.Buffer[addr]<<8) \| Pico_mcd->cdc.Buffer[addr+1];\r
	233	\r
	234	#if 0\r
	235	__asm\r
	236	{\r
	237	mov esi, Pico_mcd->cdc.DAC.N\r
	238	lea ebx, Pico_mcd->cdc.Buffer\r
	239	// and esi, 0x3FFF\r
	240	mov ax, [ebx + esi]\r
	241	add esi, 2\r
	242	rol ax, 8\r
	243	mov Pico_mcd->cdc.DAC.N, esi\r
	244	mov val, ax\r
	245	}\r
	246	#endif\r
	247	}\r
	248	\r
	249	\r
	250	void CDC_Update_Header(void)\r
	251	{\r
	252	if (Pico_mcd->cdc.CTRL.B.B1 & 0x01) // Sub-Header wanted ?\r
	253	{\r
	254	Pico_mcd->cdc.HEAD.B.B0 = 0;\r
	255	Pico_mcd->cdc.HEAD.B.B1 = 0;\r
	256	Pico_mcd->cdc.HEAD.B.B2 = 0;\r
	257	Pico_mcd->cdc.HEAD.B.B3 = 0;\r
	258	}\r
	259	else\r
	260	{\r
	261	_msf MSF;\r
	262	\r
	263	LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
	264	\r
	265	Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
	266	Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
	267	Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
	268	Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
	269	}\r
	270	}\r
	271	\r
	272	\r
	273	unsigned char CDC_Read_Reg(void)\r
	274	{\r
	275	unsigned char ret;\r
	276	\r
cc68a136	277	switch(Pico_mcd->s68k_regs[5] & 0xF)\r
	278	{\r
	279	case 0x0: // COMIN\r
c459aefd	280	cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
cc68a136	281	\r
	282	Pico_mcd->s68k_regs[5] = 0x1;\r
	283	return Pico_mcd->cdc.COMIN;\r
	284	\r
	285	case 0x1: // IFSTAT\r
c459aefd	286	cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
cc68a136	287	\r
75736070	288	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 1); // Reg 1 (decoding)\r
cc68a136	289	Pico_mcd->s68k_regs[5] = 0x2;\r
	290	return Pico_mcd->cdc.IFSTAT;\r
	291	\r
	292	case 0x2: // DBCL\r
c459aefd	293	cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
cc68a136	294	\r
	295	Pico_mcd->s68k_regs[5] = 0x3;\r
	296	return Pico_mcd->cdc.DBC.B.L;\r
	297	\r
	298	case 0x3: // DBCH\r
c459aefd	299	cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
cc68a136	300	\r
	301	Pico_mcd->s68k_regs[5] = 0x4;\r
	302	return Pico_mcd->cdc.DBC.B.H;\r
	303	\r
	304	case 0x4: // HEAD0\r
c459aefd	305	cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
cc68a136	306	\r
75736070	307	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 4); // Reg 4 (decoding)\r
cc68a136	308	Pico_mcd->s68k_regs[5] = 0x5;\r
	309	return Pico_mcd->cdc.HEAD.B.B0;\r
	310	\r
	311	case 0x5: // HEAD1\r
c459aefd	312	cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
cc68a136	313	\r
75736070	314	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 5); // Reg 5 (decoding)\r
cc68a136	315	Pico_mcd->s68k_regs[5] = 0x6;\r
	316	return Pico_mcd->cdc.HEAD.B.B1;\r
	317	\r
	318	case 0x6: // HEAD2\r
c459aefd	319	cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
cc68a136	320	\r
75736070	321	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 6); // Reg 6 (decoding)\r
cc68a136	322	Pico_mcd->s68k_regs[5] = 0x7;\r
	323	return Pico_mcd->cdc.HEAD.B.B2;\r
	324	\r
	325	case 0x7: // HEAD3\r
c459aefd	326	cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
cc68a136	327	\r
75736070	328	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 7); // Reg 7 (decoding)\r
cc68a136	329	Pico_mcd->s68k_regs[5] = 0x8;\r
	330	return Pico_mcd->cdc.HEAD.B.B3;\r
	331	\r
	332	case 0x8: // PTL\r
c459aefd	333	cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
cc68a136	334	\r
75736070	335	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 8); // Reg 8 (decoding)\r
cc68a136	336	Pico_mcd->s68k_regs[5] = 0x9;\r
	337	return Pico_mcd->cdc.PT.B.L;\r
	338	\r
	339	case 0x9: // PTH\r
c459aefd	340	cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
cc68a136	341	\r
75736070	342	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 9); // Reg 9 (decoding)\r
cc68a136	343	Pico_mcd->s68k_regs[5] = 0xA;\r
	344	return Pico_mcd->cdc.PT.B.H;\r
	345	\r
	346	case 0xA: // WAL\r
c459aefd	347	cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
cc68a136	348	\r
	349	Pico_mcd->s68k_regs[5] = 0xB;\r
	350	return Pico_mcd->cdc.WA.B.L;\r
	351	\r
	352	case 0xB: // WAH\r
c459aefd	353	cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
cc68a136	354	\r
	355	Pico_mcd->s68k_regs[5] = 0xC;\r
	356	return Pico_mcd->cdc.WA.B.H;\r
	357	\r
	358	case 0xC: // STAT0\r
c459aefd	359	cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
cc68a136	360	\r
75736070	361	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 12); // Reg 12 (decoding)\r
cc68a136	362	Pico_mcd->s68k_regs[5] = 0xD;\r
	363	return Pico_mcd->cdc.STAT.B.B0;\r
	364	\r
	365	case 0xD: // STAT1\r
c459aefd	366	cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
cc68a136	367	\r
75736070	368	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 13); // Reg 13 (decoding)\r
cc68a136	369	Pico_mcd->s68k_regs[5] = 0xE;\r
	370	return Pico_mcd->cdc.STAT.B.B1;\r
	371	\r
	372	case 0xE: // STAT2\r
c459aefd	373	cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
cc68a136	374	\r
75736070	375	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 14); // Reg 14 (decoding)\r
cc68a136	376	Pico_mcd->s68k_regs[5] = 0xF;\r
	377	return Pico_mcd->cdc.STAT.B.B2;\r
	378	\r
	379	case 0xF: // STAT3\r
c459aefd	380	cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
cc68a136	381	\r
	382	ret = Pico_mcd->cdc.STAT.B.B3;\r
	383	Pico_mcd->cdc.IFSTAT \|= 0x20; // decoding interrupt flag cleared\r
	384	if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
	385	{\r
75736070	386	if ((Pico_mcd->cdc.Decode_Reg_Read & 0x73F2) == 0x73F2)\r
cc68a136	387	Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
	388	}\r
	389	return ret;\r
	390	}\r
	391	\r
	392	return 0;\r
	393	}\r
	394	\r
	395	\r
	396	void CDC_Write_Reg(unsigned char Data)\r
	397	{\r
c459aefd	398	cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
cc68a136	399	\r
	400	switch (Pico_mcd->s68k_regs[5] & 0xF)\r
	401	{\r
	402	case 0x0: // SBOUT\r
	403	Pico_mcd->s68k_regs[5] = 0x1;\r
	404	Pico_mcd->cdc.SBOUT = Data;\r
	405	\r
	406	break;\r
	407	\r
	408	case 0x1: // IFCTRL\r
	409	Pico_mcd->s68k_regs[5] = 0x2;\r
	410	Pico_mcd->cdc.IFCTRL = Data;\r
	411	\r
	412	if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0) // Stop data transfer\r
	413	{\r
	414	Pico_mcd->cdc.DBC.N = 0;\r
c459aefd	415	Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136	416	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
	417	}\r
	418	break;\r
	419	\r
	420	case 0x2: // DBCL\r
	421	Pico_mcd->s68k_regs[5] = 0x3;\r
	422	Pico_mcd->cdc.DBC.B.L = Data;\r
	423	\r
	424	break;\r
	425	\r
	426	case 0x3: // DBCH\r
	427	Pico_mcd->s68k_regs[5] = 0x4;\r
	428	Pico_mcd->cdc.DBC.B.H = Data;\r
	429	\r
	430	break;\r
	431	\r
	432	case 0x4: // DACL\r
	433	Pico_mcd->s68k_regs[5] = 0x5;\r
	434	Pico_mcd->cdc.DAC.B.L = Data;\r
	435	\r
	436	break;\r
	437	\r
	438	case 0x5: // DACH\r
	439	Pico_mcd->s68k_regs[5] = 0x6;\r
	440	Pico_mcd->cdc.DAC.B.H = Data;\r
	441	\r
	442	break;\r
	443	\r
	444	case 0x6: // DTTRG\r
	445	if (Pico_mcd->cdc.IFCTRL & 0x02) // Data transfer enable ?\r
	446	{\r
	447	Pico_mcd->cdc.IFSTAT &= ~0x08; // Data transfer in progress\r
c459aefd	448	Pico_mcd->scd.Status_CDC \|= 0x08; // Data transfer in progress\r
cc68a136	449	Pico_mcd->s68k_regs[4] &= 0x7F; // A data transfer start\r
cc68a136	450	\r
c459aefd	451	cdprintf("************ Starting Data Transfer *********");\r
cc68a136	452	cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
cb4a513a	453	Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) \| Pico_mcd->s68k_regs[0xB]);\r
cc68a136	454	}\r
	455	break;\r
	456	\r
	457	case 0x7: // DTACK\r
	458	Pico_mcd->cdc.IFSTAT \|= 0x40; // end data transfer interrupt flag cleared\r
	459	break;\r
	460	\r
	461	case 0x8: // WAL\r
	462	Pico_mcd->s68k_regs[5] = 0x9;\r
	463	Pico_mcd->cdc.WA.B.L = Data;\r
	464	\r
	465	break;\r
	466	\r
	467	case 0x9: // WAH\r
	468	Pico_mcd->s68k_regs[5] = 0xA;\r
	469	Pico_mcd->cdc.WA.B.H = Data;\r
	470	\r
	471	break;\r
	472	\r
	473	case 0xA: // CTRL0\r
	474	Pico_mcd->s68k_regs[5] = 0xB;\r
	475	Pico_mcd->cdc.CTRL.B.B0 = Data;\r
	476	\r
	477	break;\r
	478	\r
	479	case 0xB: // CTRL1\r
	480	Pico_mcd->s68k_regs[5] = 0xC;\r
	481	Pico_mcd->cdc.CTRL.B.B1 = Data;\r
	482	\r
	483	break;\r
	484	\r
	485	case 0xC: // PTL\r
	486	Pico_mcd->s68k_regs[5] = 0xD;\r
	487	Pico_mcd->cdc.PT.B.L = Data;\r
	488	\r
	489	break;\r
	490	\r
	491	case 0xD: // PTH\r
	492	Pico_mcd->s68k_regs[5] = 0xE;\r
	493	Pico_mcd->cdc.PT.B.H = Data;\r
	494	\r
	495	break;\r
	496	\r
	497	case 0xE: // CTRL2\r
	498	Pico_mcd->cdc.CTRL.B.B2 = Data;\r
	499	break;\r
	500	\r
	501	case 0xF: // RESET\r
	502	CDC_Reset();\r
	503	break;\r
	504	}\r
	505	}\r
	506	\r
	507	\r
	508	static int bswapwrite(int a, unsigned short d)\r
	509	{\r
	510	(unsigned short )(Pico_mcd->s68k_regs + a) = (d>>8)\|(d<<8);\r
	511	return d + (d >> 8);\r
	512	}\r
	513	\r
	514	void CDD_Export_Status(void)\r
	515	{\r
	516	unsigned int csum;\r
	517	\r
518	csum = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
519	csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
520	csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
521	csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
522	Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
523	csum += Pico_mcd->cdd.Ext;\r
524	Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
525	\r
672ad671	526	Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
cc68a136	527	\r
	528	if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
	529	{\r
	530	dprintf("cdd export irq 4");\r
	531	SekInterruptS68k(4);\r
	532	}\r
	533	\r
c459aefd	534	// cdprintf("CDD exported status\n");\r
c459aefd	535	cdprintf("out: Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136	536	(Pico_mcd->s68k_regs[0x38+0] << 8) \| Pico_mcd->s68k_regs[0x38+1],\r
	537	(Pico_mcd->s68k_regs[0x38+2] << 8) \| Pico_mcd->s68k_regs[0x38+3],\r
	538	(Pico_mcd->s68k_regs[0x38+4] << 8) \| Pico_mcd->s68k_regs[0x38+5],\r
	539	(Pico_mcd->s68k_regs[0x38+6] << 8) \| Pico_mcd->s68k_regs[0x38+7],\r
	540	(Pico_mcd->s68k_regs[0x38+8] << 8) \| Pico_mcd->s68k_regs[0x38+9]);\r
	541	}\r
	542	\r
	543	\r
	544	void CDD_Import_Command(void)\r
	545	{\r
c459aefd	546	// cdprintf("CDD importing command\n");\r
c459aefd	547	cdprintf("in: Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136	548	(Pico_mcd->s68k_regs[0x38+10+0] << 8) \| Pico_mcd->s68k_regs[0x38+10+1],\r
	549	(Pico_mcd->s68k_regs[0x38+10+2] << 8) \| Pico_mcd->s68k_regs[0x38+10+3],\r
	550	(Pico_mcd->s68k_regs[0x38+10+4] << 8) \| Pico_mcd->s68k_regs[0x38+10+5],\r
	551	(Pico_mcd->s68k_regs[0x38+10+6] << 8) \| Pico_mcd->s68k_regs[0x38+10+7],\r
	552	(Pico_mcd->s68k_regs[0x38+10+8] << 8) \| Pico_mcd->s68k_regs[0x38+10+9]);\r
	553	\r
	554	switch (Pico_mcd->s68k_regs[0x38+10+0])\r
	555	{\r
	556	case 0x0: // STATUS (?)\r
	557	Get_Status_CDD_c0();\r
	558	break;\r
	559	\r
	560	case 0x1: // STOP ALL (?)\r
	561	Stop_CDD_c1();\r
	562	break;\r
	563	\r
	564	case 0x2: // GET TOC INFORMATIONS\r
	565	switch(Pico_mcd->s68k_regs[0x38+10+3])\r
	566	{\r
	567	case 0x0: // get current position (MSF format)\r
	568	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
	569	Get_Pos_CDD_c20();\r
	570	break;\r
	571	\r
	572	case 0x1: // get elapsed time of current track played/scanned (relative MSF format)\r
	573	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 1;\r
	574	Get_Track_Pos_CDD_c21();\r
	575	break;\r
	576	\r
	577	case 0x2: // get current track in RS2-RS3\r
	578	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 2;\r
	579	Get_Current_Track_CDD_c22();\r
	580	break;\r
	581	\r
bf098bc5	582	case 0x3: // get total length (MSF format)\r
cc68a136	583	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 3;\r
	584	Get_Total_Lenght_CDD_c23();\r
	585	break;\r
	586	\r
	587	case 0x4: // first & last track number\r
	588	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 4;\r
	589	Get_First_Last_Track_CDD_c24();\r
	590	break;\r
	591	\r
	592	case 0x5: // get track addresse (MSF format)\r
	593	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 5;\r
	594	Get_Track_Adr_CDD_c25();\r
	595	break;\r
	596	\r
	597	default : // invalid, then we return status\r
	598	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 0xF;\r
	599	Get_Status_CDD_c0();\r
	600	break;\r
	601	}\r
	602	break;\r
	603	\r
	604	case 0x3: // READ\r
	605	Play_CDD_c3();\r
	606	break;\r
	607	\r
	608	case 0x4: // SEEK\r
	609	Seek_CDD_c4();\r
	610	break;\r
	611	\r
	612	case 0x6: // PAUSE/STOP\r
	613	Pause_CDD_c6();\r
	614	break;\r
	615	\r
	616	case 0x7: // RESUME\r
	617	Resume_CDD_c7();\r
	618	break;\r
	619	\r
	620	case 0x8: // FAST FOWARD\r
	621	Fast_Foward_CDD_c8();\r
	622	break;\r
	623	\r
	624	case 0x9: // FAST REWIND\r
	625	Fast_Rewind_CDD_c9();\r
	626	break;\r
	627	\r
	628	case 0xA: // RECOVER INITIAL STATE (?)\r
	629	CDD_cA();\r
	630	break;\r
	631	\r
	632	case 0xC: // CLOSE TRAY\r
	633	Close_Tray_CDD_cC();\r
	634	break;\r
	635	\r
	636	case 0xD: // OPEN TRAY\r
	637	Open_Tray_CDD_cD();\r
	638	break;\r
	639	\r
	640	default: // UNKNOWN\r
	641	CDD_Def();\r
	642	break;\r
	643	}\r
	644	}\r
	645	\r