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region detection, cd states wip, fixes, stuff
[picodrive.git] / Pico / cd / LC89510.c
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bf098bc5 1/***********************************************************\r
2 * *\r
3 * This source is taken from the Gens project *\r
4 * Written by Stéphane Dallongeville *\r
5 * Copyright (c) 2002 by Stéphane Dallongeville *\r
6 * Modified/adapted for Picodrive by notaz, 2007 *\r
7 * *\r
8 ***********************************************************/\r
cc68a136 9\r
10#include "../PicoInt.h"\r
11\r
c459aefd 12#define cdprintf dprintf\r
cc68a136 13//#define cdprintf(x...)\r
14\r
15\r
16#define CDC_DMA_SPEED 256\r
17\r
cc68a136 18\r
19static void CDD_Reset(void)\r
20{\r
21 // Reseting CDD\r
22\r
23 memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
24 Pico_mcd->cdd.Status = 0;\r
25 Pico_mcd->cdd.Minute = 0;\r
26 Pico_mcd->cdd.Seconde = 0;\r
27 Pico_mcd->cdd.Frame = 0;\r
28 Pico_mcd->cdd.Ext = 0;\r
29\r
30 // clear receive status and transfer command\r
31 memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
32 Pico_mcd->s68k_regs[0x38+9] = 0xF; // Default checksum\r
33}\r
34\r
35\r
36static void CDC_Reset(void)\r
37{\r
38 // Reseting CDC\r
39\r
40 memset(Pico_mcd->cdc.Buffer, 0, (16 * 1024 * 2) + 2352);\r
41\r
42 CDC_Update_Header();\r
43\r
44 Pico_mcd->cdc.COMIN = 0;\r
45 Pico_mcd->cdc.IFSTAT = 0xFF;\r
46 Pico_mcd->cdc.DAC.N = 0;\r
47 Pico_mcd->cdc.DBC.N = 0;\r
48 Pico_mcd->cdc.HEAD.N = 0x01000000;\r
49 Pico_mcd->cdc.PT.N = 0;\r
50 Pico_mcd->cdc.WA.N = 2352 * 2;\r
51 Pico_mcd->cdc.STAT.N = 0x00000080;\r
52 Pico_mcd->cdc.SBOUT = 0;\r
53 Pico_mcd->cdc.IFCTRL = 0;\r
54 Pico_mcd->cdc.CTRL.N = 0;\r
55\r
51a902ae 56 Pico_mcd->cdd.CDC_Decode_Reg_Read = 0;\r
c459aefd 57 Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136 58}\r
59\r
60\r
61void LC89510_Reset(void)\r
62{\r
63 CDD_Reset();\r
64 CDC_Reset();\r
65\r
cb4a513a 66 // clear DMA_Adr & Stop_Watch\r
67 memset(Pico_mcd->s68k_regs + 0xA, 0, 4);\r
cc68a136 68}\r
69\r
cc68a136 70\r
bf098bc5 71void Update_CDC_TRansfer(int which)\r
72{\r
cb4a513a 73 unsigned int DMA_Adr, dep, length, len;\r
bf098bc5 74 unsigned short *dest;\r
75 unsigned char *src;\r
cc68a136 76\r
77 if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
78 {\r
bf098bc5 79 length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
c459aefd 80 Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
bf098bc5 81 Pico_mcd->s68k_regs[4] |= 0x80; // End data transfer\r
82 Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
83 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
cc68a136 84\r
bf098bc5 85 if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Trasnfer End Interrupt Enable ?\r
cc68a136 86 {\r
87 Pico_mcd->cdc.IFSTAT &= ~0x40;\r
88\r
bf098bc5 89 if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
90 {\r
91 dprintf("cdc DTE irq 5");\r
92 SekInterruptS68k(5);\r
93 }\r
cc68a136 94 }\r
95 }\r
bf098bc5 96 else length = CDC_DMA_SPEED;\r
97\r
cc68a136 98\r
bf098bc5 99 // TODO: dst bounds checking? DAC.N alignment?\r
100 src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
cb4a513a 101 DMA_Adr = (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB];\r
cc68a136 102\r
bf098bc5 103 if (which == 7) // WORD RAM\r
cc68a136 104 {\r
bf098bc5 105 if (Pico_mcd->s68k_regs[3] & 4)\r
cc68a136 106 {\r
cb4a513a 107 dep = ((DMA_Adr & 0x3FFF) << 3);\r
bf098bc5 108 cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
109 Pico_mcd->cdc.DAC.N, dep, length);\r
110\r
cb4a513a 111 dep = ((DMA_Adr & 0x3FFF) << 4);\r
bf098bc5 112 if (!(Pico_mcd->s68k_regs[3]&1)) dep += 2;\r
113 dest = (unsigned short *) (Pico_mcd->word_ram + dep);\r
114\r
115 for (len = length; len > 0; len--, src+=2, dest+=2)\r
116 *dest = (src[0]<<8) | src[1];\r
cc68a136 117 }\r
bf098bc5 118 else\r
119 {\r
cb4a513a 120 dep = ((DMA_Adr & 0x7FFF) << 3);\r
bf098bc5 121 cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
122 Pico_mcd->cdc.DAC.N, dep, length);\r
123 dest = (unsigned short *) (Pico_mcd->word_ram + dep);\r
cc68a136 124\r
bf098bc5 125 for (len = length; len > 0; len--, src+=2, dest++)\r
126 *dest = (src[0]<<8) | src[1];\r
127 }\r
cc68a136 128 }\r
bf098bc5 129 else if (which == 4) // PCM RAM\r
cc68a136 130 {\r
bf098bc5 131#if 0\r
132 dest = (unsigned char *) Ram_PCM;\r
cb4a513a 133 dep = ((DMA_Adr & 0x03FF) << 2) + PCM_Chip.Bank;\r
bf098bc5 134#else\r
cb4a513a 135 cdprintf("CD DMA # %04x -> PCD TODO", Pico_mcd->cdc.DAC.N);\r
bf098bc5 136#endif\r
137 }\r
138 else if (which == 5) // PRG RAM\r
139 {\r
cb4a513a 140 dep = DMA_Adr << 3;\r
bf098bc5 141 dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
142 cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
143 Pico_mcd->cdc.DAC.N, dep, length);\r
cc68a136 144\r
bf098bc5 145 for (len = length; len > 0; len--, src+=2, dest++)\r
146 *dest = (src[0]<<8) | src[1];\r
cc68a136 147 }\r
148\r
bf098bc5 149 length <<= 1;\r
150 Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
c459aefd 151 if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
cc68a136 152 else Pico_mcd->cdc.DBC.N = 0;\r
153}\r
cc68a136 154\r
155\r
156unsigned short Read_CDC_Host(int is_sub)\r
157{\r
158 int addr;\r
159\r
c459aefd 160 if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
cc68a136 161 {\r
162 // Transfer data disabled\r
c459aefd 163 cdprintf("Read_CDC_Host: Transfer data disabled");\r
cc68a136 164 return 0;\r
165 }\r
166\r
167 if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) ||\r
168 (!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
169 {\r
170 // Wrong setting\r
c459aefd 171 cdprintf("Read_CDC_Host: Wrong setting");\r
cc68a136 172 return 0;\r
173 }\r
174\r
175 Pico_mcd->cdc.DBC.N -= 2;\r
176\r
177 if (Pico_mcd->cdc.DBC.N <= 0)\r
178 {\r
179 Pico_mcd->cdc.DBC.N = 0;\r
c459aefd 180 Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
cc68a136 181 Pico_mcd->s68k_regs[4] |= 0x80; // End data transfer\r
182 Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
183 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
184\r
185 if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Transfer End Interrupt Enable ?\r
186 {\r
187 Pico_mcd->cdc.IFSTAT &= ~0x40;\r
188\r
189 if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
190 dprintf("m68k: s68k irq 5");\r
191 SekInterruptS68k(5);\r
192 }\r
193\r
c459aefd 194 cdprintf("CDC - DTE interrupt");\r
cc68a136 195 }\r
196 }\r
197\r
198 addr = Pico_mcd->cdc.DAC.N;\r
199 Pico_mcd->cdc.DAC.N += 2;\r
c459aefd 200\r
201 cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
202 (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
203\r
cc68a136 204 return (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1];\r
205\r
206#if 0\r
207 __asm\r
208 {\r
209 mov esi, Pico_mcd->cdc.DAC.N\r
210 lea ebx, Pico_mcd->cdc.Buffer\r
211// and esi, 0x3FFF\r
212 mov ax, [ebx + esi]\r
213 add esi, 2\r
214 rol ax, 8\r
215 mov Pico_mcd->cdc.DAC.N, esi\r
216 mov val, ax\r
217 }\r
218#endif\r
219}\r
220\r
221\r
222void CDC_Update_Header(void)\r
223{\r
224 if (Pico_mcd->cdc.CTRL.B.B1 & 0x01) // Sub-Header wanted ?\r
225 {\r
226 Pico_mcd->cdc.HEAD.B.B0 = 0;\r
227 Pico_mcd->cdc.HEAD.B.B1 = 0;\r
228 Pico_mcd->cdc.HEAD.B.B2 = 0;\r
229 Pico_mcd->cdc.HEAD.B.B3 = 0;\r
230 }\r
231 else\r
232 {\r
233 _msf MSF;\r
234\r
235 LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
236\r
237 Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
238 Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
239 Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
240 Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
241 }\r
242}\r
243\r
244\r
245unsigned char CDC_Read_Reg(void)\r
246{\r
247 unsigned char ret;\r
248\r
cc68a136 249 switch(Pico_mcd->s68k_regs[5] & 0xF)\r
250 {\r
251 case 0x0: // COMIN\r
c459aefd 252 cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
cc68a136 253\r
254 Pico_mcd->s68k_regs[5] = 0x1;\r
255 return Pico_mcd->cdc.COMIN;\r
256\r
257 case 0x1: // IFSTAT\r
c459aefd 258 cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
cc68a136 259\r
51a902ae 260 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 1); // Reg 1 (decoding)\r
cc68a136 261 Pico_mcd->s68k_regs[5] = 0x2;\r
262 return Pico_mcd->cdc.IFSTAT;\r
263\r
264 case 0x2: // DBCL\r
c459aefd 265 cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
cc68a136 266\r
267 Pico_mcd->s68k_regs[5] = 0x3;\r
268 return Pico_mcd->cdc.DBC.B.L;\r
269\r
270 case 0x3: // DBCH\r
c459aefd 271 cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
cc68a136 272\r
273 Pico_mcd->s68k_regs[5] = 0x4;\r
274 return Pico_mcd->cdc.DBC.B.H;\r
275\r
276 case 0x4: // HEAD0\r
c459aefd 277 cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
cc68a136 278\r
51a902ae 279 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 4); // Reg 4 (decoding)\r
cc68a136 280 Pico_mcd->s68k_regs[5] = 0x5;\r
281 return Pico_mcd->cdc.HEAD.B.B0;\r
282\r
283 case 0x5: // HEAD1\r
c459aefd 284 cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
cc68a136 285\r
51a902ae 286 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 5); // Reg 5 (decoding)\r
cc68a136 287 Pico_mcd->s68k_regs[5] = 0x6;\r
288 return Pico_mcd->cdc.HEAD.B.B1;\r
289\r
290 case 0x6: // HEAD2\r
c459aefd 291 cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
cc68a136 292\r
51a902ae 293 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 6); // Reg 6 (decoding)\r
cc68a136 294 Pico_mcd->s68k_regs[5] = 0x7;\r
295 return Pico_mcd->cdc.HEAD.B.B2;\r
296\r
297 case 0x7: // HEAD3\r
c459aefd 298 cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
cc68a136 299\r
51a902ae 300 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 7); // Reg 7 (decoding)\r
cc68a136 301 Pico_mcd->s68k_regs[5] = 0x8;\r
302 return Pico_mcd->cdc.HEAD.B.B3;\r
303\r
304 case 0x8: // PTL\r
c459aefd 305 cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
cc68a136 306\r
51a902ae 307 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 8); // Reg 8 (decoding)\r
cc68a136 308 Pico_mcd->s68k_regs[5] = 0x9;\r
309 return Pico_mcd->cdc.PT.B.L;\r
310\r
311 case 0x9: // PTH\r
c459aefd 312 cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
cc68a136 313\r
51a902ae 314 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 9); // Reg 9 (decoding)\r
cc68a136 315 Pico_mcd->s68k_regs[5] = 0xA;\r
316 return Pico_mcd->cdc.PT.B.H;\r
317\r
318 case 0xA: // WAL\r
c459aefd 319 cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
cc68a136 320\r
321 Pico_mcd->s68k_regs[5] = 0xB;\r
322 return Pico_mcd->cdc.WA.B.L;\r
323\r
324 case 0xB: // WAH\r
c459aefd 325 cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
cc68a136 326\r
327 Pico_mcd->s68k_regs[5] = 0xC;\r
328 return Pico_mcd->cdc.WA.B.H;\r
329\r
330 case 0xC: // STAT0\r
c459aefd 331 cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
cc68a136 332\r
51a902ae 333 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 12); // Reg 12 (decoding)\r
cc68a136 334 Pico_mcd->s68k_regs[5] = 0xD;\r
335 return Pico_mcd->cdc.STAT.B.B0;\r
336\r
337 case 0xD: // STAT1\r
c459aefd 338 cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
cc68a136 339\r
51a902ae 340 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 13); // Reg 13 (decoding)\r
cc68a136 341 Pico_mcd->s68k_regs[5] = 0xE;\r
342 return Pico_mcd->cdc.STAT.B.B1;\r
343\r
344 case 0xE: // STAT2\r
c459aefd 345 cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
cc68a136 346\r
51a902ae 347 Pico_mcd->cdd.CDC_Decode_Reg_Read |= (1 << 14); // Reg 14 (decoding)\r
cc68a136 348 Pico_mcd->s68k_regs[5] = 0xF;\r
349 return Pico_mcd->cdc.STAT.B.B2;\r
350\r
351 case 0xF: // STAT3\r
c459aefd 352 cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
cc68a136 353\r
354 ret = Pico_mcd->cdc.STAT.B.B3;\r
355 Pico_mcd->cdc.IFSTAT |= 0x20; // decoding interrupt flag cleared\r
356 if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
357 {\r
51a902ae 358 if ((Pico_mcd->cdd.CDC_Decode_Reg_Read & 0x73F2) == 0x73F2)\r
cc68a136 359 Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
360 }\r
361 return ret;\r
362 }\r
363\r
364 return 0;\r
365}\r
366\r
367\r
368void CDC_Write_Reg(unsigned char Data)\r
369{\r
c459aefd 370 cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
cc68a136 371\r
372 switch (Pico_mcd->s68k_regs[5] & 0xF)\r
373 {\r
374 case 0x0: // SBOUT\r
375 Pico_mcd->s68k_regs[5] = 0x1;\r
376 Pico_mcd->cdc.SBOUT = Data;\r
377\r
378 break;\r
379\r
380 case 0x1: // IFCTRL\r
381 Pico_mcd->s68k_regs[5] = 0x2;\r
382 Pico_mcd->cdc.IFCTRL = Data;\r
383\r
384 if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0) // Stop data transfer\r
385 {\r
386 Pico_mcd->cdc.DBC.N = 0;\r
c459aefd 387 Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136 388 Pico_mcd->cdc.IFSTAT |= 0x08; // No more data transfer in progress\r
389 }\r
390 break;\r
391\r
392 case 0x2: // DBCL\r
393 Pico_mcd->s68k_regs[5] = 0x3;\r
394 Pico_mcd->cdc.DBC.B.L = Data;\r
395\r
396 break;\r
397\r
398 case 0x3: // DBCH\r
399 Pico_mcd->s68k_regs[5] = 0x4;\r
400 Pico_mcd->cdc.DBC.B.H = Data;\r
401\r
402 break;\r
403\r
404 case 0x4: // DACL\r
405 Pico_mcd->s68k_regs[5] = 0x5;\r
406 Pico_mcd->cdc.DAC.B.L = Data;\r
407\r
408 break;\r
409\r
410 case 0x5: // DACH\r
411 Pico_mcd->s68k_regs[5] = 0x6;\r
412 Pico_mcd->cdc.DAC.B.H = Data;\r
413\r
414 break;\r
415\r
416 case 0x6: // DTTRG\r
417 if (Pico_mcd->cdc.IFCTRL & 0x02) // Data transfer enable ?\r
418 {\r
419 Pico_mcd->cdc.IFSTAT &= ~0x08; // Data transfer in progress\r
c459aefd 420 Pico_mcd->scd.Status_CDC |= 0x08; // Data transfer in progress\r
cc68a136 421 Pico_mcd->s68k_regs[4] &= 0x7F; // A data transfer start\r
422\r
c459aefd 423 cdprintf("************** Starting Data Transfer ***********");\r
cc68a136 424 cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
cb4a513a 425 Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB]);\r
cc68a136 426 }\r
427 break;\r
428\r
429 case 0x7: // DTACK\r
430 Pico_mcd->cdc.IFSTAT |= 0x40; // end data transfer interrupt flag cleared\r
431 break;\r
432\r
433 case 0x8: // WAL\r
434 Pico_mcd->s68k_regs[5] = 0x9;\r
435 Pico_mcd->cdc.WA.B.L = Data;\r
436\r
437 break;\r
438\r
439 case 0x9: // WAH\r
440 Pico_mcd->s68k_regs[5] = 0xA;\r
441 Pico_mcd->cdc.WA.B.H = Data;\r
442\r
443 break;\r
444\r
445 case 0xA: // CTRL0\r
446 Pico_mcd->s68k_regs[5] = 0xB;\r
447 Pico_mcd->cdc.CTRL.B.B0 = Data;\r
448\r
449 break;\r
450\r
451 case 0xB: // CTRL1\r
452 Pico_mcd->s68k_regs[5] = 0xC;\r
453 Pico_mcd->cdc.CTRL.B.B1 = Data;\r
454\r
455 break;\r
456\r
457 case 0xC: // PTL\r
458 Pico_mcd->s68k_regs[5] = 0xD;\r
459 Pico_mcd->cdc.PT.B.L = Data;\r
460\r
461 break;\r
462\r
463 case 0xD: // PTH\r
464 Pico_mcd->s68k_regs[5] = 0xE;\r
465 Pico_mcd->cdc.PT.B.H = Data;\r
466\r
467 break;\r
468\r
469 case 0xE: // CTRL2\r
470 Pico_mcd->cdc.CTRL.B.B2 = Data;\r
471 break;\r
472\r
473 case 0xF: // RESET\r
474 CDC_Reset();\r
475 break;\r
476 }\r
477}\r
478\r
479\r
480static int bswapwrite(int a, unsigned short d)\r
481{\r
482 *(unsigned short *)(Pico_mcd->s68k_regs + a) = (d>>8)|(d<<8);\r
483 return d + (d >> 8);\r
484}\r
485\r
486void CDD_Export_Status(void)\r
487{\r
488 unsigned int csum;\r
489\r
490 csum = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
491 csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
492 csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
493 csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
494 Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
495 csum += Pico_mcd->cdd.Ext;\r
496 Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
497\r
672ad671 498 Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
cc68a136 499\r
500 if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
501 {\r
502 dprintf("cdd export irq 4");\r
503 SekInterruptS68k(4);\r
504 }\r
505\r
c459aefd 506// cdprintf("CDD exported status\n");\r
507 cdprintf("out: Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136 508 (Pico_mcd->s68k_regs[0x38+0] << 8) | Pico_mcd->s68k_regs[0x38+1],\r
509 (Pico_mcd->s68k_regs[0x38+2] << 8) | Pico_mcd->s68k_regs[0x38+3],\r
510 (Pico_mcd->s68k_regs[0x38+4] << 8) | Pico_mcd->s68k_regs[0x38+5],\r
511 (Pico_mcd->s68k_regs[0x38+6] << 8) | Pico_mcd->s68k_regs[0x38+7],\r
512 (Pico_mcd->s68k_regs[0x38+8] << 8) | Pico_mcd->s68k_regs[0x38+9]);\r
513}\r
514\r
515\r
516void CDD_Import_Command(void)\r
517{\r
c459aefd 518// cdprintf("CDD importing command\n");\r
519 cdprintf("in: Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136 520 (Pico_mcd->s68k_regs[0x38+10+0] << 8) | Pico_mcd->s68k_regs[0x38+10+1],\r
521 (Pico_mcd->s68k_regs[0x38+10+2] << 8) | Pico_mcd->s68k_regs[0x38+10+3],\r
522 (Pico_mcd->s68k_regs[0x38+10+4] << 8) | Pico_mcd->s68k_regs[0x38+10+5],\r
523 (Pico_mcd->s68k_regs[0x38+10+6] << 8) | Pico_mcd->s68k_regs[0x38+10+7],\r
524 (Pico_mcd->s68k_regs[0x38+10+8] << 8) | Pico_mcd->s68k_regs[0x38+10+9]);\r
525\r
526 switch (Pico_mcd->s68k_regs[0x38+10+0])\r
527 {\r
528 case 0x0: // STATUS (?)\r
529 Get_Status_CDD_c0();\r
530 break;\r
531\r
532 case 0x1: // STOP ALL (?)\r
533 Stop_CDD_c1();\r
534 break;\r
535\r
536 case 0x2: // GET TOC INFORMATIONS\r
537 switch(Pico_mcd->s68k_regs[0x38+10+3])\r
538 {\r
539 case 0x0: // get current position (MSF format)\r
540 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
541 Get_Pos_CDD_c20();\r
542 break;\r
543\r
544 case 0x1: // get elapsed time of current track played/scanned (relative MSF format)\r
545 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 1;\r
546 Get_Track_Pos_CDD_c21();\r
547 break;\r
548\r
549 case 0x2: // get current track in RS2-RS3\r
550 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 2;\r
551 Get_Current_Track_CDD_c22();\r
552 break;\r
553\r
bf098bc5 554 case 0x3: // get total length (MSF format)\r
cc68a136 555 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 3;\r
556 Get_Total_Lenght_CDD_c23();\r
557 break;\r
558\r
559 case 0x4: // first & last track number\r
560 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 4;\r
561 Get_First_Last_Track_CDD_c24();\r
562 break;\r
563\r
564 case 0x5: // get track addresse (MSF format)\r
565 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 5;\r
566 Get_Track_Adr_CDD_c25();\r
567 break;\r
568\r
569 default : // invalid, then we return status\r
570 Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 0xF;\r
571 Get_Status_CDD_c0();\r
572 break;\r
573 }\r
574 break;\r
575\r
576 case 0x3: // READ\r
577 Play_CDD_c3();\r
578 break;\r
579\r
580 case 0x4: // SEEK\r
581 Seek_CDD_c4();\r
582 break;\r
583\r
584 case 0x6: // PAUSE/STOP\r
585 Pause_CDD_c6();\r
586 break;\r
587\r
588 case 0x7: // RESUME\r
589 Resume_CDD_c7();\r
590 break;\r
591\r
592 case 0x8: // FAST FOWARD\r
593 Fast_Foward_CDD_c8();\r
594 break;\r
595\r
596 case 0x9: // FAST REWIND\r
597 Fast_Rewind_CDD_c9();\r
598 break;\r
599\r
600 case 0xA: // RECOVER INITIAL STATE (?)\r
601 CDD_cA();\r
602 break;\r
603\r
604 case 0xC: // CLOSE TRAY\r
605 Close_Tray_CDD_cC();\r
606 break;\r
607\r
608 case 0xD: // OPEN TRAY\r
609 Open_Tray_CDD_cD();\r
610 break;\r
611\r
612 default: // UNKNOWN\r
613 CDD_Def();\r
614 break;\r
615 }\r
616}\r
617\r
fast MegaDrive/MegaCD/32X emulator