[picodrive.git] / Pico / cd / LC89510.c

/***********************************************************\r
 *                                                         *\r
 * This source is taken from the Gens project              *\r
 * Written by Stéphane Dallongeville                       *\r
 * Copyright (c) 2002 by Stéphane Dallongeville            *\r
 * Modified/adapted for Picodrive by notaz, 2007           *\r
 *                                                         *\r
 ***********************************************************/\r
\r
#include "../PicoInt.h"\r
\r
#define cdprintf dprintf\r
//#define cdprintf(x...)\r
\r
\r
#define CDC_DMA_SPEED 256\r
\r
\r
static void CDD_Reset(void)\r
{\r
	// Reseting CDD\r
\r
	memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
	Pico_mcd->cdd.Status = 0;\r
	Pico_mcd->cdd.Minute = 0;\r
	Pico_mcd->cdd.Seconde = 0;\r
	Pico_mcd->cdd.Frame = 0;\r
	Pico_mcd->cdd.Ext = 0;\r
\r
	// clear receive status and transfer command\r
	memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
	Pico_mcd->s68k_regs[0x38+9] = 0xF;		// Default checksum\r
}\r
\r
\r
static void CDC_Reset(void)\r
{\r
	// Reseting CDC\r
\r
	memset(Pico_mcd->cdc.Buffer, 0, sizeof(Pico_mcd->cdc.Buffer));\r
\r
	Pico_mcd->cdc.COMIN = 0;\r
	Pico_mcd->cdc.IFSTAT = 0xFF;\r
	Pico_mcd->cdc.DAC.N = 0;\r
	Pico_mcd->cdc.DBC.N = 0;\r
	Pico_mcd->cdc.HEAD.N = 0x01000000;\r
	Pico_mcd->cdc.PT.N = 0;\r
	Pico_mcd->cdc.WA.N = 2352 * 2;\r
	Pico_mcd->cdc.STAT.N = 0x00000080;\r
	Pico_mcd->cdc.SBOUT = 0;\r
	Pico_mcd->cdc.IFCTRL = 0;\r
	Pico_mcd->cdc.CTRL.N = 0;\r
\r
	Pico_mcd->cdc.Decode_Reg_Read = 0;\r
	Pico_mcd->scd.Status_CDC &= ~0x08;\r
}\r
\r
\r
void LC89510_Reset(void)\r
{\r
	CDD_Reset();\r
	CDC_Reset();\r
\r
	// clear DMA_Adr & Stop_Watch\r
	memset(Pico_mcd->s68k_regs + 0xA, 0, 4);\r
}\r
\r
\r
void Update_CDC_TRansfer(int which)\r
{\r
	unsigned int DMA_Adr, dep, length;\r
	unsigned short *dest;\r
	unsigned char  *src;\r
\r
	if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
	{\r
		length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
		Pico_mcd->scd.Status_CDC &= ~0x08;	// Last transfer\r
		Pico_mcd->s68k_regs[4] |=  0x80;	// End data transfer\r
		Pico_mcd->s68k_regs[4] &= ~0x40;	// no more data ready\r
		Pico_mcd->cdc.IFSTAT |= 0x08;		// No more data transfer in progress\r
\r
		if (Pico_mcd->cdc.IFCTRL & 0x40)	// DTEIEN = Data Trasnfer End Interrupt Enable ?\r
		{\r
			Pico_mcd->cdc.IFSTAT &= ~0x40;\r
\r
			if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
			{\r
				dprintf("cdc DTE irq 5");\r
				SekInterruptS68k(5);\r
			}\r
		}\r
	}\r
	else length = CDC_DMA_SPEED;\r
\r
\r
	// TODO: dst bounds checking?\r
	src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
	DMA_Adr = (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB];\r
\r
	if (which == 7) // WORD RAM\r
	{\r
		if (Pico_mcd->s68k_regs[3] & 4)\r
		{\r
			// test: Final Fight\r
			int bank = !(Pico_mcd->s68k_regs[3]&1);\r
			dep = ((DMA_Adr & 0x3FFF) << 3);\r
			cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
					Pico_mcd->cdc.DAC.N, dep, length);\r
\r
			dest = (unsigned short *) (Pico_mcd->word_ram1M[bank] + dep);\r
\r
			memcpy16bswap(dest, src, length);\r
\r
			{ // debug\r
				unsigned char *b1 = Pico_mcd->word_ram1M[bank] + dep;\r
				unsigned char *b2 = (unsigned char *)(dest+length) - 8;\r
				dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
					b1[0], b1[1], b1[4], b1[5], b2[0], b2[1], b2[4], b2[5]);\r
			}\r
		}\r
		else\r
		{\r
			dep = ((DMA_Adr & 0x7FFF) << 3);\r
			cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
					Pico_mcd->cdc.DAC.N, dep, length);\r
			dest = (unsigned short *) (Pico_mcd->word_ram2M + dep);\r
\r
			memcpy16bswap(dest, src, length);\r
\r
			{ // debug\r
				unsigned char *b1 = Pico_mcd->word_ram2M + dep;\r
				unsigned char *b2 = (unsigned char *)(dest+length) - 4;\r
				dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
					b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
			}\r
		}\r
	}\r
	else if (which == 4) // PCM RAM (check: popful Mail)\r
	{\r
		dep = (DMA_Adr & 0x03FF) << 2;\r
		dprintf("CD DMA # %04x -> PCM[%i] # %04x, len=%i",\r
			Pico_mcd->cdc.DAC.N, Pico_mcd->pcm.bank, dep, length);\r
		dest = (unsigned short *) (Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank] + dep);\r
\r
		if (Pico_mcd->cdc.DAC.N & 1) /* unaligned src? */\r
			memcpy(dest, src, length*2);\r
		else	memcpy16(dest, (unsigned short *) src, length);\r
	}\r
	else if (which == 5) // PRG RAM\r
	{\r
		dep = DMA_Adr << 3;\r
		dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
		cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
				Pico_mcd->cdc.DAC.N, dep, length);\r
\r
		memcpy16bswap(dest, src, length);\r
\r
		{ // debug\r
			unsigned char *b1 = Pico_mcd->prg_ram + dep;\r
			unsigned char *b2 = (unsigned char *)(dest+length) - 4;\r
			dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
				b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
		}\r
	}\r
\r
	length <<= 1;\r
	Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
	if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
	else Pico_mcd->cdc.DBC.N = 0;\r
\r
	// update DMA_Adr\r
	length >>= 2;\r
	if (which != 4) length >>= 1;\r
	DMA_Adr += length;\r
	Pico_mcd->s68k_regs[0xA] = DMA_Adr >> 8;\r
	Pico_mcd->s68k_regs[0xB] = DMA_Adr;\r
}\r
\r
\r
unsigned short Read_CDC_Host(int is_sub)\r
{\r
	int addr;\r
\r
	if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
	{\r
		// Transfer data disabled\r
		cdprintf("Read_CDC_Host FIXME: Transfer data disabled");\r
		return 0;\r
	}\r
\r
	if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) ||\r
		(!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
	{\r
		// Wrong setting\r
		cdprintf("Read_CDC_Host FIXME: Wrong setting");\r
		return 0;\r
	}\r
\r
	Pico_mcd->cdc.DBC.N -= 2;\r
\r
	if (Pico_mcd->cdc.DBC.N <= 0)\r
	{\r
		Pico_mcd->cdc.DBC.N = 0;\r
		Pico_mcd->scd.Status_CDC &= ~0x08;		// Last transfer\r
		Pico_mcd->s68k_regs[4] |=  0x80;		// End data transfer\r
		Pico_mcd->s68k_regs[4] &= ~0x40;		// no more data ready\r
		Pico_mcd->cdc.IFSTAT |= 0x08;			// No more data transfer in progress\r
\r
		if (Pico_mcd->cdc.IFCTRL & 0x40)		// DTEIEN = Data Transfer End Interrupt Enable ?\r
		{\r
			Pico_mcd->cdc.IFSTAT &= ~0x40;\r
\r
			if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
				dprintf("m68k: s68k irq 5");\r
				SekInterruptS68k(5);\r
			}\r
\r
			cdprintf("CDC - DTE interrupt");\r
		}\r
	}\r
\r
	addr = Pico_mcd->cdc.DAC.N;\r
	Pico_mcd->cdc.DAC.N += 2;\r
\r
	cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
		(Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
\r
	return (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1];\r
\r
#if 0\r
	__asm\r
	{\r
		mov esi, Pico_mcd->cdc.DAC.N\r
		lea ebx, Pico_mcd->cdc.Buffer\r
//				and esi, 0x3FFF\r
		mov ax, [ebx + esi]\r
		add esi, 2\r
		rol ax, 8\r
		mov Pico_mcd->cdc.DAC.N, esi\r
		mov val, ax\r
	}\r
#endif\r
}\r
\r
\r
void CDC_Update_Header(void)\r
{\r
	if (Pico_mcd->cdc.CTRL.B.B1 & 0x01)		// Sub-Header wanted ?\r
	{\r
		Pico_mcd->cdc.HEAD.B.B0 = 0;\r
		Pico_mcd->cdc.HEAD.B.B1 = 0;\r
		Pico_mcd->cdc.HEAD.B.B2 = 0;\r
		Pico_mcd->cdc.HEAD.B.B3 = 0;\r
	}\r
	else\r
	{\r
		_msf MSF;\r
\r
		LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
\r
		Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
		Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
		Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
		Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
	}\r
}\r
\r
\r
unsigned char CDC_Read_Reg(void)\r
{\r
	unsigned char ret;\r
\r
	switch(Pico_mcd->s68k_regs[5] & 0xF)\r
	{\r
		case 0x0: // COMIN\r
			cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
\r
			Pico_mcd->s68k_regs[5] = 0x1;\r
			return Pico_mcd->cdc.COMIN;\r
\r
		case 0x1: // IFSTAT\r
			cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 1);		// Reg 1 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x2;\r
			return Pico_mcd->cdc.IFSTAT;\r
\r
		case 0x2: // DBCL\r
			cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
\r
			Pico_mcd->s68k_regs[5] = 0x3;\r
			return Pico_mcd->cdc.DBC.B.L;\r
\r
		case 0x3: // DBCH\r
			cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
\r
			Pico_mcd->s68k_regs[5] = 0x4;\r
			return Pico_mcd->cdc.DBC.B.H;\r
\r
		case 0x4: // HEAD0\r
			cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 4);		// Reg 4 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x5;\r
			return Pico_mcd->cdc.HEAD.B.B0;\r
\r
		case 0x5: // HEAD1\r
			cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 5);		// Reg 5 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x6;\r
			return Pico_mcd->cdc.HEAD.B.B1;\r
\r
		case 0x6: // HEAD2\r
			cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 6);		// Reg 6 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x7;\r
			return Pico_mcd->cdc.HEAD.B.B2;\r
\r
		case 0x7: // HEAD3\r
			cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 7);		// Reg 7 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x8;\r
			return Pico_mcd->cdc.HEAD.B.B3;\r
\r
		case 0x8: // PTL\r
			cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 8);		// Reg 8 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x9;\r
			return Pico_mcd->cdc.PT.B.L;\r
\r
		case 0x9: // PTH\r
			cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 9);		// Reg 9 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xA;\r
			return Pico_mcd->cdc.PT.B.H;\r
\r
		case 0xA: // WAL\r
			cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
\r
			Pico_mcd->s68k_regs[5] = 0xB;\r
			return Pico_mcd->cdc.WA.B.L;\r
\r
		case 0xB: // WAH\r
			cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
\r
			Pico_mcd->s68k_regs[5] = 0xC;\r
			return Pico_mcd->cdc.WA.B.H;\r
\r
		case 0xC: // STAT0\r
			cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 12);		// Reg 12 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xD;\r
			return Pico_mcd->cdc.STAT.B.B0;\r
\r
		case 0xD: // STAT1\r
			cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 13);		// Reg 13 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xE;\r
			return Pico_mcd->cdc.STAT.B.B1;\r
\r
		case 0xE: // STAT2\r
			cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 14);		// Reg 14 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xF;\r
			return Pico_mcd->cdc.STAT.B.B2;\r
\r
		case 0xF: // STAT3\r
			cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
\r
			ret = Pico_mcd->cdc.STAT.B.B3;\r
			Pico_mcd->cdc.IFSTAT |= 0x20;			// decoding interrupt flag cleared\r
			if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
			{\r
				if ((Pico_mcd->cdc.Decode_Reg_Read & 0x73F2) == 0x73F2)\r
					Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
			}\r
			return ret;\r
	}\r
\r
	return 0;\r
}\r
\r
\r
void CDC_Write_Reg(unsigned char Data)\r
{\r
	cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
\r
	switch (Pico_mcd->s68k_regs[5] & 0xF)\r
	{\r
		case 0x0: // SBOUT\r
			Pico_mcd->s68k_regs[5] = 0x1;\r
			Pico_mcd->cdc.SBOUT = Data;\r
\r
			break;\r
\r
		case 0x1: // IFCTRL\r
			Pico_mcd->s68k_regs[5] = 0x2;\r
			Pico_mcd->cdc.IFCTRL = Data;\r
\r
			if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0)		// Stop data transfer\r
			{\r
				Pico_mcd->cdc.DBC.N = 0;\r
				Pico_mcd->scd.Status_CDC &= ~0x08;\r
				Pico_mcd->cdc.IFSTAT |= 0x08;		// No more data transfer in progress\r
			}\r
			break;\r
\r
		case 0x2: // DBCL\r
			Pico_mcd->s68k_regs[5] = 0x3;\r
			Pico_mcd->cdc.DBC.B.L = Data;\r
\r
			break;\r
\r
		case 0x3: // DBCH\r
			Pico_mcd->s68k_regs[5] = 0x4;\r
			Pico_mcd->cdc.DBC.B.H = Data;\r
\r
			break;\r
\r
		case 0x4: // DACL\r
			Pico_mcd->s68k_regs[5] = 0x5;\r
			Pico_mcd->cdc.DAC.B.L = Data;\r
\r
			break;\r
\r
		case 0x5: // DACH\r
			Pico_mcd->s68k_regs[5] = 0x6;\r
			Pico_mcd->cdc.DAC.B.H = Data;\r
\r
			break;\r
\r
		case 0x6: // DTTRG\r
			if (Pico_mcd->cdc.IFCTRL & 0x02)		// Data transfer enable ?\r
			{\r
				Pico_mcd->cdc.IFSTAT &= ~0x08;		// Data transfer in progress\r
				Pico_mcd->scd.Status_CDC |= 0x08;	// Data transfer in progress\r
				Pico_mcd->s68k_regs[4] &= 0x7F;		// A data transfer start\r
\r
				cdprintf("************** Starting Data Transfer ***********");\r
				cdprintf("RS0 = %.4X  DAC = %.4X  DBC = %.4X  DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
					Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB]);\r
			}\r
			break;\r
\r
		case 0x7: // DTACK\r
			Pico_mcd->cdc.IFSTAT |= 0x40;			// end data transfer interrupt flag cleared\r
			break;\r
\r
		case 0x8: // WAL\r
			Pico_mcd->s68k_regs[5] = 0x9;\r
			Pico_mcd->cdc.WA.B.L = Data;\r
\r
			break;\r
\r
		case 0x9: // WAH\r
			Pico_mcd->s68k_regs[5] = 0xA;\r
			Pico_mcd->cdc.WA.B.H = Data;\r
\r
			break;\r
\r
		case 0xA: // CTRL0\r
			Pico_mcd->s68k_regs[5] = 0xB;\r
			Pico_mcd->cdc.CTRL.B.B0 = Data;\r
\r
			break;\r
\r
		case 0xB: // CTRL1\r
			Pico_mcd->s68k_regs[5] = 0xC;\r
			Pico_mcd->cdc.CTRL.B.B1 = Data;\r
\r
			break;\r
\r
		case 0xC: // PTL\r
			Pico_mcd->s68k_regs[5] = 0xD;\r
			Pico_mcd->cdc.PT.B.L = Data;\r
\r
			break;\r
\r
		case 0xD: // PTH\r
			Pico_mcd->s68k_regs[5] = 0xE;\r
			Pico_mcd->cdc.PT.B.H = Data;\r
\r
			break;\r
\r
		case 0xE: // CTRL2\r
			Pico_mcd->cdc.CTRL.B.B2 = Data;\r
			break;\r
\r
		case 0xF: // RESET\r
			CDC_Reset();\r
			break;\r
	}\r
}\r
\r
\r
static int bswapwrite(int a, unsigned short d)\r
{\r
	*(unsigned short *)(Pico_mcd->s68k_regs + a) = (d>>8)|(d<<8);\r
	return d + (d >> 8);\r
}\r
\r
void CDD_Export_Status(void)\r
{\r
	unsigned int csum;\r
\r
	csum  = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
	csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
	csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
	csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
	Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
	csum += Pico_mcd->cdd.Ext;\r
	Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
\r
	Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
\r
	if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
	{\r
		dprintf("cdd export irq 4");\r
		SekInterruptS68k(4);\r
	}\r
\r
//	cdprintf("CDD exported status\n");\r
	cdprintf("out:  Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X  Checksum=%.4X",\r
		(Pico_mcd->s68k_regs[0x38+0] << 8) | Pico_mcd->s68k_regs[0x38+1],\r
		(Pico_mcd->s68k_regs[0x38+2] << 8) | Pico_mcd->s68k_regs[0x38+3],\r
		(Pico_mcd->s68k_regs[0x38+4] << 8) | Pico_mcd->s68k_regs[0x38+5],\r
		(Pico_mcd->s68k_regs[0x38+6] << 8) | Pico_mcd->s68k_regs[0x38+7],\r
		(Pico_mcd->s68k_regs[0x38+8] << 8) | Pico_mcd->s68k_regs[0x38+9]);\r
}\r
\r
\r
void CDD_Import_Command(void)\r
{\r
//	cdprintf("CDD importing command\n");\r
	cdprintf("in:  Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X  Checksum=%.4X",\r
		(Pico_mcd->s68k_regs[0x38+10+0] << 8) | Pico_mcd->s68k_regs[0x38+10+1],\r
		(Pico_mcd->s68k_regs[0x38+10+2] << 8) | Pico_mcd->s68k_regs[0x38+10+3],\r
		(Pico_mcd->s68k_regs[0x38+10+4] << 8) | Pico_mcd->s68k_regs[0x38+10+5],\r
		(Pico_mcd->s68k_regs[0x38+10+6] << 8) | Pico_mcd->s68k_regs[0x38+10+7],\r
		(Pico_mcd->s68k_regs[0x38+10+8] << 8) | Pico_mcd->s68k_regs[0x38+10+9]);\r
\r
	switch (Pico_mcd->s68k_regs[0x38+10+0])\r
	{\r
		case 0x0:	// STATUS (?)\r
			Get_Status_CDD_c0();\r
			break;\r
\r
		case 0x1:	// STOP ALL (?)\r
			Stop_CDD_c1();\r
			break;\r
\r
		case 0x2:	// GET TOC INFORMATIONS\r
			switch(Pico_mcd->s68k_regs[0x38+10+3])\r
			{\r
				case 0x0:	// get current position (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
					Get_Pos_CDD_c20();\r
					break;\r
\r
				case 0x1:	// get elapsed time of current track played/scanned (relative MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 1;\r
					Get_Track_Pos_CDD_c21();\r
					break;\r
\r
				case 0x2:	// get current track in RS2-RS3\r
					Pico_mcd->cdd.Status =  (Pico_mcd->cdd.Status & 0xFF00) | 2;\r
					Get_Current_Track_CDD_c22();\r
					break;\r
\r
				case 0x3:	// get total length (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 3;\r
					Get_Total_Lenght_CDD_c23();\r
					break;\r
\r
				case 0x4:	// first & last track number\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 4;\r
					Get_First_Last_Track_CDD_c24();\r
					break;\r
\r
				case 0x5:	// get track addresse (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 5;\r
					Get_Track_Adr_CDD_c25();\r
					break;\r
\r
				default :	// invalid, then we return status\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 0xF;\r
					Get_Status_CDD_c0();\r
					break;\r
			}\r
			break;\r
\r
		case 0x3:	// READ\r
			Play_CDD_c3();\r
			break;\r
\r
		case 0x4:	// SEEK\r
			Seek_CDD_c4();\r
			break;\r
\r
		case 0x6:	// PAUSE/STOP\r
			Pause_CDD_c6();\r
			break;\r
\r
		case 0x7:	// RESUME\r
			Resume_CDD_c7();\r
			break;\r
\r
		case 0x8:	// FAST FOWARD\r
			Fast_Foward_CDD_c8();\r
			break;\r
\r
		case 0x9:	// FAST REWIND\r
			Fast_Rewind_CDD_c9();\r
			break;\r
\r
		case 0xA:	// RECOVER INITIAL STATE (?)\r
			CDD_cA();\r
			break;\r
\r
		case 0xC:	// CLOSE TRAY\r
			Close_Tray_CDD_cC();\r
			break;\r
\r
		case 0xD:	// OPEN TRAY\r
			Open_Tray_CDD_cD();\r
			break;\r
\r
		default:	// UNKNOWN\r
			CDD_Def();\r
			break;\r
	}\r
}\r
\r
Commit	Line	Data
bf098bc5	1	/***********************************************************\r
	2	* *\r
	3	* This source is taken from the Gens project *\r
	4	* Written by Stéphane Dallongeville *\r
	5	* Copyright (c) 2002 by Stéphane Dallongeville *\r
	6	* Modified/adapted for Picodrive by notaz, 2007 *\r
	7	* *\r
	8	***********************************************************/\r
cc68a136	9	\r
	10	#include "../PicoInt.h"\r
	11	\r
c459aefd	12	#define cdprintf dprintf\r
cc68a136	13	//#define cdprintf(x...)\r
	14	\r
	15	\r
	16	#define CDC_DMA_SPEED 256\r
	17	\r
cc68a136	18	\r
	19	static void CDD_Reset(void)\r
	20	{\r
	21	// Reseting CDD\r
	22	\r
	23	memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
	24	Pico_mcd->cdd.Status = 0;\r
	25	Pico_mcd->cdd.Minute = 0;\r
	26	Pico_mcd->cdd.Seconde = 0;\r
	27	Pico_mcd->cdd.Frame = 0;\r
	28	Pico_mcd->cdd.Ext = 0;\r
	29	\r
	30	// clear receive status and transfer command\r
	31	memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
	32	Pico_mcd->s68k_regs[0x38+9] = 0xF; // Default checksum\r
	33	}\r
	34	\r
	35	\r
	36	static void CDC_Reset(void)\r
	37	{\r
	38	// Reseting CDC\r
	39	\r
5c69a605	40	memset(Pico_mcd->cdc.Buffer, 0, sizeof(Pico_mcd->cdc.Buffer));\r
cc68a136	41	\r
	42	Pico_mcd->cdc.COMIN = 0;\r
	43	Pico_mcd->cdc.IFSTAT = 0xFF;\r
	44	Pico_mcd->cdc.DAC.N = 0;\r
	45	Pico_mcd->cdc.DBC.N = 0;\r
	46	Pico_mcd->cdc.HEAD.N = 0x01000000;\r
	47	Pico_mcd->cdc.PT.N = 0;\r
	48	Pico_mcd->cdc.WA.N = 2352 * 2;\r
	49	Pico_mcd->cdc.STAT.N = 0x00000080;\r
	50	Pico_mcd->cdc.SBOUT = 0;\r
	51	Pico_mcd->cdc.IFCTRL = 0;\r
	52	Pico_mcd->cdc.CTRL.N = 0;\r
	53	\r
75736070	54	Pico_mcd->cdc.Decode_Reg_Read = 0;\r
c459aefd	55	Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136	56	}\r
	57	\r
	58	\r
	59	void LC89510_Reset(void)\r
	60	{\r
	61	CDD_Reset();\r
	62	CDC_Reset();\r
	63	\r
cb4a513a	64	// clear DMA_Adr & Stop_Watch\r
cb4a513a	65	memset(Pico_mcd->s68k_regs + 0xA, 0, 4);\r
cc68a136	66	}\r
cc68a136	67	\r
cc68a136	68	\r
bf098bc5	69	void Update_CDC_TRansfer(int which)\r
bf098bc5	70	{\r
0a051f55	71	unsigned int DMA_Adr, dep, length;\r
bf098bc5	72	unsigned short *dest;\r
bf098bc5	73	unsigned char *src;\r
cc68a136	74	\r
	75	if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
	76	{\r
bf098bc5	77	length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
c459aefd	78	Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
bf098bc5	79	Pico_mcd->s68k_regs[4] \|= 0x80; // End data transfer\r
	80	Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
	81	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
cc68a136	82	\r
bf098bc5	83	if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Trasnfer End Interrupt Enable ?\r
cc68a136	84	{\r
	85	Pico_mcd->cdc.IFSTAT &= ~0x40;\r
	86	\r
bf098bc5	87	if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
	88	{\r
	89	dprintf("cdc DTE irq 5");\r
	90	SekInterruptS68k(5);\r
	91	}\r
cc68a136	92	}\r
cc68a136	93	}\r
bf098bc5	94	else length = CDC_DMA_SPEED;\r
bf098bc5	95	\r
cc68a136	96	\r
0a051f55	97	// TODO: dst bounds checking?\r
bf098bc5	98	src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
cb4a513a	99	DMA_Adr = (Pico_mcd->s68k_regs[0xA]<<8) \| Pico_mcd->s68k_regs[0xB];\r
cc68a136	100	\r
bf098bc5	101	if (which == 7) // WORD RAM\r
cc68a136	102	{\r
bf098bc5	103	if (Pico_mcd->s68k_regs[3] & 4)\r
cc68a136	104	{\r
fa1e5e29	105	// test: Final Fight\r
fa1e5e29	106	int bank = !(Pico_mcd->s68k_regs[3]&1);\r
cb4a513a	107	dep = ((DMA_Adr & 0x3FFF) << 3);\r
bf098bc5	108	cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
	109	Pico_mcd->cdc.DAC.N, dep, length);\r
	110	\r
fa1e5e29	111	dest = (unsigned short *) (Pico_mcd->word_ram1M[bank] + dep);\r
bf098bc5	112	\r
0a051f55	113	memcpy16bswap(dest, src, length);\r
1cd356a3	114	\r
1cd356a3	115	{ // debug\r
fa1e5e29	116	unsigned char *b1 = Pico_mcd->word_ram1M[bank] + dep;\r
0a051f55	117	unsigned char b2 = (unsigned char )(dest+length) - 8;\r
1cd356a3	118	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
	119	b1[0], b1[1], b1[4], b1[5], b2[0], b2[1], b2[4], b2[5]);\r
	120	}\r
cc68a136	121	}\r
bf098bc5	122	else\r
bf098bc5	123	{\r
cb4a513a	124	dep = ((DMA_Adr & 0x7FFF) << 3);\r
bf098bc5	125	cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
bf098bc5	126	Pico_mcd->cdc.DAC.N, dep, length);\r
fa1e5e29	127	dest = (unsigned short *) (Pico_mcd->word_ram2M + dep);\r
cc68a136	128	\r
0a051f55	129	memcpy16bswap(dest, src, length);\r
1cd356a3	130	\r
1cd356a3	131	{ // debug\r
fa1e5e29	132	unsigned char *b1 = Pico_mcd->word_ram2M + dep;\r
0a051f55	133	unsigned char b2 = (unsigned char )(dest+length) - 4;\r
1cd356a3	134	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
	135	b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
	136	}\r
bf098bc5	137	}\r
cc68a136	138	}\r
0a051f55	139	else if (which == 4) // PCM RAM (check: popful Mail)\r
cc68a136	140	{\r
0a051f55	141	dep = (DMA_Adr & 0x03FF) << 2;\r
	142	dprintf("CD DMA # %04x -> PCM[%i] # %04x, len=%i",\r
	143	Pico_mcd->cdc.DAC.N, Pico_mcd->pcm.bank, dep, length);\r
	144	dest = (unsigned short *) (Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank] + dep);\r
	145	\r
	146	if (Pico_mcd->cdc.DAC.N & 1) /* unaligned src? */\r
	147	memcpy(dest, src, length*2);\r
	148	else memcpy16(dest, (unsigned short *) src, length);\r
bf098bc5	149	}\r
	150	else if (which == 5) // PRG RAM\r
	151	{\r
cb4a513a	152	dep = DMA_Adr << 3;\r
bf098bc5	153	dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
	154	cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
	155	Pico_mcd->cdc.DAC.N, dep, length);\r
cc68a136	156	\r
0a051f55	157	memcpy16bswap(dest, src, length);\r
1cd356a3	158	\r
	159	{ // debug\r
	160	unsigned char *b1 = Pico_mcd->prg_ram + dep;\r
0a051f55	161	unsigned char b2 = (unsigned char )(dest+length) - 4;\r
1cd356a3	162	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
	163	b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
	164	}\r
cc68a136	165	}\r
cc68a136	166	\r
bf098bc5	167	length <<= 1;\r
bf098bc5	168	Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
c459aefd	169	if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
cc68a136	170	else Pico_mcd->cdc.DBC.N = 0;\r
1cd356a3	171	\r
	172	// update DMA_Adr\r
	173	length >>= 2;\r
	174	if (which != 4) length >>= 1;\r
	175	DMA_Adr += length;\r
	176	Pico_mcd->s68k_regs[0xA] = DMA_Adr >> 8;\r
	177	Pico_mcd->s68k_regs[0xB] = DMA_Adr;\r
cc68a136	178	}\r
cc68a136	179	\r
	180	\r
	181	unsigned short Read_CDC_Host(int is_sub)\r
	182	{\r
	183	int addr;\r
	184	\r
c459aefd	185	if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
cc68a136	186	{\r
cc68a136	187	// Transfer data disabled\r
fa1e5e29	188	cdprintf("Read_CDC_Host FIXME: Transfer data disabled");\r
cc68a136	189	return 0;\r
	190	}\r
	191	\r
	192	if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) \|\|\r
	193	(!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
	194	{\r
	195	// Wrong setting\r
fa1e5e29	196	cdprintf("Read_CDC_Host FIXME: Wrong setting");\r
cc68a136	197	return 0;\r
	198	}\r
	199	\r
	200	Pico_mcd->cdc.DBC.N -= 2;\r
	201	\r
	202	if (Pico_mcd->cdc.DBC.N <= 0)\r
	203	{\r
	204	Pico_mcd->cdc.DBC.N = 0;\r
c459aefd	205	Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
cc68a136	206	Pico_mcd->s68k_regs[4] \|= 0x80; // End data transfer\r
	207	Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
	208	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
	209	\r
	210	if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Transfer End Interrupt Enable ?\r
	211	{\r
	212	Pico_mcd->cdc.IFSTAT &= ~0x40;\r
	213	\r
	214	if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
	215	dprintf("m68k: s68k irq 5");\r
	216	SekInterruptS68k(5);\r
	217	}\r
	218	\r
c459aefd	219	cdprintf("CDC - DTE interrupt");\r
cc68a136	220	}\r
	221	}\r
	222	\r
	223	addr = Pico_mcd->cdc.DAC.N;\r
	224	Pico_mcd->cdc.DAC.N += 2;\r
c459aefd	225	\r
	226	cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
	227	(Pico_mcd->cdc.Buffer[addr]<<8) \| Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
	228	\r
cc68a136	229	return (Pico_mcd->cdc.Buffer[addr]<<8) \| Pico_mcd->cdc.Buffer[addr+1];\r
	230	\r
	231	#if 0\r
	232	__asm\r
	233	{\r
	234	mov esi, Pico_mcd->cdc.DAC.N\r
	235	lea ebx, Pico_mcd->cdc.Buffer\r
	236	// and esi, 0x3FFF\r
	237	mov ax, [ebx + esi]\r
	238	add esi, 2\r
	239	rol ax, 8\r
	240	mov Pico_mcd->cdc.DAC.N, esi\r
	241	mov val, ax\r
	242	}\r
	243	#endif\r
	244	}\r
	245	\r
	246	\r
	247	void CDC_Update_Header(void)\r
	248	{\r
	249	if (Pico_mcd->cdc.CTRL.B.B1 & 0x01) // Sub-Header wanted ?\r
	250	{\r
	251	Pico_mcd->cdc.HEAD.B.B0 = 0;\r
	252	Pico_mcd->cdc.HEAD.B.B1 = 0;\r
	253	Pico_mcd->cdc.HEAD.B.B2 = 0;\r
	254	Pico_mcd->cdc.HEAD.B.B3 = 0;\r
	255	}\r
	256	else\r
	257	{\r
	258	_msf MSF;\r
	259	\r
	260	LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
	261	\r
	262	Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
	263	Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
	264	Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
	265	Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
	266	}\r
	267	}\r
	268	\r
	269	\r
	270	unsigned char CDC_Read_Reg(void)\r
	271	{\r
	272	unsigned char ret;\r
	273	\r
cc68a136	274	switch(Pico_mcd->s68k_regs[5] & 0xF)\r
	275	{\r
	276	case 0x0: // COMIN\r
c459aefd	277	cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
cc68a136	278	\r
	279	Pico_mcd->s68k_regs[5] = 0x1;\r
	280	return Pico_mcd->cdc.COMIN;\r
	281	\r
	282	case 0x1: // IFSTAT\r
c459aefd	283	cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
cc68a136	284	\r
75736070	285	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 1); // Reg 1 (decoding)\r
cc68a136	286	Pico_mcd->s68k_regs[5] = 0x2;\r
	287	return Pico_mcd->cdc.IFSTAT;\r
	288	\r
	289	case 0x2: // DBCL\r
c459aefd	290	cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
cc68a136	291	\r
	292	Pico_mcd->s68k_regs[5] = 0x3;\r
	293	return Pico_mcd->cdc.DBC.B.L;\r
	294	\r
	295	case 0x3: // DBCH\r
c459aefd	296	cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
cc68a136	297	\r
	298	Pico_mcd->s68k_regs[5] = 0x4;\r
	299	return Pico_mcd->cdc.DBC.B.H;\r
	300	\r
	301	case 0x4: // HEAD0\r
c459aefd	302	cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
cc68a136	303	\r
75736070	304	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 4); // Reg 4 (decoding)\r
cc68a136	305	Pico_mcd->s68k_regs[5] = 0x5;\r
	306	return Pico_mcd->cdc.HEAD.B.B0;\r
	307	\r
	308	case 0x5: // HEAD1\r
c459aefd	309	cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
cc68a136	310	\r
75736070	311	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 5); // Reg 5 (decoding)\r
cc68a136	312	Pico_mcd->s68k_regs[5] = 0x6;\r
	313	return Pico_mcd->cdc.HEAD.B.B1;\r
	314	\r
	315	case 0x6: // HEAD2\r
c459aefd	316	cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
cc68a136	317	\r
75736070	318	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 6); // Reg 6 (decoding)\r
cc68a136	319	Pico_mcd->s68k_regs[5] = 0x7;\r
	320	return Pico_mcd->cdc.HEAD.B.B2;\r
	321	\r
	322	case 0x7: // HEAD3\r
c459aefd	323	cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
cc68a136	324	\r
75736070	325	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 7); // Reg 7 (decoding)\r
cc68a136	326	Pico_mcd->s68k_regs[5] = 0x8;\r
	327	return Pico_mcd->cdc.HEAD.B.B3;\r
	328	\r
	329	case 0x8: // PTL\r
c459aefd	330	cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
cc68a136	331	\r
75736070	332	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 8); // Reg 8 (decoding)\r
cc68a136	333	Pico_mcd->s68k_regs[5] = 0x9;\r
	334	return Pico_mcd->cdc.PT.B.L;\r
	335	\r
	336	case 0x9: // PTH\r
c459aefd	337	cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
cc68a136	338	\r
75736070	339	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 9); // Reg 9 (decoding)\r
cc68a136	340	Pico_mcd->s68k_regs[5] = 0xA;\r
	341	return Pico_mcd->cdc.PT.B.H;\r
	342	\r
	343	case 0xA: // WAL\r
c459aefd	344	cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
cc68a136	345	\r
	346	Pico_mcd->s68k_regs[5] = 0xB;\r
	347	return Pico_mcd->cdc.WA.B.L;\r
	348	\r
	349	case 0xB: // WAH\r
c459aefd	350	cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
cc68a136	351	\r
	352	Pico_mcd->s68k_regs[5] = 0xC;\r
	353	return Pico_mcd->cdc.WA.B.H;\r
	354	\r
	355	case 0xC: // STAT0\r
c459aefd	356	cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
cc68a136	357	\r
75736070	358	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 12); // Reg 12 (decoding)\r
cc68a136	359	Pico_mcd->s68k_regs[5] = 0xD;\r
	360	return Pico_mcd->cdc.STAT.B.B0;\r
	361	\r
	362	case 0xD: // STAT1\r
c459aefd	363	cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
cc68a136	364	\r
75736070	365	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 13); // Reg 13 (decoding)\r
cc68a136	366	Pico_mcd->s68k_regs[5] = 0xE;\r
	367	return Pico_mcd->cdc.STAT.B.B1;\r
	368	\r
	369	case 0xE: // STAT2\r
c459aefd	370	cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
cc68a136	371	\r
75736070	372	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 14); // Reg 14 (decoding)\r
cc68a136	373	Pico_mcd->s68k_regs[5] = 0xF;\r
	374	return Pico_mcd->cdc.STAT.B.B2;\r
	375	\r
	376	case 0xF: // STAT3\r
c459aefd	377	cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
cc68a136	378	\r
	379	ret = Pico_mcd->cdc.STAT.B.B3;\r
	380	Pico_mcd->cdc.IFSTAT \|= 0x20; // decoding interrupt flag cleared\r
	381	if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
	382	{\r
75736070	383	if ((Pico_mcd->cdc.Decode_Reg_Read & 0x73F2) == 0x73F2)\r
cc68a136	384	Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
	385	}\r
	386	return ret;\r
	387	}\r
	388	\r
	389	return 0;\r
	390	}\r
	391	\r
	392	\r
	393	void CDC_Write_Reg(unsigned char Data)\r
	394	{\r
c459aefd	395	cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
cc68a136	396	\r
	397	switch (Pico_mcd->s68k_regs[5] & 0xF)\r
	398	{\r
	399	case 0x0: // SBOUT\r
	400	Pico_mcd->s68k_regs[5] = 0x1;\r
	401	Pico_mcd->cdc.SBOUT = Data;\r
	402	\r
	403	break;\r
	404	\r
	405	case 0x1: // IFCTRL\r
	406	Pico_mcd->s68k_regs[5] = 0x2;\r
	407	Pico_mcd->cdc.IFCTRL = Data;\r
	408	\r
	409	if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0) // Stop data transfer\r
	410	{\r
	411	Pico_mcd->cdc.DBC.N = 0;\r
c459aefd	412	Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136	413	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
	414	}\r
	415	break;\r
	416	\r
	417	case 0x2: // DBCL\r
	418	Pico_mcd->s68k_regs[5] = 0x3;\r
	419	Pico_mcd->cdc.DBC.B.L = Data;\r
	420	\r
	421	break;\r
	422	\r
	423	case 0x3: // DBCH\r
	424	Pico_mcd->s68k_regs[5] = 0x4;\r
	425	Pico_mcd->cdc.DBC.B.H = Data;\r
	426	\r
	427	break;\r
	428	\r
	429	case 0x4: // DACL\r
	430	Pico_mcd->s68k_regs[5] = 0x5;\r
	431	Pico_mcd->cdc.DAC.B.L = Data;\r
	432	\r
	433	break;\r
	434	\r
	435	case 0x5: // DACH\r
	436	Pico_mcd->s68k_regs[5] = 0x6;\r
	437	Pico_mcd->cdc.DAC.B.H = Data;\r
	438	\r
	439	break;\r
	440	\r
	441	case 0x6: // DTTRG\r
	442	if (Pico_mcd->cdc.IFCTRL & 0x02) // Data transfer enable ?\r
	443	{\r
	444	Pico_mcd->cdc.IFSTAT &= ~0x08; // Data transfer in progress\r
c459aefd	445	Pico_mcd->scd.Status_CDC \|= 0x08; // Data transfer in progress\r
cc68a136	446	Pico_mcd->s68k_regs[4] &= 0x7F; // A data transfer start\r
cc68a136	447	\r
c459aefd	448	cdprintf("************ Starting Data Transfer *********");\r
cc68a136	449	cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
cb4a513a	450	Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) \| Pico_mcd->s68k_regs[0xB]);\r
cc68a136	451	}\r
	452	break;\r
	453	\r
	454	case 0x7: // DTACK\r
	455	Pico_mcd->cdc.IFSTAT \|= 0x40; // end data transfer interrupt flag cleared\r
	456	break;\r
	457	\r
	458	case 0x8: // WAL\r
	459	Pico_mcd->s68k_regs[5] = 0x9;\r
	460	Pico_mcd->cdc.WA.B.L = Data;\r
	461	\r
	462	break;\r
	463	\r
	464	case 0x9: // WAH\r
	465	Pico_mcd->s68k_regs[5] = 0xA;\r
	466	Pico_mcd->cdc.WA.B.H = Data;\r
	467	\r
	468	break;\r
	469	\r
	470	case 0xA: // CTRL0\r
	471	Pico_mcd->s68k_regs[5] = 0xB;\r
	472	Pico_mcd->cdc.CTRL.B.B0 = Data;\r
	473	\r
	474	break;\r
	475	\r
	476	case 0xB: // CTRL1\r
	477	Pico_mcd->s68k_regs[5] = 0xC;\r
	478	Pico_mcd->cdc.CTRL.B.B1 = Data;\r
	479	\r
	480	break;\r
	481	\r
	482	case 0xC: // PTL\r
	483	Pico_mcd->s68k_regs[5] = 0xD;\r
	484	Pico_mcd->cdc.PT.B.L = Data;\r
	485	\r
	486	break;\r
	487	\r
	488	case 0xD: // PTH\r
	489	Pico_mcd->s68k_regs[5] = 0xE;\r
	490	Pico_mcd->cdc.PT.B.H = Data;\r
	491	\r
	492	break;\r
	493	\r
	494	case 0xE: // CTRL2\r
	495	Pico_mcd->cdc.CTRL.B.B2 = Data;\r
	496	break;\r
	497	\r
	498	case 0xF: // RESET\r
	499	CDC_Reset();\r
	500	break;\r
	501	}\r
	502	}\r
	503	\r
	504	\r
	505	static int bswapwrite(int a, unsigned short d)\r
	506	{\r
	507	(unsigned short )(Pico_mcd->s68k_regs + a) = (d>>8)\|(d<<8);\r
	508	return d + (d >> 8);\r
	509	}\r
	510	\r
	511	void CDD_Export_Status(void)\r
	512	{\r
	513	unsigned int csum;\r
	514	\r
515	csum = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
516	csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
517	csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
518	csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
519	Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
520	csum += Pico_mcd->cdd.Ext;\r
521	Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
522	\r
672ad671	523	Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
cc68a136	524	\r
	525	if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
	526	{\r
	527	dprintf("cdd export irq 4");\r
	528	SekInterruptS68k(4);\r
	529	}\r
	530	\r
c459aefd	531	// cdprintf("CDD exported status\n");\r
c459aefd	532	cdprintf("out: Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136	533	(Pico_mcd->s68k_regs[0x38+0] << 8) \| Pico_mcd->s68k_regs[0x38+1],\r
	534	(Pico_mcd->s68k_regs[0x38+2] << 8) \| Pico_mcd->s68k_regs[0x38+3],\r
	535	(Pico_mcd->s68k_regs[0x38+4] << 8) \| Pico_mcd->s68k_regs[0x38+5],\r
	536	(Pico_mcd->s68k_regs[0x38+6] << 8) \| Pico_mcd->s68k_regs[0x38+7],\r
	537	(Pico_mcd->s68k_regs[0x38+8] << 8) \| Pico_mcd->s68k_regs[0x38+9]);\r
	538	}\r
	539	\r
	540	\r
	541	void CDD_Import_Command(void)\r
	542	{\r
c459aefd	543	// cdprintf("CDD importing command\n");\r
c459aefd	544	cdprintf("in: Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136	545	(Pico_mcd->s68k_regs[0x38+10+0] << 8) \| Pico_mcd->s68k_regs[0x38+10+1],\r
	546	(Pico_mcd->s68k_regs[0x38+10+2] << 8) \| Pico_mcd->s68k_regs[0x38+10+3],\r
	547	(Pico_mcd->s68k_regs[0x38+10+4] << 8) \| Pico_mcd->s68k_regs[0x38+10+5],\r
	548	(Pico_mcd->s68k_regs[0x38+10+6] << 8) \| Pico_mcd->s68k_regs[0x38+10+7],\r
	549	(Pico_mcd->s68k_regs[0x38+10+8] << 8) \| Pico_mcd->s68k_regs[0x38+10+9]);\r
	550	\r
	551	switch (Pico_mcd->s68k_regs[0x38+10+0])\r
	552	{\r
	553	case 0x0: // STATUS (?)\r
	554	Get_Status_CDD_c0();\r
	555	break;\r
	556	\r
	557	case 0x1: // STOP ALL (?)\r
	558	Stop_CDD_c1();\r
	559	break;\r
	560	\r
	561	case 0x2: // GET TOC INFORMATIONS\r
	562	switch(Pico_mcd->s68k_regs[0x38+10+3])\r
	563	{\r
	564	case 0x0: // get current position (MSF format)\r
	565	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
	566	Get_Pos_CDD_c20();\r
	567	break;\r
	568	\r
	569	case 0x1: // get elapsed time of current track played/scanned (relative MSF format)\r
	570	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 1;\r
	571	Get_Track_Pos_CDD_c21();\r
	572	break;\r
	573	\r
	574	case 0x2: // get current track in RS2-RS3\r
	575	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 2;\r
	576	Get_Current_Track_CDD_c22();\r
	577	break;\r
	578	\r
bf098bc5	579	case 0x3: // get total length (MSF format)\r
cc68a136	580	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 3;\r
	581	Get_Total_Lenght_CDD_c23();\r
	582	break;\r
	583	\r
	584	case 0x4: // first & last track number\r
	585	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 4;\r
	586	Get_First_Last_Track_CDD_c24();\r
	587	break;\r
	588	\r
	589	case 0x5: // get track addresse (MSF format)\r
	590	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 5;\r
	591	Get_Track_Adr_CDD_c25();\r
	592	break;\r
	593	\r
	594	default : // invalid, then we return status\r
	595	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 0xF;\r
	596	Get_Status_CDD_c0();\r
	597	break;\r
	598	}\r
	599	break;\r
	600	\r
	601	case 0x3: // READ\r
	602	Play_CDD_c3();\r
	603	break;\r
	604	\r
	605	case 0x4: // SEEK\r
	606	Seek_CDD_c4();\r
	607	break;\r
	608	\r
	609	case 0x6: // PAUSE/STOP\r
	610	Pause_CDD_c6();\r
	611	break;\r
	612	\r
	613	case 0x7: // RESUME\r
	614	Resume_CDD_c7();\r
	615	break;\r
	616	\r
	617	case 0x8: // FAST FOWARD\r
	618	Fast_Foward_CDD_c8();\r
	619	break;\r
	620	\r
	621	case 0x9: // FAST REWIND\r
	622	Fast_Rewind_CDD_c9();\r
	623	break;\r
	624	\r
	625	case 0xA: // RECOVER INITIAL STATE (?)\r
	626	CDD_cA();\r
	627	break;\r
	628	\r
	629	case 0xC: // CLOSE TRAY\r
	630	Close_Tray_CDD_cC();\r
	631	break;\r
	632	\r
	633	case 0xD: // OPEN TRAY\r
	634	Open_Tray_CDD_cD();\r
	635	break;\r
	636	\r
	637	default: // UNKNOWN\r
	638	CDD_Def();\r
	639	break;\r
	640	}\r
	641	}\r
	642	\r