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gfx chip faker, hint vector
[picodrive.git] / Pico / cd / Memory.c
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cc68a136 1// This is part of Pico Library\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4// (c) Copyright 2006 notaz, All rights reserved.\r
5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9// A68K no longer supported here\r
10\r
11//#define __debug_io\r
12\r
13#include "../PicoInt.h"\r
14\r
15#include "../sound/sound.h"\r
16#include "../sound/ym2612.h"\r
17#include "../sound/sn76496.h"\r
18\r
cb4a513a 19#include "gfx_cd.h"\r
20\r
cc68a136 21typedef unsigned char u8;\r
22typedef unsigned short u16;\r
23typedef unsigned int u32;\r
24\r
25//#define __debug_io\r
26//#define __debug_io2\r
d1df8786 27//#define rdprintf dprintf\r
28#define rdprintf(...)\r
cc68a136 29\r
30// -----------------------------------------------------------------\r
31\r
8c1952f0 32// extern m68ki_cpu_core m68ki_cpu;\r
cc68a136 33\r
34extern int counter75hz;\r
35\r
36\r
cb4a513a 37static u32 m68k_reg_read16(u32 a)\r
cc68a136 38{\r
39 u32 d=0;\r
40 a &= 0x3e;\r
672ad671 41 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);\r
cc68a136 42\r
43 switch (a) {\r
672ad671 44 case 0:\r
c459aefd 45 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens\r
672ad671 46 goto end;\r
cc68a136 47 case 2:\r
672ad671 48 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
bf098bc5 49 dprintf("m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
cc68a136 50 goto end;\r
c459aefd 51 case 4:\r
52 d = Pico_mcd->s68k_regs[4]<<8;\r
53 goto end;\r
54 case 6:\r
55 d = Pico_mcd->m.hint_vector;\r
56 goto end;\r
cc68a136 57 case 8:\r
cc68a136 58 d = Read_CDC_Host(0);\r
59 goto end;\r
c459aefd 60 case 0xA:\r
61 dprintf("m68k reserved read");\r
62 goto end;\r
cc68a136 63 case 0xC:\r
d1df8786 64 dprintf("m68k stopwatch timer read");\r
cc68a136 65 break;\r
66 }\r
67\r
cc68a136 68 if (a < 0x30) {\r
69 // comm flag/cmd/status (0xE-0x2F)\r
70 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
71 goto end;\r
72 }\r
73\r
74 dprintf("m68k_regs invalid read @ %02x", a);\r
75\r
76end:\r
77\r
672ad671 78 // dprintf("ret = %04x", d);\r
cc68a136 79 return d;\r
80}\r
81\r
cb4a513a 82static void m68k_reg_write8(u32 a, u32 d)\r
cc68a136 83{\r
84 a &= 0x3f;\r
672ad671 85 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);\r
cc68a136 86\r
87 switch (a) {\r
88 case 0:\r
672ad671 89 d &= 1;\r
cc68a136 90 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }\r
c459aefd 91 return;\r
cc68a136 92 case 1:\r
672ad671 93 d &= 3;\r
cc68a136 94 if (!(d&1)) PicoMCD |= 2; // reset pending, needed to be sure we fetch the right vectors on reset\r
c459aefd 95 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));\r
96 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);\r
97 if ((PicoMCD&2) && (d&3)==1) {\r
cc68a136 98 SekResetS68k(); // S68k comes out of RESET or BRQ state\r
99 PicoMCD&=~2;\r
672ad671 100 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);\r
cc68a136 101 }\r
c459aefd 102 Pico_mcd->m.busreq = d;\r
103 return;\r
672ad671 104 case 2:\r
105 Pico_mcd->s68k_regs[2] = d; // really use s68k side register\r
106 return;\r
cc68a136 107 case 3:\r
bf098bc5 108 dprintf("m68k_regs w3: %02x @%06x", (u8)d, SekPc);\r
672ad671 109 d &= 0xc2;\r
110 if ((Pico_mcd->s68k_regs[3]>>6) != ((d>>6)&3))\r
111 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
112 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);\r
113 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :\r
114 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));\r
115 d |= Pico_mcd->s68k_regs[3]&0x1d;\r
d0d47c5b 116 if (!(d & 4) && (d & 2)) d &= ~1; // return word RAM to s68k in 2M mode\r
672ad671 117 Pico_mcd->s68k_regs[3] = d; // really use s68k side register\r
118 return;\r
c459aefd 119 case 6:\r
120 *((char *)&Pico_mcd->m.hint_vector+1) = d;\r
d1df8786 121 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer\r
c459aefd 122 return;\r
123 case 7:\r
124 *(char *)&Pico_mcd->m.hint_vector = d;\r
d1df8786 125 Pico_mcd->bios[0x72] = d;\r
c459aefd 126 return;\r
cc68a136 127 case 0xe:\r
672ad671 128 //dprintf("m68k: comm flag: %02x", d);\r
cc68a136 129\r
672ad671 130 //dprintf("s68k @ %06x", SekPcS68k);\r
cc68a136 131\r
132 Pico_mcd->s68k_regs[0xe] = d;\r
c459aefd 133 return;\r
672ad671 134 }\r
135\r
136 if ((a&0xf0) == 0x10) {\r
cc68a136 137 Pico_mcd->s68k_regs[a] = d;\r
672ad671 138 return;\r
cc68a136 139 }\r
140\r
c459aefd 141 dprintf("m68k: invalid write? [%02x] %02x", a, d);\r
cc68a136 142}\r
143\r
144\r
145\r
cb4a513a 146static u32 s68k_reg_read16(u32 a)\r
cc68a136 147{\r
148 u32 d=0;\r
cc68a136 149\r
672ad671 150 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);\r
cc68a136 151\r
152 switch (a) {\r
153 case 0:\r
cb4a513a 154 d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state\r
c459aefd 155 goto end;\r
672ad671 156 case 2:\r
157 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0x1f);\r
bf098bc5 158 dprintf("s68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
672ad671 159 goto end;\r
cc68a136 160 case 6:\r
161 d = CDC_Read_Reg();\r
162 goto end;\r
163 case 8:\r
cb4a513a 164 d = Read_CDC_Host(1); // Gens returns 0 here on byte reads\r
cc68a136 165 goto end;\r
166 case 0xC:\r
d1df8786 167 dprintf("s68k stopwatch timer read");\r
168 break;\r
169 case 0x30:\r
170 dprintf("s68k int3 timer read");\r
cc68a136 171 break;\r
172 case 0x34: // fader\r
173 d = 0; // no busy bit\r
174 goto end;\r
175 }\r
176\r
177 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
178\r
179end:\r
180\r
672ad671 181 // dprintf("ret = %04x", d);\r
cc68a136 182\r
183 return d;\r
184}\r
185\r
cb4a513a 186static void s68k_reg_write8(u32 a, u32 d)\r
cc68a136 187{\r
672ad671 188 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);\r
cc68a136 189\r
190 // TODO: review against Gens\r
191 switch (a) {\r
672ad671 192 case 2:\r
193 return; // only m68k can change WP\r
194 case 3:\r
bf098bc5 195 dprintf("s68k_regs w3: %02x @%06x", (u8)d, SekPc);\r
672ad671 196 d &= 0x1d;\r
d0d47c5b 197 if (d&4) {\r
198 d |= Pico_mcd->s68k_regs[3]&0xc2;\r
199 if ((d ^ Pico_mcd->s68k_regs[3]) & 5) d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit\r
200 } else {\r
201 d |= Pico_mcd->s68k_regs[3]&0xc3;\r
202 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode\r
203 }\r
672ad671 204 break;\r
cc68a136 205 case 4:\r
206 dprintf("s68k CDC dest: %x", d&7);\r
207 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode\r
208 return;\r
209 case 5:\r
c459aefd 210 //dprintf("s68k CDC reg addr: %x", d&0xf);\r
cc68a136 211 break;\r
212 case 7:\r
213 CDC_Write_Reg(d);\r
214 return;\r
215 case 0xa:\r
216 dprintf("s68k set CDC dma addr");\r
217 break;\r
d1df8786 218 case 0xc:\r
219 dprintf("s68k set stopwatch timer");\r
220 break;\r
221 case 0x31:\r
222 dprintf("s68k set int3 timer");\r
223 break;\r
cc68a136 224 case 0x33: // IRQ mask\r
225 dprintf("s68k irq mask: %02x", d);\r
226 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {\r
227 CDD_Export_Status();\r
228 // counter75hz = 0; // ???\r
229 }\r
230 break;\r
231 case 0x34: // fader\r
232 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;\r
233 return;\r
672ad671 234 case 0x36:\r
235 return; // d/m bit is unsetable\r
236 case 0x37: {\r
237 u32 d_old = Pico_mcd->s68k_regs[0x37];\r
238 Pico_mcd->s68k_regs[0x37] = d&7;\r
239 if ((d&4) && !(d_old&4)) {\r
cc68a136 240 CDD_Export_Status();\r
241 // counter75hz = 0; // ???\r
242 }\r
672ad671 243 return;\r
244 }\r
cc68a136 245 case 0x4b:\r
246 Pico_mcd->s68k_regs[a] = (u8) d;\r
247 CDD_Import_Command();\r
248 return;\r
249 }\r
250\r
251 if ((a&0x1f0) == 0x10 || a == 0x0e || (a >= 0x38 && a < 0x42))\r
252 {\r
253 dprintf("m68k: invalid write @ %02x?", a);\r
254 return;\r
255 }\r
256\r
257 Pico_mcd->s68k_regs[a] = (u8) d;\r
258}\r
259\r
260\r
261\r
262\r
263\r
264static int PadRead(int i)\r
265{\r
266 int pad=0,value=0,TH;\r
267 pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU\r
268 TH=Pico.ioports[i+1]&0x40;\r
269\r
270 if(PicoOpt & 0x20) { // 6 button gamepad enabled\r
271 int phase = Pico.m.padTHPhase[i];\r
272\r
273 if(phase == 2 && !TH) {\r
274 value=(pad&0xc0)>>2; // ?0SA 0000\r
275 goto end;\r
276 } else if(phase == 3 && TH) {\r
277 value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r
278 goto end;\r
279 } else if(phase == 3 && !TH) {\r
280 value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r
281 goto end;\r
282 }\r
283 }\r
284\r
285 if(TH) value=(pad&0x3f); // ?1CB RLDU\r
286 else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
287\r
288 end:\r
289\r
290 // orr the bits, which are set as output\r
291 value |= Pico.ioports[i+1]&Pico.ioports[i+4];\r
292\r
293 return value; // will mirror later\r
294}\r
295\r
296static u8 z80Read8(u32 a)\r
297{\r
298 if(Pico.m.z80Run&1) return 0;\r
299\r
300 a&=0x1fff;\r
301\r
302 if(!(PicoOpt&4)) {\r
303 // Z80 disabled, do some faking\r
304 static u8 zerosent = 0;\r
305 if(a == Pico.m.z80_lastaddr) { // probably polling something\r
306 u8 d = Pico.m.z80_fakeval;\r
307 if((d & 0xf) == 0xf && !zerosent) {\r
308 d = 0; zerosent = 1;\r
309 } else {\r
310 Pico.m.z80_fakeval++;\r
311 zerosent = 0;\r
312 }\r
313 return d;\r
314 } else {\r
315 Pico.m.z80_fakeval = 0;\r
316 }\r
317 }\r
318\r
319 Pico.m.z80_lastaddr = (u16) a;\r
320 return Pico.zram[a];\r
321}\r
322\r
323\r
324// for nonstandard reads\r
325static u32 UnusualRead16(u32 a, int realsize)\r
326{\r
327 u32 d=0;\r
328\r
329 dprintf("unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);\r
330\r
331\r
332 dprintf("ret = %04x", d);\r
333 return d;\r
334}\r
335\r
336static u32 OtherRead16(u32 a, int realsize)\r
337{\r
338 u32 d=0;\r
339\r
340 if ((a&0xff0000)==0xa00000) {\r
341 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)\r
342 if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; goto end; } // 0x4000-0x5fff, Fudge if disabled\r
343 d=0xffff; goto end;\r
344 }\r
345 if ((a&0xffffe0)==0xa10000) { // I/O ports\r
346 a=(a>>1)&0xf;\r
347 switch(a) {\r
348 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)\r
349 case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;\r
350 case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;\r
351 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM\r
352 }\r
353 d|=d<<8;\r
354 goto end;\r
355 }\r
356 // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers\r
357 if (a==0xa11100) { d=((Pico.m.z80Run&1)<<8)|0x8000|Pico.m.rotate++; goto end; }\r
358\r
359 if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }\r
360\r
672ad671 361 if ((a&0xffffc0)==0xa12000) {\r
cb4a513a 362 d=m68k_reg_read16(a);\r
672ad671 363 goto end;\r
364 }\r
cc68a136 365\r
366 d = UnusualRead16(a, realsize);\r
367\r
368end:\r
369 return d;\r
370}\r
371\r
372//extern UINT32 mz80GetRegisterValue(void *, UINT32);\r
373\r
374static void OtherWrite8(u32 a,u32 d,int realsize)\r
375{\r
376 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound\r
377 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram\r
378 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound\r
379 if ((a&0xffffe0)==0xa10000) { // I/O ports\r
380 a=(a>>1)&0xf;\r
381 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
382 if(PicoOpt&0x20) {\r
383 if(a==1) {\r
384 Pico.m.padDelay[0] = 0;\r
385 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;\r
386 }\r
387 else if(a==2) {\r
388 Pico.m.padDelay[1] = 0;\r
389 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;\r
390 }\r
391 }\r
392 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM\r
393 return;\r
394 }\r
395 if (a==0xa11100) {\r
396 extern int z80startCycle, z80stopCycle;\r
397 //int lineCycles=(488-SekCyclesLeft)&0x1ff;\r
398 d&=1; d^=1;\r
399 if(!d) {\r
400 // hack: detect a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)\r
401 if((PicoOpt&4) && Pico.m.z80Run==1) z80_run(20);\r
402 z80stopCycle = SekCyclesDone();\r
403 //z80ExtraCycles += (lineCycles>>1)-(lineCycles>>5); // only meaningful in PicoFrameHints()\r
404 } else {\r
405 z80startCycle = SekCyclesDone();\r
406 //if(Pico.m.scanline != -1)\r
407 //z80ExtraCycles -= (lineCycles>>1)-(lineCycles>>5)+16;\r
408 }\r
409 //dprintf("set_zrun: %i [%i|%i] zPC=%04x @%06x", d, Pico.m.scanline, SekCyclesDone(), mz80GetRegisterValue(NULL, 0), SekPc);\r
410 Pico.m.z80Run=(u8)d; return;\r
411 }\r
412 if (a==0xa11200) { if(!(d&1)) z80_reset(); return; }\r
413\r
414 if ((a&0xff7f00)==0xa06000) // Z80 BANK register\r
415 {\r
416 Pico.m.z80_bank68k>>=1;\r
417 Pico.m.z80_bank68k|=(d&1)<<8;\r
418 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one\r
419 return;\r
420 }\r
421\r
422 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored\r
423\r
cb4a513a 424 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }\r
cc68a136 425\r
426 dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
427}\r
428\r
429static void OtherWrite16(u32 a,u32 d)\r
430{\r
431 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }\r
432 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)\r
433\r
434 if ((a&0xffffe0)==0xa10000) { // I/O ports\r
435 a=(a>>1)&0xf;\r
436 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
437 if(PicoOpt&0x20) {\r
438 if(a==1) {\r
439 Pico.m.padDelay[0] = 0;\r
440 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;\r
441 }\r
442 else if(a==2) {\r
443 Pico.m.padDelay[1] = 0;\r
444 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;\r
445 }\r
446 }\r
447 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM\r
448 return;\r
449 }\r
450 if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }\r
451 if (a==0xa11200) { if(!(d&0x100)) z80_reset(); return; }\r
452\r
453 OtherWrite8(a, d>>8, 16);\r
454 OtherWrite8(a+1,d&0xff, 16);\r
455}\r
456\r
457// -----------------------------------------------------------------\r
458// Read Rom and read Ram\r
459\r
460u8 PicoReadM68k8(u32 a)\r
461{\r
462 u32 d=0;\r
463\r
464 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram\r
465\r
466 a&=0xffffff;\r
467\r
468 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios\r
469\r
470 // prg RAM\r
471 if ((a&0xfe0000)==0x020000) {\r
672ad671 472 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 473 d = *(prg_bank+((a^1)&0x1ffff));\r
474 goto end;\r
475 }\r
476\r
d0d47c5b 477 // word RAM\r
478 if ((a&0xfc0000)==0x200000) {\r
479 dprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);\r
480 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 481 if (a >= 0x220000) {\r
482 dprintf("cell");\r
483 } else {\r
484 a=((a&0x1fffe)<<1)|(a&1);\r
485 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
486 d = Pico_mcd->word_ram[a^1];\r
487 }\r
d0d47c5b 488 } else {\r
489 // allow access in any mode, like Gens does\r
490 d = Pico_mcd->word_ram[(a^1)&0x3ffff];\r
491 }\r
492 dprintf("ret = %02x", (u8)d);\r
493 goto end;\r
494 }\r
495\r
cc68a136 496 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r
497\r
c459aefd 498 if ((a&0xffffc0)==0xa12000)\r
499 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);\r
672ad671 500\r
cc68a136 501 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;\r
502\r
c459aefd 503 if ((a&0xffffc0)==0xa12000)\r
504 rdprintf("ret = %02x", (u8)d);\r
672ad671 505\r
cc68a136 506 end:\r
507\r
508#ifdef __debug_io\r
509 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
510#endif\r
511 return (u8)d;\r
512}\r
513\r
ab0607f7 514\r
cc68a136 515u16 PicoReadM68k16(u32 a)\r
516{\r
517 u16 d=0;\r
518\r
519 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram\r
520\r
521 a&=0xfffffe;\r
522\r
523 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios\r
524\r
525 // prg RAM\r
526 if ((a&0xfe0000)==0x020000) {\r
672ad671 527 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 528 d = *(u16 *)(prg_bank+(a&0x1fffe));\r
529 goto end;\r
530 }\r
531\r
d0d47c5b 532 // word RAM\r
533 if ((a&0xfc0000)==0x200000) {\r
534 dprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);\r
535 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 536 if (a >= 0x220000) {\r
537 dprintf("cell");\r
538 } else {\r
539 a=((a&0x1fffe)<<1);\r
540 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
541 d = *(u16 *)(Pico_mcd->word_ram+a);\r
542 }\r
d0d47c5b 543 } else {\r
544 // allow access in any mode, like Gens does\r
545 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r
546 }\r
547 dprintf("ret = %04x", d);\r
548 goto end;\r
549 }\r
550\r
c459aefd 551 if ((a&0xffffc0)==0xa12000)\r
552 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);\r
672ad671 553\r
cc68a136 554 d = (u16)OtherRead16(a, 16);\r
555\r
c459aefd 556 if ((a&0xffffc0)==0xa12000)\r
557 rdprintf("ret = %04x", d);\r
672ad671 558\r
cc68a136 559 end:\r
560\r
561#ifdef __debug_io\r
562 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
563#endif\r
564 return d;\r
565}\r
566\r
ab0607f7 567\r
cc68a136 568u32 PicoReadM68k32(u32 a)\r
569{\r
570 u32 d=0;\r
571\r
572 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram\r
573\r
574 a&=0xfffffe;\r
575\r
576 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios\r
577\r
578 // prg RAM\r
579 if ((a&0xfe0000)==0x020000) {\r
672ad671 580 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 581 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r
582 d = (pm[0]<<16)|pm[1];\r
583 goto end;\r
584 }\r
585\r
d0d47c5b 586 // word RAM\r
587 if ((a&0xfc0000)==0x200000) {\r
588 dprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);\r
589 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 590 if (a >= 0x220000) {\r
591 dprintf("cell");\r
592 } else {\r
bf098bc5 593 a=((a&0x1fffe)<<1);\r
594 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
ab0607f7 595 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;\r
596 d |= *(u16 *)(Pico_mcd->word_ram+a+4);\r
bf098bc5 597 }\r
d0d47c5b 598 } else {\r
599 // allow access in any mode, like Gens does\r
600 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r
601 }\r
602 dprintf("ret = %08x", d);\r
603 goto end;\r
604 }\r
605\r
c459aefd 606 if ((a&0xffffc0)==0xa12000)\r
607 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);\r
672ad671 608\r
cc68a136 609 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
610\r
c459aefd 611 if ((a&0xffffc0)==0xa12000)\r
612 rdprintf("ret = %08x", d);\r
672ad671 613\r
cc68a136 614 end:\r
615#ifdef __debug_io\r
616 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
617#endif\r
618 return d;\r
619}\r
620\r
ab0607f7 621\r
cc68a136 622// -----------------------------------------------------------------\r
623// Write Ram\r
624\r
625void PicoWriteM68k8(u32 a,u8 d)\r
626{\r
627#ifdef __debug_io\r
628 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
629#endif\r
630 //if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
631 // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
632\r
633\r
ab0607f7 634 if ((a&0xe00000)==0xe00000) { // Ram\r
635 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;\r
636 return;\r
637 }\r
cc68a136 638\r
639 a&=0xffffff;\r
640\r
641 // prg RAM\r
642 if ((a&0xfe0000)==0x020000) {\r
672ad671 643 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
bf098bc5 644 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;\r
cc68a136 645 return;\r
646 }\r
647\r
d0d47c5b 648 // word RAM\r
649 if ((a&0xfc0000)==0x200000) {\r
650 dprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);\r
651 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 652 if (a >= 0x220000) {\r
653 dprintf("cell");\r
654 } else {\r
655 a=((a&0x1fffe)<<1)|(a&1);\r
656 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
657 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;\r
658 }\r
d0d47c5b 659 } else {\r
660 // allow access in any mode, like Gens does\r
bf098bc5 661 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;\r
d0d47c5b 662 }\r
663 return;\r
664 }\r
665\r
c459aefd 666 if ((a&0xffffc0)==0xa12000)\r
667 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);\r
672ad671 668\r
cc68a136 669 OtherWrite8(a,d,8);\r
670}\r
671\r
ab0607f7 672\r
cc68a136 673void PicoWriteM68k16(u32 a,u16 d)\r
674{\r
675#ifdef __debug_io\r
676 dprintf("w16: %06x, %04x", a&0xffffff, d);\r
677#endif\r
cc68a136 678 // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
679\r
ab0607f7 680 if ((a&0xe00000)==0xe00000) { // Ram\r
681 *(u16 *)(Pico.ram+(a&0xfffe))=d;\r
682 return;\r
683 }\r
cc68a136 684\r
685 a&=0xfffffe;\r
686\r
687 // prg RAM\r
688 if ((a&0xfe0000)==0x020000) {\r
672ad671 689 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 690 *(u16 *)(prg_bank+(a&0x1fffe))=d;\r
691 return;\r
692 }\r
693\r
d0d47c5b 694 // word RAM\r
695 if ((a&0xfc0000)==0x200000) {\r
696 dprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);\r
697 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 698 if (a >= 0x220000) {\r
699 dprintf("cell");\r
700 } else {\r
701 a=((a&0x1fffe)<<1);\r
702 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
703 *(u16 *)(Pico_mcd->word_ram+a)=d;\r
704 }\r
d0d47c5b 705 } else {\r
706 // allow access in any mode, like Gens does\r
707 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;\r
708 }\r
709 return;\r
710 }\r
711\r
c459aefd 712 if ((a&0xffffc0)==0xa12000)\r
713 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);\r
cc68a136 714\r
715 OtherWrite16(a,d);\r
716}\r
717\r
ab0607f7 718\r
cc68a136 719void PicoWriteM68k32(u32 a,u32 d)\r
720{\r
721#ifdef __debug_io\r
722 dprintf("w32: %06x, %08x", a&0xffffff, d);\r
723#endif\r
724\r
725 if ((a&0xe00000)==0xe00000)\r
726 {\r
727 // Ram:\r
728 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r
729 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
730 return;\r
731 }\r
732\r
733 a&=0xfffffe;\r
734\r
735 // prg RAM\r
736 if ((a&0xfe0000)==0x020000) {\r
672ad671 737 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 738 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r
739 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
740 return;\r
741 }\r
742\r
672ad671 743 // word RAM\r
d0d47c5b 744 if ((a&0xfc0000)==0x200000) {\r
745 if (d != 0) // don't log clears\r
746 dprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);\r
747 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
bf098bc5 748 if (a >= 0x220000) {\r
749 dprintf("cell");\r
750 } else {\r
bf098bc5 751 a=((a&0x1fffe)<<1);\r
752 if (Pico_mcd->s68k_regs[3]&1) a+=2;\r
ab0607f7 753 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;\r
754 *(u16 *)(Pico_mcd->word_ram+a+4) = d;\r
bf098bc5 755 }\r
d0d47c5b 756 } else {\r
757 // allow access in any mode, like Gens does\r
758 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r
759 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
760 }\r
672ad671 761 return;\r
d0d47c5b 762 }\r
672ad671 763\r
c459aefd 764 if ((a&0xffffc0)==0xa12000)\r
765 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);\r
cc68a136 766\r
ab0607f7 767#if 0\r
768 if ((a&0x3f) == 0x1c && SekPc == 0xffff05ba)\r
769 {\r
770 int i;\r
771 FILE *ff;\r
772 unsigned short *ram = (unsigned short *) Pico.ram;\r
773 // unswap and dump RAM\r
774 for (i = 0; i < 0x10000/2; i++)\r
775 ram[i] = (ram[i]>>8) | (ram[i]<<8);\r
776 ff = fopen("ram.bin", "wb");\r
777 fwrite(ram, 1, 0x10000, ff);\r
778 fclose(ff);\r
779 exit(0);\r
780 }\r
781#endif\r
782\r
cc68a136 783 OtherWrite16(a, (u16)(d>>16));\r
784 OtherWrite16(a+2,(u16)d);\r
785}\r
786\r
787\r
788// -----------------------------------------------------------------\r
789\r
790\r
791u8 PicoReadS68k8(u32 a)\r
792{\r
793 u32 d=0;\r
794\r
795 a&=0xffffff;\r
796\r
797 // prg RAM\r
798 if (a < 0x80000) {\r
799 d = *(Pico_mcd->prg_ram+(a^1));\r
800 goto end;\r
801 }\r
802\r
803 // regs\r
804 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 805 a &= 0x1ff;\r
806 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);\r
807 if (a >= 0x50 && a < 0x68)\r
808 d = gfx_cd_read(a&~1);\r
809 else d = s68k_reg_read16(a&~1);\r
810 if ((a&1)==0) d>>=8;\r
c459aefd 811 rdprintf("ret = %02x", (u8)d);\r
cc68a136 812 goto end;\r
813 }\r
814\r
d0d47c5b 815 // word RAM (2M area)\r
816 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
817 dprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPc);\r
818 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
819 // TODO (decode)\r
820 dprintf("(decode)");\r
821 } else {\r
822 // allow access in any mode, like Gens does\r
823 d = Pico_mcd->word_ram[(a^1)&0x3ffff];\r
824 }\r
825 dprintf("ret = %02x", (u8)d);\r
826 goto end;\r
827 }\r
828\r
829 // word RAM (1M area)\r
830 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
831 dprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPc);\r
bf098bc5 832 a=((a&0x1fffe)<<1)|(a&1);\r
833 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
834 d = Pico_mcd->word_ram[a^1];\r
835 dprintf("ret = %02x", (u8)d);\r
d0d47c5b 836 goto end;\r
837 }\r
838\r
ab0607f7 839 // bram\r
840 if ((a&0xff0000)==0xfe0000) {\r
841 d = Pico_mcd->bram[(a>>1)&0x1fff];\r
842 goto end;\r
843 }\r
844\r
cc68a136 845 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
846\r
847 end:\r
848\r
849#ifdef __debug_io2\r
850 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
851#endif\r
852 return (u8)d;\r
853}\r
854\r
ab0607f7 855\r
cc68a136 856u16 PicoReadS68k16(u32 a)\r
857{\r
858 u16 d=0;\r
859\r
860 a&=0xfffffe;\r
861\r
862 // prg RAM\r
863 if (a < 0x80000) {\r
864 d = *(u16 *)(Pico_mcd->prg_ram+a);\r
865 goto end;\r
866 }\r
867\r
868 // regs\r
869 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 870 a &= 0x1fe;\r
871 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);\r
872 if (a >= 0x50 && a < 0x68)\r
873 d = gfx_cd_read(a);\r
874 else d = s68k_reg_read16(a);\r
c459aefd 875 rdprintf("ret = %04x", d);\r
cc68a136 876 goto end;\r
877 }\r
878\r
d0d47c5b 879 // word RAM (2M area)\r
880 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
881 dprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPc);\r
882 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
883 // TODO (decode)\r
884 dprintf("(decode)");\r
885 } else {\r
886 // allow access in any mode, like Gens does\r
887 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r
888 }\r
ab0607f7 889 dprintf("ret = %04x", d);\r
d0d47c5b 890 goto end;\r
891 }\r
892\r
893 // word RAM (1M area)\r
894 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
895 dprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPc);\r
bf098bc5 896 a=((a&0x1fffe)<<1);\r
897 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
898 d = *(u16 *)(Pico_mcd->word_ram+a);\r
ab0607f7 899 dprintf("ret = %04x", d);\r
900 goto end;\r
901 }\r
902\r
903 // bram\r
904 if ((a&0xff0000)==0xfe0000) {\r
905 dprintf("s68k_bram r16: [%06x] @%06x", a, SekPc);\r
906 a = (a>>1)&0x1fff;\r
907 d = Pico_mcd->bram[a++]; // Gens does little endian here, an so do we..\r
908 d|= Pico_mcd->bram[a++] << 8;\r
909 dprintf("ret = %04x", d);\r
d0d47c5b 910 goto end;\r
911 }\r
912\r
cc68a136 913 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
914\r
915 end:\r
916\r
917#ifdef __debug_io2\r
918 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
919#endif\r
920 return d;\r
921}\r
922\r
ab0607f7 923\r
cc68a136 924u32 PicoReadS68k32(u32 a)\r
925{\r
926 u32 d=0;\r
927\r
928 a&=0xfffffe;\r
929\r
930 // prg RAM\r
931 if (a < 0x80000) {\r
932 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r
933 d = (pm[0]<<16)|pm[1];\r
934 goto end;\r
935 }\r
936\r
937 // regs\r
938 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 939 a &= 0x1fe;\r
940 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);\r
941 if (a >= 0x50 && a < 0x68)\r
942 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);\r
943 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);\r
c459aefd 944 rdprintf("ret = %08x", d);\r
cc68a136 945 goto end;\r
946 }\r
947\r
d0d47c5b 948 // word RAM (2M area)\r
949 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
950 dprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPc);\r
951 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
952 // TODO (decode)\r
953 dprintf("(decode)");\r
954 } else {\r
955 // allow access in any mode, like Gens does\r
956 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r
957 }\r
ab0607f7 958 dprintf("ret = %08x", d);\r
d0d47c5b 959 goto end;\r
960 }\r
961\r
962 // word RAM (1M area)\r
963 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
ab0607f7 964 dprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPc);\r
bf098bc5 965 a=((a&0x1fffe)<<1);\r
966 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
ab0607f7 967 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;\r
968 d |= *(u16 *)(Pico_mcd->word_ram+a+4);\r
969 dprintf("ret = %08x", d);\r
970 goto end;\r
971 }\r
972\r
973 // bram\r
974 if ((a&0xff0000)==0xfe0000) {\r
975 dprintf("s68k_bram r32: [%06x] @%06x", a, SekPc);\r
976 a = (a>>1)&0x1fff;\r
977 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..\r
978 d|= Pico_mcd->bram[a++] << 24;\r
979 d|= Pico_mcd->bram[a++];\r
980 d|= Pico_mcd->bram[a++] << 8;\r
981 dprintf("ret = %08x", d);\r
d0d47c5b 982 goto end;\r
983 }\r
984\r
cc68a136 985 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
986\r
987 end:\r
988\r
989#ifdef __debug_io2\r
990 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
991#endif\r
992 return d;\r
993}\r
994\r
ab0607f7 995\r
cc68a136 996// -----------------------------------------------------------------\r
997\r
998void PicoWriteS68k8(u32 a,u8 d)\r
999{\r
1000#ifdef __debug_io2\r
1001 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r
1002#endif\r
1003\r
1004 a&=0xffffff;\r
1005\r
1006 // prg RAM\r
1007 if (a < 0x80000) {\r
1008 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));\r
1009 *pm=d;\r
1010 return;\r
1011 }\r
1012\r
672ad671 1013 if (a != 0xff0011 && (a&0xff8000) == 0xff0000) // PCM hack\r
1014 return;\r
1015\r
cc68a136 1016 // regs\r
1017 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1018 a &= 0x1ff;\r
1019 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);\r
1020 if (a >= 0x50 && a < 0x68)\r
1021 gfx_cd_write(a&~1, (d<<8)|d);\r
1022 else s68k_reg_write8(a,d);\r
cc68a136 1023 return;\r
1024 }\r
1025\r
d0d47c5b 1026 // word RAM (2M area)\r
1027 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1028 dprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPc);\r
1029 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
1030 // TODO (decode)\r
1031 dprintf("(decode)");\r
1032 } else {\r
1033 // allow access in any mode, like Gens does\r
bf098bc5 1034 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;\r
d0d47c5b 1035 }\r
1036 return;\r
1037 }\r
1038\r
1039 // word RAM (1M area)\r
1040 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1041 if (d)\r
1042 dprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPc);\r
bf098bc5 1043 a=((a&0x1fffe)<<1)|(a&1);\r
1044 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
1045 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;\r
d0d47c5b 1046 return;\r
1047 }\r
1048\r
ab0607f7 1049 // bram\r
1050 if ((a&0xff0000)==0xfe0000) {\r
1051 Pico_mcd->bram[(a>>1)&0x1fff] = d;\r
1052 SRam.changed = 1;\r
1053 return;\r
1054 }\r
1055\r
cc68a136 1056 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r
1057}\r
1058\r
ab0607f7 1059\r
cc68a136 1060void PicoWriteS68k16(u32 a,u16 d)\r
1061{\r
1062#ifdef __debug_io2\r
1063 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
1064#endif\r
1065\r
1066 a&=0xfffffe;\r
1067\r
1068 // prg RAM\r
1069 if (a < 0x80000) {\r
1070 *(u16 *)(Pico_mcd->prg_ram+a)=d;\r
1071 return;\r
1072 }\r
1073\r
1074 // regs\r
1075 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1076 a &= 0x1fe;\r
1077 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);\r
1078 if (a >= 0x50 && a < 0x68)\r
1079 gfx_cd_write(a, d);\r
1080 else {\r
1081 s68k_reg_write8(a, d>>8);\r
1082 s68k_reg_write8(a+1,d&0xff);\r
1083 }\r
cc68a136 1084 return;\r
1085 }\r
1086\r
d0d47c5b 1087 // word RAM (2M area)\r
1088 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1089 dprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPc);\r
1090 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
1091 // TODO (decode)\r
1092 dprintf("(decode)");\r
1093 } else {\r
1094 // allow access in any mode, like Gens does\r
1095 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;\r
1096 }\r
1097 return;\r
1098 }\r
1099\r
1100 // word RAM (1M area)\r
1101 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1102 if (d)\r
1103 dprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPc);\r
bf098bc5 1104 a=((a&0x1fffe)<<1);\r
1105 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
1106 *(u16 *)(Pico_mcd->word_ram+a)=d;\r
d0d47c5b 1107 return;\r
1108 }\r
1109\r
ab0607f7 1110 // bram\r
1111 if ((a&0xff0000)==0xfe0000) {\r
1112 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPc);\r
1113 a = (a>>1)&0x1fff;\r
1114 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..\r
1115 Pico_mcd->bram[a++] = d >> 8;\r
1116 SRam.changed = 1;\r
1117 return;\r
1118 }\r
1119\r
cc68a136 1120 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
1121}\r
1122\r
ab0607f7 1123\r
cc68a136 1124void PicoWriteS68k32(u32 a,u32 d)\r
1125{\r
1126#ifdef __debug_io2\r
1127 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
1128#endif\r
1129\r
1130 a&=0xfffffe;\r
1131\r
1132 // prg RAM\r
1133 if (a < 0x80000) {\r
1134 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r
1135 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1136 return;\r
1137 }\r
1138\r
1139 // regs\r
1140 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1141 a &= 0x1fe;\r
1142 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);\r
1143 if (a >= 0x50 && a < 0x68) {\r
1144 gfx_cd_write(a, d>>16);\r
1145 gfx_cd_write(a+2, d&0xffff);\r
1146 } else {\r
1147 s68k_reg_write8(a, d>>24);\r
1148 s68k_reg_write8(a+1,(d>>16)&0xff);\r
1149 s68k_reg_write8(a+2,(d>>8) &0xff);\r
1150 s68k_reg_write8(a+3, d &0xff);\r
1151 }\r
cc68a136 1152 return;\r
1153 }\r
1154\r
d0d47c5b 1155 // word RAM (2M area)\r
1156 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
1157 dprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPc);\r
1158 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
1159 // TODO (decode)\r
1160 dprintf("(decode)");\r
1161 } else {\r
1162 // allow access in any mode, like Gens does\r
1163 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r
1164 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1165 }\r
1166 return;\r
1167 }\r
1168\r
1169 // word RAM (1M area)\r
1170 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1171 if (d)\r
1172 dprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPc);\r
bf098bc5 1173 a=((a&0x1fffe)<<1);\r
1174 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r
ab0607f7 1175 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;\r
1176 *(u16 *)(Pico_mcd->word_ram+a+4) = d;\r
d0d47c5b 1177 return;\r
1178 }\r
ab0607f7 1179\r
1180 // bram\r
1181 if ((a&0xff0000)==0xfe0000) {\r
1182 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPc);\r
1183 a = (a>>1)&0x1fff;\r
1184 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?\r
1185 Pico_mcd->bram[a++] = d >> 24;\r
1186 Pico_mcd->bram[a++] = d;\r
1187 Pico_mcd->bram[a++] = d >> 8;\r
1188 SRam.changed = 1;\r
1189 return;\r
1190 }\r
1191\r
cc68a136 1192 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
1193}\r
1194\r
1195\r
1196\r
1197// -----------------------------------------------------------------\r
1198\r
1199#ifdef EMU_M68K\r
1200unsigned char PicoReadCD8w (unsigned int a) {\r
1201 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k8(a) : PicoReadM68k8(a);\r
1202}\r
1203unsigned short PicoReadCD16w(unsigned int a) {\r
1204 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k16(a) : PicoReadM68k16(a);\r
1205}\r
1206unsigned int PicoReadCD32w(unsigned int a) {\r
1207 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k32(a) : PicoReadM68k32(a);\r
1208}\r
1209void PicoWriteCD8w (unsigned int a, unsigned char d) {\r
1210 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);\r
1211}\r
1212void PicoWriteCD16w(unsigned int a, unsigned short d) {\r
1213 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);\r
1214}\r
1215void PicoWriteCD32w(unsigned int a, unsigned int d) {\r
1216 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);\r
1217}\r
1218\r
1219// these are allowed to access RAM\r
1220unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {\r
1221 a&=0xffffff;\r
1222 if(m68ki_cpu_p == &PicoS68kCPU) {\r
1223 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram\r
1224 else dprintf("s68k read_pcrel8 @ %06x", a);\r
1225 } else {\r
1226 if(a<Pico.romsize) return *(u8 *)(Pico.rom+(a^1)); // Rom\r
1227 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
1228 }\r
1229 return 0;//(u8) lastread_d;\r
1230}\r
1231unsigned int m68k_read_pcrelative_CD16(unsigned int a) {\r
1232 a&=0xffffff;\r
1233 if(m68ki_cpu_p == &PicoS68kCPU) {\r
1234 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram\r
1235 else dprintf("s68k read_pcrel16 @ %06x", a);\r
1236 } else {\r
1237 if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
1238 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
1239 }\r
1240 return 0;//(u16) lastread_d;\r
1241}\r
1242unsigned int m68k_read_pcrelative_CD32(unsigned int a) {\r
1243 a&=0xffffff;\r
1244 if(m68ki_cpu_p == &PicoS68kCPU) {\r
1245 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram\r
1246 else dprintf("s68k read_pcrel32 @ %06x", a);\r
1247 } else {\r
1248 if(a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
1249 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
1250 }\r
1251 return 0; //lastread_d;\r
1252}\r
1253#endif // EMU_M68K\r
1254\r
fast MegaDrive/MegaCD/32X emulator