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optimizations, bugfixes, uae works (but with timing glitches?)
[picodrive.git] / cpu / Cyclone / OpBranch.cpp
CommitLineData
cc68a136 1\r
2#include "app.h"\r
3\r
cfb3dfa0 4static void CheckPc(int reg)\r
cc68a136 5{\r
cfb3dfa0 6#if USE_CHECKPC_CALLBACK\r
ee5e024c 7 ot(";@ Check Memory Base+pc (r%i)\n",reg);\r
cfb3dfa0 8 if (reg != 0)\r
9 ot(" mov r0,r%i\n", reg);\r
10 ot(" mov lr,pc\n");\r
cc68a136 11 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
12 ot(" mov r4,r0\n");\r
cfb3dfa0 13#else\r
1c88b865 14 ot(" bic r4,r%d,#1\n",reg); // we do not emulate address errors\r
cfb3dfa0 15#endif\r
cc68a136 16 ot("\n");\r
17}\r
cc68a136 18\r
19// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
20void OpPush32()\r
21{\r
22 ot(";@ Push r1 onto stack\n");\r
23 ot(" ldr r0,[r7,#0x3c]\n");\r
24 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
25 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
26 MemHandler(1,2);\r
27 ot("\n");\r
28}\r
29\r
30// Push SR - trashes r0-r3,r12,lr\r
31void OpPushSr(int high)\r
32{\r
33 ot(";@ Push SR:\n");\r
34 OpFlagsToReg(high);\r
35 ot(" ldr r0,[r7,#0x3c]\n");\r
36 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
37 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
38 MemHandler(1,1);\r
39 ot("\n");\r
40}\r
41\r
42// Pop SR - trashes r0-r3\r
43static void PopSr(int high)\r
44{\r
45 ot(";@ Pop SR:\n");\r
46 ot(" ldr r0,[r7,#0x3c]\n");\r
47 ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r
48 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
49 MemHandler(0,1);\r
50 ot("\n");\r
51 OpRegToFlags(high);\r
52}\r
53\r
54// Pop PC - assumes r10=Memory Base - trashes r0-r3\r
55static void PopPc()\r
56{\r
57 ot(";@ Pop PC:\n");\r
58 ot(" ldr r0,[r7,#0x3c]\n");\r
59 ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
60 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
61 MemHandler(0,2);\r
cfb3dfa0 62 ot(" add r0,r0,r10 ;@ Memory Base+PC\n");\r
cc68a136 63 ot("\n");\r
cfb3dfa0 64 CheckPc(0);\r
cc68a136 65}\r
66\r
67int OpTrap(int op)\r
68{\r
69 int use=0;\r
70\r
71 use=op&~0xf;\r
72 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
73\r
a6785576 74 OpStart(op,0x10);\r
cc68a136 75 ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
76 ot(" orr r0,r0,#0x20\n");\r
77 ot(" mov r0,r0,asl #2\n");\r
78 ot(" bl Exception\n");\r
79 ot("\n");\r
80\r
cfb3dfa0 81 Cycles=38; OpEnd(0x10);\r
cc68a136 82\r
83 return 0;\r
84}\r
85\r
86// --------------------- Opcodes 0x4e50+ ---------------------\r
87int OpLink(int op)\r
88{\r
89 int use=0,reg;\r
90\r
91 use=op&~7;\r
92 reg=op&7;\r
93 if (reg==7) use=op;\r
94 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
95\r
a6785576 96 OpStart(op,0x10);\r
cc68a136 97\r
98 if(reg!=7) {\r
99 ot(";@ Get An\n");\r
100 EaCalc(10, 7, 8, 2, 1);\r
101 EaRead(10, 1, 8, 2, 7, 1);\r
102 }\r
103\r
104 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
105 ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
106 ot(" mov r11,r0\n");\r
107 if(reg==7) ot(" mov r1,r0\n");\r
108 ot("\n");\r
109 \r
110 ot(";@ Write An to Stack\n");\r
111 MemHandler(1,2);\r
112\r
113 ot(";@ Save to An\n");\r
114 if(reg!=7)\r
115 EaWrite(10,11, 8, 2, 7, 1);\r
116\r
117 ot(";@ Get offset:\n");\r
118 EaCalc(0,0,0x3c,1);\r
119 EaRead(0,0,0x3c,1,0);\r
120\r
121 ot(" add r11,r11,r0 ;@ Add offset to A7\n");\r
122 ot(" str r11,[r7,#0x3c]\n");\r
123 ot("\n");\r
124\r
125 Cycles=16;\r
cfb3dfa0 126 OpEnd(0x10);\r
cc68a136 127 return 0;\r
128}\r
129\r
130// --------------------- Opcodes 0x4e58+ ---------------------\r
131int OpUnlk(int op)\r
132{\r
133 int use=0;\r
134\r
135 use=op&~7;\r
136 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
137\r
a6785576 138 OpStart(op,0x10);\r
cc68a136 139\r
140 ot(";@ Get An\n");\r
85a36a57 141 EaCalc(10, 0xf, 8, 2, 1);\r
142 EaRead(10, 0, 8, 2, 0xf, 1);\r
cc68a136 143\r
144 ot(" add r11,r0,#4 ;@ A7+=4\n");\r
145 ot("\n");\r
146 ot(";@ Pop An from stack:\n");\r
147 MemHandler(0,2);\r
148 ot("\n");\r
149 ot(" str r11,[r7,#0x3c] ;@ Save A7\n");\r
150 ot("\n");\r
151 ot(";@ An = value from stack:\n");\r
152 EaWrite(10, 0, 8, 2, 7, 1);\r
85a36a57 153\r
cc68a136 154 Cycles=12;\r
cfb3dfa0 155 OpEnd(0x10);\r
cc68a136 156 return 0;\r
157}\r
158\r
159// --------------------- Opcodes 0x4e70+ ---------------------\r
03c5768c 160// 01001110 01110ttt\r
cc68a136 161int Op4E70(int op)\r
162{\r
163 int type=0;\r
164\r
03c5768c 165 type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
cc68a136 166\r
167 switch (type)\r
168 {\r
169 case 1: // nop\r
170 OpStart(op);\r
171 Cycles=4;\r
172 OpEnd();\r
173 return 0;\r
174\r
a6785576 175 case 3: // rte\r
ee5e024c 176 OpStart(op,0x10,0,0,1); Cycles=20;\r
cc68a136 177 PopSr(1);\r
178 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
179 PopPc();\r
a6785576 180 SuperChange(op);\r
ee5e024c 181 OpEnd(0x10,0,0,1);\r
cc68a136 182 return 0;\r
183\r
184 case 5: // rts\r
a6785576 185 OpStart(op,0x10); Cycles=16;\r
cc68a136 186 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
187 PopPc();\r
cfb3dfa0 188 OpEnd(0x10);\r
cc68a136 189 return 0;\r
190\r
191 case 6: // trapv\r
ee5e024c 192 OpStart(op,0x10,0,1); Cycles=4;\r
cc68a136 193 ot(" tst r9,#0x10000000\n");\r
1c88b865 194 ot(" subne r5,r5,#%i\n",34);\r
cc68a136 195 ot(" movne r0,#0x1c ;@ TRAPV exception\n");\r
196 ot(" blne Exception\n");\r
ee5e024c 197 OpEnd(0x10,0,1);\r
cc68a136 198 return 0;\r
199\r
200 case 7: // rtr\r
a6785576 201 OpStart(op,0x10); Cycles=20;\r
cc68a136 202 PopSr(0);\r
203 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
204 PopPc();\r
cfb3dfa0 205 OpEnd(0x10);\r
cc68a136 206 return 0;\r
207\r
208 default:\r
209 return 1;\r
210 }\r
211}\r
212\r
213// --------------------- Opcodes 0x4e80+ ---------------------\r
214// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
215int OpJsr(int op)\r
216{\r
217 int use=0;\r
218 int sea=0;\r
219\r
220 sea=op&0x003f;\r
221\r
222 // See if we can do this opcode:\r
223 if (EaCanRead(sea,-1)==0) return 1;\r
224\r
85a36a57 225 use=OpBase(op,0);\r
cc68a136 226 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
227\r
cfb3dfa0 228 OpStart(op,(op&0x40)?0:0x10);\r
cc68a136 229\r
230 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
231 ot("\n");\r
cfb3dfa0 232 EaCalc(11,0x003f,sea,0);\r
cc68a136 233\r
ee5e024c 234 if (!(op&0x40))\r
cc68a136 235 {\r
236 ot(";@ Jsr - Push old PC first\n");\r
cc68a136 237 ot(" ldr r0,[r7,#0x3c]\n");\r
547045e3 238 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
cc68a136 239 ot(";@ Push r1 onto stack\n");\r
240 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
241 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
242 MemHandler(1,2);\r
cc68a136 243 }\r
ee5e024c 244 ot(";@ Jump - Get new PC from r11\n");\r
245 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
246 ot("\n");\r
cc68a136 247\r
cfb3dfa0 248 CheckPc(0);\r
cc68a136 249\r
250 Cycles=(op&0x40) ? 4 : 12;\r
251 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
252\r
cfb3dfa0 253 OpEnd((op&0x40)?0:0x10);\r
cc68a136 254\r
255 return 0;\r
256}\r
257\r
258// --------------------- Opcodes 0x50c8+ ---------------------\r
259\r
260// ARM version of 68000 condition codes:\r
261static char *Cond[16]=\r
262{\r
263 "", "", "hi","ls","cc","cs","ne","eq",\r
264 "vc","vs","pl","mi","ge","lt","gt","le"\r
265};\r
266\r
267// Emit a Dbra opcode, 0101cccc 11001nnn vv\r
268int OpDbra(int op)\r
269{\r
270 int use=0;\r
271 int cc=0;\r
272\r
273 use=op&~7; // Use same handler\r
274 cc=(op>>8)&15;\r
275 \r
276 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
277 OpStart(op);\r
278\r
3a5e6cf8 279 switch (cc)\r
cc68a136 280 {\r
3a5e6cf8 281 case 0: // T\r
282 case 1: // F\r
283 break;\r
284 case 2: // hi\r
285 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
85a36a57 286 ot(" beq DbraTrue\n\n");\r
3a5e6cf8 287 break;\r
288 case 3: // ls\r
289 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
85a36a57 290 ot(" bne DbraTrue\n\n");\r
3a5e6cf8 291 break;\r
292 default:\r
293 ot(";@ Is the condition true?\n");\r
294 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
295 ot(";@ If so, don't dbra\n");\r
85a36a57 296 ot(" b%s DbraTrue\n\n",Cond[cc]);\r
3a5e6cf8 297 break;\r
cc68a136 298 }\r
299\r
3a5e6cf8 300 if (cc!=0)\r
301 {\r
302 ot(";@ Decrement Dn.w\n");\r
303 ot(" and r1,r8,#0x0007\n");\r
304 ot(" mov r1,r1,lsl #2\n");\r
305 ot(" ldrsh r0,[r7,r1]\n");\r
306 ot(" sub r0,r0,#1\n");\r
307 ot(" strh r0,[r7,r1]\n");\r
308 ot("\n");\r
cc68a136 309\r
3a5e6cf8 310 ot(";@ Check if Dn.w is -1\n");\r
311 ot(" cmn r0,#1\n");\r
03c5768c 312\r
313#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
314 ot(" beq DbraMin1\n");\r
3a5e6cf8 315 ot("\n");\r
cc68a136 316\r
03c5768c 317 ot(";@ Get Branch offset:\n");\r
318 ot(" ldrsh r0,[r4]\n");\r
319 ot(" add r0,r4,r0 ;@ r4 = New PC\n");\r
320 CheckPc(0);\r
321#else\r
322 ot("\n");\r
3a5e6cf8 323 ot(";@ Get Branch offset:\n");\r
324 ot(" ldrnesh r0,[r4]\n");\r
325 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
326 ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
327 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
1c88b865 328 ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r
3a5e6cf8 329 ot("\n");\r
03c5768c 330#endif\r
3a5e6cf8 331 Cycles=12-2;\r
332 OpEnd();\r
333 }\r
cc68a136 334 \r
85a36a57 335 //if (cc==0||cc>=2)\r
336 if (op==0x50c8)\r
3a5e6cf8 337 {\r
338 ot(";@ condition true:\n");\r
85a36a57 339 ot("DbraTrue%s\n", ms?"":":");\r
3a5e6cf8 340 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
341 ot("\n");\r
342 Cycles=12;\r
343 OpEnd();\r
344 }\r
cc68a136 345\r
03c5768c 346#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
347 if (op==0x51c8)\r
348 {\r
349 ot(";@ Dn.w is -1:\n");\r
350 ot("DbraMin1%s\n", ms?"":":");\r
351 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
352 ot("\n");\r
353 Cycles=12+2;\r
354 OpEnd();\r
355 }\r
356#endif\r
357\r
cc68a136 358 return 0;\r
359}\r
360\r
361// --------------------- Opcodes 0x6000+ ---------------------\r
362// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
363int OpBranch(int op)\r
364{\r
03c5768c 365 int size=0,use=0,checkpc=0;\r
cc68a136 366 int offset=0;\r
367 int cc=0;\r
85a36a57 368 char *asr_r11="";\r
cc68a136 369\r
370 offset=(char)(op&0xff);\r
371 cc=(op>>8)&15;\r
372\r
373 // Special offsets:\r
374 if (offset==0) size=1;\r
375 if (offset==-1) size=2;\r
376\r
1c88b865 377 if (size==2) size=0; // 000 model does not support long displacement\r
cc68a136 378 if (size) use=op; // 16-bit or 32-bit\r
379 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
380\r
381 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
a6785576 382 OpStart(op,size?0x10:0);\r
cc68a136 383 Cycles=10; // Assume branch taken\r
384\r
cc68a136 385 if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
386\r
85a36a57 387 switch (cc)\r
cc68a136 388 {\r
85a36a57 389 case 0: // T\r
390 case 1: // F\r
391 break;\r
392 case 2: // hi\r
393 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
394 ot(" bne BccDontBranch%i\n\n",8<<size);\r
395 break;\r
396 case 3: // ls\r
397 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
398 ot(" beq BccDontBranch%i\n\n",8<<size);\r
399 break;\r
400 default:\r
401 ot(";@ Is the condition true?\n");\r
402 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
403 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
404 break;\r
cc68a136 405 }\r
cfb3dfa0 406\r
85a36a57 407 if (size) \r
408 {\r
409 if (size<2)\r
410 {\r
411 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
412 }\r
413 else\r
414 {\r
415 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
416 ot(" ldrh r11,[r4,#2]\n");\r
417 ot(" orr r11,r11,r2,lsl #16\n");\r
418 }\r
419 }\r
420 else\r
421 {\r
422 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
423 asr_r11=",asr #24";\r
424 }\r
cc68a136 425\r
426 ot(";@ Branch taken - Add on r0 to PC\n");\r
427\r
428 if (cc==1)\r
429 {\r
430 ot(";@ Bsr - remember old PC\n");\r
547045e3 431 ot(" ldr r2,[r7,#0x3c]\n");\r
cc68a136 432 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
85a36a57 433 if (size) ot(" add r1,r1,#%d\n",1<<size);\r
cc68a136 434 ot("\n");\r
cc68a136 435 ot(";@ Push r1 onto stack\n");\r
436 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
437 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
438 MemHandler(1,2);\r
439 ot("\n");\r
440 Cycles=18; // always 18\r
03c5768c 441 }\r
442\r
1c88b865 443 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
444\r
03c5768c 445#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
446 if (offset!=0 && offset!=-1) checkpc=1;\r
447#endif\r
448#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
449 if (offset==0) checkpc=1;\r
450#endif\r
451#if USE_CHECKPC_CALLBACK\r
452 if (offset==-1) checkpc=1;\r
453#endif\r
454 if (checkpc)\r
455 {\r
03c5768c 456 CheckPc(0);\r
cc68a136 457 }\r
458 else\r
459 {\r
1c88b865 460 ot(" bic r4,r0,#1\n"); // we do not emulate address errors\r
03c5768c 461 ot("\n");\r
cc68a136 462 }\r
463\r
cfb3dfa0 464 OpEnd(size?0x10:0);\r
cc68a136 465\r
85a36a57 466 // since all "DontBranch" code is same for every size, output only once\r
467 if (cc>=2&&(op&0xff00)==0x6200)\r
cc68a136 468 {\r
85a36a57 469 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
03c5768c 470 if (size) ot(" add r4,r4,#%d\n",1<<size);\r
85a36a57 471 Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
472 OpEnd(0);\r
cc68a136 473 }\r
474\r
475 return 0;\r
476}\r
477\r
fast MegaDrive/MegaCD/32X emulator