32x: change irq hadling, make it more drc friendly

[picodrive.git] / cpu / sh2 / sh2.h

#ifndef __SH2_H__\r
#define __SH2_H__\r
\r
// pico memhandlers\r
// XXX: move somewhere else\r
unsigned int p32x_sh2_read8(unsigned int a, int id);\r
unsigned int p32x_sh2_read16(unsigned int a, int id);\r
unsigned int p32x_sh2_read32(unsigned int a, int id);\r
void p32x_sh2_write8(unsigned int a, unsigned int d, int id);\r
void p32x_sh2_write16(unsigned int a, unsigned int d, int id);\r
void p32x_sh2_write32(unsigned int a, unsigned int d, int id);\r
\r
\r
typedef struct\r
{\r
	unsigned int	r[16];		// 00\r
	unsigned int	pc;		// 40\r
	unsigned int	ppc;\r
	unsigned int	pr;\r
	unsigned int	sr;\r
	unsigned int	gbr, vbr;	// 50\r
	unsigned int	mach, macl;	// 58\r
\r
	// interpreter stuff\r
	int		icount;		// 60 cycles left in current timeslice\r
	unsigned int	ea;\r
	unsigned int	delay;\r
	unsigned int	test_irq;\r
\r
	// drc stuff\r
	void	**pc_hashtab;		// 70\r
\r
	// common\r
	int	pending_level;		// MAX(pending_irl, pending_int_irq)\r
	int	pending_irl;\r
	int	pending_int_irq;	// internal irq\r
	int	pending_int_vector;\r
	void	(*irq_callback)(int id, int level);\r
	int	is_slave;\r
\r
	unsigned int	cycles_aim;	// subtract sh2_icount to get global counter\r
	unsigned int	cycles_done;\r
} SH2;\r
\r
extern SH2 *sh2; // active sh2\r
\r
int  sh2_init(SH2 *sh2, int is_slave);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
void sh2_irl_irq(SH2 *sh2, int level);\r
void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
void sh2_do_irq(SH2 *sh2, int level, int vector);\r
\r
void sh2_execute(SH2 *sh2, int cycles);\r
\r
#endif /* __SH2_H__ */\r