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1 | /* |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2009-2011 |
3 | * |
4 | * This work is licensed under the terms of the GNU GPLv2 or later. |
5 | * See the COPYING file in the top-level directory. |
6 | */ |
7 | |
8 | #include <stdio.h> |
9 | #include <stdlib.h> |
10 | #include <string.h> |
11 | #include <sys/types.h> |
12 | #include <sys/stat.h> |
13 | #include <fcntl.h> |
14 | #include <sys/ioctl.h> |
15 | #include <unistd.h> |
16 | #include <linux/fb.h> |
17 | #include <sys/mman.h> |
18 | |
19 | #include "common/input.h" |
20 | #include "common/menu.h" |
21 | #include "warm/warm.h" |
22 | #include "plugin_lib.h" |
23 | #include "cspace.h" |
24 | #include "main.h" |
25 | #include "menu.h" |
26 | #include "plat.h" |
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27 | #include "pcnt.h" |
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28 | |
29 | static int fbdev = -1, memdev = -1, battdev = -1; |
30 | static volatile unsigned short *memregs; |
31 | static volatile unsigned int *memregl; |
32 | static void *fb_vaddrs[2]; |
33 | static unsigned int fb_paddrs[2]; |
34 | static int fb_work_buf; |
35 | static int cpu_clock_allowed; |
36 | |
37 | static unsigned short *psx_vram; |
38 | static unsigned int psx_vram_padds[512]; |
39 | static int psx_offset, psx_step, psx_width, psx_height, psx_bpp; |
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40 | static int fb_offset_x, fb_offset_y; |
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41 | |
42 | // TODO: get rid of this |
43 | struct vout_fbdev; |
44 | struct vout_fbdev *layer_fb; |
45 | int g_layer_x, g_layer_y, g_layer_w, g_layer_h; |
46 | |
47 | int omap_enable_layer(int enabled) |
48 | { |
49 | return 0; |
50 | } |
51 | |
52 | static void *fb_flip(void) |
53 | { |
54 | memregl[0x406C>>2] = fb_paddrs[fb_work_buf]; |
55 | memregl[0x4058>>2] |= 0x10; |
56 | fb_work_buf ^= 1; |
57 | return fb_vaddrs[fb_work_buf]; |
58 | } |
59 | |
60 | static void pollux_changemode(int bpp, int is_bgr) |
61 | { |
62 | int code = 0, bytes = 2; |
63 | unsigned int r; |
64 | |
65 | printf("changemode: %dbpp %s\n", bpp, is_bgr ? "bgr" : "rgb"); |
66 | |
67 | memregl[0x4004>>2] = 0x00ef013f; |
68 | memregl[0x4000>>2] |= 1 << 3; |
69 | |
70 | switch (bpp) |
71 | { |
72 | case 8: |
73 | code = 0x443a; |
74 | bytes = 1; |
75 | break; |
76 | case 16: |
77 | code = is_bgr ? 0xc342 : 0x4432; |
78 | bytes = 2; |
79 | break; |
80 | case 24: |
81 | code = is_bgr ? 0xc653 : 0x4653; |
82 | bytes = 3; |
83 | break; |
84 | default: |
85 | printf("unhandled bpp request: %d\n", bpp); |
86 | return; |
87 | } |
88 | |
89 | memregl[0x405c>>2] = bytes; |
90 | memregl[0x4060>>2] = 320 * bytes; |
91 | |
92 | r = memregl[0x4058>>2]; |
93 | r = (r & 0xffff) | (code << 16) | 0x10; |
94 | memregl[0x4058>>2] = r; |
95 | } |
96 | |
97 | /* note: both PLLs are programmed the same way, |
98 | * the databook incorrectly states that PLL1 differs */ |
99 | static int decode_pll(unsigned int reg) |
100 | { |
101 | long long v; |
102 | int p, m, s; |
103 | |
104 | p = (reg >> 18) & 0x3f; |
105 | m = (reg >> 8) & 0x3ff; |
106 | s = reg & 0xff; |
107 | |
108 | if (p == 0) |
109 | p = 1; |
110 | |
111 | v = 27000000; // master clock |
112 | v = v * m / (p << s); |
113 | return v; |
114 | } |
115 | |
116 | int plat_cpu_clock_get(void) |
117 | { |
118 | return decode_pll(memregl[0xf004>>2]) / 1000000; |
119 | } |
120 | |
121 | int plat_cpu_clock_apply(int mhz) |
122 | { |
123 | int adiv, mdiv, pdiv, sdiv = 0; |
124 | int i, vf000, vf004; |
125 | |
126 | if (!cpu_clock_allowed) |
127 | return -1; |
128 | if (mhz == plat_cpu_clock_get()) |
129 | return 0; |
130 | |
131 | // m = MDIV, p = PDIV, s = SDIV |
132 | #define SYS_CLK_FREQ 27 |
133 | pdiv = 9; |
134 | mdiv = (mhz * pdiv) / SYS_CLK_FREQ; |
135 | if (mdiv & ~0x3ff) |
136 | return -1; |
137 | vf004 = (pdiv<<18) | (mdiv<<8) | sdiv; |
138 | |
139 | // attempt to keep the AHB divider close to 250, but not higher |
140 | for (adiv = 1; mhz / adiv > 250; adiv++) |
141 | ; |
142 | |
143 | vf000 = memregl[0xf000>>2]; |
144 | vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6); |
145 | memregl[0xf000>>2] = vf000; |
146 | memregl[0xf004>>2] = vf004; |
147 | memregl[0xf07c>>2] |= 0x8000; |
148 | for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++) |
149 | ; |
150 | |
151 | printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv); |
152 | |
153 | // stupid pll share hack - must restart audio |
154 | extern long SPUopen(void); |
155 | extern long SPUclose(void); |
156 | SPUclose(); |
157 | SPUopen(); |
158 | |
159 | return 0; |
160 | } |
161 | |
162 | int plat_get_bat_capacity(void) |
163 | { |
164 | unsigned short magic_val = 0; |
165 | |
166 | if (battdev < 0) |
167 | return -1; |
168 | if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val)) |
169 | return -1; |
170 | switch (magic_val) { |
171 | default: |
172 | case 1: return 100; |
173 | case 2: return 66; |
174 | case 3: return 40; |
175 | case 4: return 0; |
176 | } |
177 | } |
178 | |
179 | #define TIMER_BASE3 0x1980 |
180 | #define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2] |
181 | |
182 | static __attribute__((unused)) unsigned int timer_get(void) |
183 | { |
184 | TIMER_REG(0x08) |= 0x48; /* run timer, latch value */ |
185 | return TIMER_REG(0); |
186 | } |
187 | |
188 | static void timer_cleanup(void) |
189 | { |
190 | TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */ |
191 | TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */ |
192 | TIMER_REG(0x00) = 0; /* clear counter */ |
193 | TIMER_REG(0x40) = 0; /* clocks off */ |
194 | TIMER_REG(0x44) = 0; /* dividers back to default */ |
195 | } |
196 | |
197 | void plat_video_menu_enter(int is_rom_loaded) |
198 | { |
199 | if (pl_vout_buf != NULL) { |
200 | if (psx_bpp == 16) |
201 | // have to do rgb conversion for menu bg |
202 | bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 320*240*2); |
203 | else |
204 | memset(pl_vout_buf, 0, 320*240*2); |
205 | } |
206 | |
207 | pollux_changemode(16, 0); |
208 | } |
209 | |
210 | void plat_video_menu_begin(void) |
211 | { |
212 | } |
213 | |
214 | void plat_video_menu_end(void) |
215 | { |
216 | g_menuscreen_ptr = fb_flip(); |
217 | } |
218 | |
219 | void plat_video_menu_leave(void) |
220 | { |
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221 | if (psx_vram == NULL) { |
222 | fprintf(stderr, "GPU plugin did not provide vram\n"); |
223 | exit(1); |
224 | } |
225 | |
226 | in_set_config_int(in_name_to_id("evdev:pollux-analog"), |
227 | IN_CFG_ABS_DEAD_ZONE, analog_deadzone); |
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228 | |
229 | memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8); |
230 | g_menuscreen_ptr = fb_flip(); |
231 | memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8); |
232 | |
233 | pollux_changemode(psx_bpp, 1); |
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234 | } |
235 | |
236 | static void pl_vout_set_raw_vram(void *vram) |
237 | { |
238 | int i; |
239 | |
240 | psx_vram = vram; |
241 | |
242 | if (vram == NULL) |
243 | return; |
244 | |
245 | if ((long)psx_vram & 0x7ff) |
246 | fprintf(stderr, "GPU plugin did not align vram\n"); |
247 | |
248 | for (i = 0; i < 512; i++) { |
249 | psx_vram[i * 1024] = 0; // touch |
250 | psx_vram_padds[i] = warm_virt2phys(&psx_vram[i * 1024]); |
251 | } |
252 | } |
253 | |
254 | static void *pl_vout_set_mode(int w, int h, int bpp) |
255 | { |
256 | static int old_w, old_h, old_bpp; |
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257 | int poff_w, poff_h; |
258 | |
259 | if (!w || !h || !bpp || (w == old_w && h == old_h && bpp == old_bpp)) |
260 | return NULL; |
261 | |
262 | printf("psx mode: %dx%d@%d\n", w, h, bpp); |
263 | |
264 | psx_step = 1; |
265 | if (h > 256) { |
266 | psx_step = 2; |
267 | h /= 2; |
268 | } |
269 | |
270 | poff_w = poff_h = 0; |
271 | if (w > 320) { |
272 | poff_w = w / 2 - 320/2; |
273 | w = 320; |
274 | } |
275 | if (h > 240) { |
276 | poff_h = h / 2 - 240/2; |
277 | h = 240; |
278 | } |
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279 | fb_offset_x = 320/2 - w / 2; |
280 | fb_offset_y = 240/2 - h / 2; |
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281 | |
282 | psx_offset = poff_h * 1024 + poff_w; |
283 | psx_width = w; |
284 | psx_height = h; |
285 | psx_bpp = bpp; |
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286 | |
287 | if (fb_offset_x || fb_offset_y) { |
288 | // not fullscreen, must clear borders |
289 | memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8); |
290 | g_menuscreen_ptr = fb_flip(); |
291 | memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8); |
292 | } |
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293 | |
294 | pollux_changemode(bpp, 1); |
295 | |
296 | return NULL; |
297 | } |
298 | |
299 | static void spend_cycles(int loops) |
300 | { |
301 | asm volatile ( |
302 | " mov r0,%0 ;\n" |
303 | "0: subs r0,r0,#1 ;\n" |
304 | " bgt 0b" |
305 | :: "r" (loops) : "cc", "r0"); |
306 | } |
307 | |
308 | #define DMA_BASE6 0x0300 |
309 | #define DMA_REG(x) memregl[(DMA_BASE6 + x) >> 2] |
310 | |
311 | /* this takes ~1.5ms, while ldm/stm ~1.95ms */ |
312 | static void raw_flip_dma(int x, int y) |
313 | { |
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314 | unsigned int dst = fb_paddrs[fb_work_buf] + |
315 | (fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8; |
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316 | int spsx_line = y + (psx_offset >> 10); |
317 | int spsx_offset = (x + psx_offset) & 0x3f8; |
318 | int dst_stride = 320 * psx_bpp / 8; |
319 | int len = psx_width * psx_bpp / 8; |
320 | //unsigned int st = timer_get(); |
321 | int i; |
322 | |
323 | warm_cache_op_all(WOP_D_CLEAN); |
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324 | pcnt_start(PCNT_BLIT); |
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325 | |
326 | dst &= ~7; |
327 | len &= ~7; |
328 | |
329 | if (DMA_REG(0x0c) & 0x90000) { |
330 | printf("already runnig DMA?\n"); |
331 | DMA_REG(0x0c) = 0x100000; |
332 | } |
333 | if ((DMA_REG(0x2c) & 0x0f) < 5) { |
334 | printf("DMA queue busy?\n"); |
335 | DMA_REG(0x24) = 1; |
336 | } |
337 | |
338 | for (i = psx_height; i > 0; i--, spsx_line += psx_step, dst += dst_stride) { |
339 | while ((DMA_REG(0x2c) & 0x0f) < 4) |
340 | spend_cycles(10); |
341 | |
342 | // XXX: it seems we must always set all regs, what is autoincrement there for? |
343 | DMA_REG(0x20) = 1; // queue wait cmd |
344 | DMA_REG(0x10) = psx_vram_padds[spsx_line & 511] + spsx_offset * 2; // DMA src |
345 | DMA_REG(0x14) = dst; // DMA dst |
346 | DMA_REG(0x18) = len - 1; // len |
347 | DMA_REG(0x1c) = 0x80000; // go |
348 | } |
349 | |
350 | //printf("d %d\n", timer_get() - st); |
351 | |
352 | if (psx_bpp == 16) { |
353 | pl_vout_buf = g_menuscreen_ptr; |
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354 | pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x); |
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355 | } |
356 | |
357 | g_menuscreen_ptr = fb_flip(); |
358 | pl_flip_cnt++; |
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359 | |
360 | pcnt_end(PCNT_BLIT); |
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361 | } |
362 | |
363 | static void raw_flip_soft(int x, int y) |
364 | { |
365 | unsigned short *src = psx_vram + y * 1024 + x + psx_offset; |
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366 | unsigned char *dst = (unsigned char *)g_menuscreen_ptr + |
367 | (fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8; |
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368 | int dst_stride = 320 * psx_bpp / 8; |
369 | int len = psx_width * psx_bpp / 8; |
370 | //unsigned int st = timer_get(); |
371 | int i; |
372 | |
373 | for (i = psx_height; i > 0; i--, src += psx_step * 1024, dst += dst_stride) |
374 | memcpy(dst, src, len); |
375 | |
376 | //printf("s %d\n", timer_get() - st); |
377 | |
378 | if (psx_bpp == 16) { |
379 | pl_vout_buf = g_menuscreen_ptr; |
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380 | pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x); |
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381 | } |
382 | |
383 | g_menuscreen_ptr = fb_flip(); |
384 | pl_flip_cnt++; |
385 | } |
386 | |
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387 | static void *pl_vout_flip(void) |
388 | { |
389 | return NULL; |
390 | } |
391 | |
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392 | void plat_init(void) |
393 | { |
394 | const char *main_fb_name = "/dev/fb0"; |
395 | struct fb_fix_screeninfo fbfix; |
396 | int rate, timer_div, timer_div2; |
397 | int fbdev, ret, warm_ret; |
398 | |
399 | memdev = open("/dev/mem", O_RDWR); |
400 | if (memdev == -1) { |
401 | perror("open(/dev/mem) failed"); |
402 | exit(1); |
403 | } |
404 | |
405 | memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000); |
406 | if (memregs == MAP_FAILED) { |
407 | perror("mmap(memregs) failed"); |
408 | exit(1); |
409 | } |
410 | memregl = (volatile void *)memregs; |
411 | |
412 | fbdev = open(main_fb_name, O_RDWR); |
413 | if (fbdev == -1) { |
414 | fprintf(stderr, "%s: ", main_fb_name); |
415 | perror("open"); |
416 | exit(1); |
417 | } |
418 | |
419 | ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix); |
420 | if (ret == -1) { |
421 | perror("ioctl(fbdev) failed"); |
422 | exit(1); |
423 | } |
424 | printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start); |
425 | fb_paddrs[0] = fbfix.smem_start; |
426 | fb_paddrs[1] = fb_paddrs[0] + 320*240*4; // leave space for 24bpp |
427 | |
428 | fb_vaddrs[0] = mmap(0, 320*240*2*4, PROT_READ|PROT_WRITE, |
429 | MAP_SHARED, memdev, fb_paddrs[0]); |
430 | if (fb_vaddrs[0] == MAP_FAILED) { |
431 | perror("mmap(fb_vaddrs) failed"); |
432 | exit(1); |
433 | } |
434 | fb_vaddrs[1] = (char *)fb_vaddrs[0] + 320*240*4; |
435 | |
436 | pollux_changemode(16, 0); |
437 | g_menuscreen_w = 320; |
438 | g_menuscreen_h = 240; |
439 | g_menuscreen_ptr = fb_flip(); |
440 | |
441 | g_menubg_ptr = calloc(320*240*2, 1); |
442 | if (g_menubg_ptr == NULL) { |
443 | fprintf(stderr, "OOM\n"); |
444 | exit(1); |
445 | } |
446 | |
447 | warm_ret = warm_init(); |
448 | warm_change_cb_upper(WCB_B_BIT, 1); |
449 | |
450 | /* some firmwares have sys clk on PLL0, we can't adjust CPU clock |
451 | * by reprogramming the PLL0 then, as it overclocks system bus */ |
452 | if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000) |
453 | cpu_clock_allowed = 1; |
454 | else { |
455 | cpu_clock_allowed = 0; |
456 | fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n", |
457 | memregl[0xf000>>2]); |
458 | } |
459 | |
460 | /* find what PLL1 runs at, for the timer */ |
461 | rate = decode_pll(memregl[0xf008>>2]); |
462 | printf("PLL1 @ %dHz\n", rate); |
463 | |
464 | /* setup timer */ |
465 | timer_div = (rate + 500000) / 1000000; |
466 | timer_div2 = 0; |
467 | while (timer_div > 256) { |
468 | timer_div /= 2; |
469 | timer_div2++; |
470 | } |
471 | if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) { |
472 | int timer_rate = (rate >> timer_div2) / timer_div; |
473 | if (TIMER_REG(0x08) & 8) { |
474 | fprintf(stderr, "warning: timer in use, overriding!\n"); |
475 | timer_cleanup(); |
476 | } |
477 | if (timer_rate != 1000000) |
478 | fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000); |
479 | |
480 | timer_div2 = (timer_div2 + 3) & 3; |
481 | TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */ |
482 | TIMER_REG(0x40) = 0x0c; /* clocks on */ |
483 | TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */ |
484 | } |
485 | else |
486 | fprintf(stderr, "warning: could not make use of timer\n"); |
487 | |
488 | /* setup DMA */ |
489 | DMA_REG(0x0c) = 0x20000; // pending IRQ clear |
490 | |
491 | battdev = open("/dev/pollux_batt", O_RDONLY); |
492 | if (battdev < 0) |
493 | perror("Warning: could't open pollux_batt"); |
494 | |
495 | // hmh |
496 | plat_rescan_inputs(); |
497 | |
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498 | pl_rearmed_cbs.pl_vout_flip = pl_vout_flip; |
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499 | pl_rearmed_cbs.pl_vout_raw_flip = warm_ret == 0 ? raw_flip_dma : raw_flip_soft; |
500 | pl_rearmed_cbs.pl_vout_set_mode = pl_vout_set_mode; |
501 | pl_rearmed_cbs.pl_vout_set_raw_vram = pl_vout_set_raw_vram; |
502 | |
503 | psx_width = 320; |
504 | psx_height = 240; |
505 | psx_bpp = 16; |
506 | } |
507 | |
508 | void plat_finish(void) |
509 | { |
510 | warm_finish(); |
511 | timer_cleanup(); |
512 | pollux_changemode(16, 0); |
513 | fb_work_buf = 0; |
514 | fb_flip(); |
515 | |
516 | if (battdev >= 0) |
517 | close(battdev); |
518 | munmap(fb_vaddrs[0], 320*240*2*2); |
519 | close(fbdev); |
520 | munmap((void *)memregs, 0x20000); |
521 | close(memdev); |
522 | } |
523 | |
524 | void in_update_analogs(void) |
525 | { |
526 | } |
527 | |
528 | /* Caanoo stuff, perhaps move later */ |
529 | #include <linux/input.h> |
530 | |
531 | struct in_default_bind in_evdev_defbinds[] = { |
532 | { KEY_UP, IN_BINDTYPE_PLAYER12, DKEY_UP }, |
533 | { KEY_DOWN, IN_BINDTYPE_PLAYER12, DKEY_DOWN }, |
534 | { KEY_LEFT, IN_BINDTYPE_PLAYER12, DKEY_LEFT }, |
535 | { KEY_RIGHT, IN_BINDTYPE_PLAYER12, DKEY_RIGHT }, |
536 | { BTN_TOP, IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE }, |
537 | { BTN_THUMB, IN_BINDTYPE_PLAYER12, DKEY_CROSS }, |
538 | { BTN_THUMB2, IN_BINDTYPE_PLAYER12, DKEY_CIRCLE }, |
539 | { BTN_TRIGGER, IN_BINDTYPE_PLAYER12, DKEY_SQUARE }, |
540 | { BTN_BASE3, IN_BINDTYPE_PLAYER12, DKEY_START }, |
541 | { BTN_BASE4, IN_BINDTYPE_PLAYER12, DKEY_SELECT }, |
542 | { BTN_TOP2, IN_BINDTYPE_PLAYER12, DKEY_L1 }, |
543 | { BTN_PINKIE, IN_BINDTYPE_PLAYER12, DKEY_R1 }, |
544 | { BTN_BASE, IN_BINDTYPE_EMU, SACTION_ENTER_MENU }, |
545 | { 0, 0, 0 }, |
546 | }; |
547 | |
548 | static const char * const caanoo_keys[KEY_MAX + 1] = { |
549 | [0 ... KEY_MAX] = NULL, |
550 | [KEY_UP] = "Up", |
551 | [KEY_LEFT] = "Left", |
552 | [KEY_RIGHT] = "Right", |
553 | [KEY_DOWN] = "Down", |
554 | [BTN_TRIGGER] = "A", |
555 | [BTN_THUMB] = "X", |
556 | [BTN_THUMB2] = "B", |
557 | [BTN_TOP] = "Y", |
558 | [BTN_TOP2] = "L", |
559 | [BTN_PINKIE] = "R", |
560 | [BTN_BASE] = "Home", |
561 | [BTN_BASE2] = "Lock", |
562 | [BTN_BASE3] = "I", |
563 | [BTN_BASE4] = "II", |
564 | [BTN_BASE5] = "Push", |
565 | }; |
566 | |
567 | int plat_rescan_inputs(void) |
568 | { |
569 | in_probe(); |
570 | in_set_config(in_name_to_id("evdev:pollux-analog"), IN_CFG_KEY_NAMES, |
571 | caanoo_keys, sizeof(caanoo_keys)); |
572 | return 0; |
573 | } |