f27b1cea |
1 | /* |
f89d8471 |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2009-2010 |
3 | * |
4 | * This work is licensed under the terms of any of these licenses |
5 | * (at your option): |
6 | * - GNU GPL, version 2 or later. |
7 | * - GNU LGPL, version 2.1 or later. |
8 | * - MAME license. |
9 | * See the COPYING file in the top-level directory. |
10 | * |
f27b1cea |
11 | * <random_info=mem_map> |
12 | * 00000000-029fffff linux (42MB) |
13 | * 02a00000-02dfffff fb (4MB, 153600B really used) |
14 | * 02e00000-02ffffff sound dma (2MB) |
15 | * 03000000-03ffffff MPEGDEC (?, 16MB) |
16 | * </random_info> |
17 | */ |
f89d8471 |
18 | |
fa8d1331 |
19 | #include <stdio.h> |
20 | #include <stdlib.h> |
21 | #include <string.h> |
22 | #include <math.h> |
23 | #include <sys/types.h> |
24 | #include <sys/stat.h> |
25 | #include <fcntl.h> |
26 | #include <sys/mman.h> |
27 | #include <unistd.h> |
28 | #include <sys/ioctl.h> |
29 | #include <linux/fb.h> |
afdbb7c8 |
30 | #include <linux/soundcard.h> |
fa8d1331 |
31 | |
32 | #include "soc.h" |
33 | #include "plat_gp2x.h" |
a86e9a3e |
34 | #include "../plat.h" |
fa8d1331 |
35 | |
afdbb7c8 |
36 | volatile unsigned short *memregs; |
37 | volatile unsigned int *memregl; |
38 | int memdev = -1; |
39 | int gp2x_dev_id; |
fa8d1331 |
40 | |
afdbb7c8 |
41 | static int battdev = -1, mixerdev = -1; |
42 | static int cpu_clock_allowed; |
43 | static unsigned int saved_video_regs[2][6]; |
44 | |
45 | #ifndef ARRAY_SIZE |
46 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) |
47 | #endif |
48 | |
49 | // TODO FIXME: merge |
50 | #if 0 |
fa8d1331 |
51 | extern void *gp2x_screens[4]; |
52 | |
53 | #define fb_buf_count 4 |
54 | static unsigned int fb_paddr[fb_buf_count]; |
55 | static int fb_work_buf; |
56 | static int fbdev = -1; |
57 | |
71769e27 |
58 | static char cpuclk_was_changed = 0; |
59 | static unsigned short memtimex_old[2]; |
f679add7 |
60 | static unsigned int pllsetreg0_old; |
61 | static unsigned int timer_drift; // count per real second |
b7911801 |
62 | static int last_pal_setting = 0; |
71769e27 |
63 | |
fa8d1331 |
64 | |
f71361b5 |
65 | /* misc */ |
66 | static void pollux_set_fromenv(const char *env_var) |
67 | { |
68 | const char *set_string; |
69 | set_string = getenv(env_var); |
70 | if (set_string) |
71 | pollux_set(memregs, set_string); |
72 | else |
73 | printf("env var %s not defined.\n", env_var); |
74 | } |
75 | |
fa8d1331 |
76 | /* video stuff */ |
77 | static void pollux_video_flip(int buf_count) |
78 | { |
79 | memregl[0x406C>>2] = fb_paddr[fb_work_buf]; |
80 | memregl[0x4058>>2] |= 0x10; |
81 | fb_work_buf++; |
82 | if (fb_work_buf >= buf_count) |
83 | fb_work_buf = 0; |
84 | g_screen_ptr = gp2x_screens[fb_work_buf]; |
85 | } |
86 | |
87 | static void gp2x_video_flip_(void) |
88 | { |
89 | pollux_video_flip(fb_buf_count); |
90 | } |
91 | |
92 | /* doulblebuffered flip */ |
93 | static void gp2x_video_flip2_(void) |
94 | { |
95 | pollux_video_flip(2); |
96 | } |
97 | |
98 | static void gp2x_video_changemode_ll_(int bpp) |
99 | { |
b7911801 |
100 | static int prev_bpp = 0; |
fa8d1331 |
101 | int code = 0, bytes = 2; |
b7911801 |
102 | int rot_cmd[2] = { 0, 0 }; |
fa8d1331 |
103 | unsigned int r; |
f71361b5 |
104 | char buff[32]; |
b7911801 |
105 | int ret; |
106 | |
107 | if (bpp == prev_bpp) |
108 | return; |
109 | prev_bpp = bpp; |
110 | |
111 | printf("changemode: %dbpp rot=%d\n", abs(bpp), bpp < 0); |
112 | |
113 | /* negative bpp means rotated mode */ |
114 | rot_cmd[0] = (bpp < 0) ? 6 : 5; |
115 | ret = ioctl(fbdev, _IOW('D', 90, int[2]), rot_cmd); |
116 | if (ret < 0) |
117 | perror("rot ioctl failed"); |
118 | memregl[0x4004>>2] = (bpp < 0) ? 0x013f00ef : 0x00ef013f; |
119 | memregl[0x4000>>2] |= 1 << 3; |
120 | |
121 | /* the above ioctl resets LCD timings, so set them here */ |
f71361b5 |
122 | snprintf(buff, sizeof(buff), "POLLUX_LCD_TIMINGS_%s", last_pal_setting ? "PAL" : "NTSC"); |
123 | pollux_set_fromenv(buff); |
b7911801 |
124 | |
125 | switch (abs(bpp)) |
fa8d1331 |
126 | { |
127 | case 8: |
128 | code = 0x443a; |
129 | bytes = 1; |
130 | break; |
131 | |
132 | case 15: |
133 | case 16: |
134 | code = 0x4432; |
135 | bytes = 2; |
136 | break; |
137 | |
138 | default: |
b7911801 |
139 | printf("unhandled bpp request: %d\n", abs(bpp)); |
fa8d1331 |
140 | return; |
141 | } |
142 | |
143 | memregl[0x405c>>2] = bytes; |
b7911801 |
144 | memregl[0x4060>>2] = bytes * (bpp < 0 ? 240 : 320); |
fa8d1331 |
145 | |
146 | r = memregl[0x4058>>2]; |
147 | r = (r & 0xffff) | (code << 16) | 0x10; |
148 | memregl[0x4058>>2] = r; |
149 | } |
150 | |
151 | static void gp2x_video_setpalette_(int *pal, int len) |
152 | { |
153 | /* pollux palette is 16bpp only.. */ |
154 | int i; |
155 | for (i = 0; i < len; i++) |
156 | { |
157 | int c = pal[i]; |
158 | c = ((c >> 8) & 0xf800) | ((c >> 5) & 0x07c0) | ((c >> 3) & 0x001f); |
159 | memregl[0x4070>>2] = (i << 24) | c; |
160 | } |
161 | } |
162 | |
163 | static void gp2x_video_RGB_setscaling_(int ln_offs, int W, int H) |
164 | { |
165 | /* maybe a job for 3d hardware? */ |
166 | } |
167 | |
168 | static void gp2x_video_wait_vsync_(void) |
169 | { |
38163dd7 |
170 | while (!(memregl[0x308c>>2] & (1 << 10))) |
fa8d1331 |
171 | spend_cycles(128); |
172 | memregl[0x308c>>2] |= 1 << 10; |
173 | } |
174 | |
175 | /* CPU clock */ |
176 | static void gp2x_set_cpuclk_(unsigned int mhz) |
177 | { |
178 | char buff[24]; |
179 | snprintf(buff, sizeof(buff), "cpuclk=%u", mhz); |
180 | pollux_set(memregs, buff); |
71769e27 |
181 | |
182 | cpuclk_was_changed = 1; |
fa8d1331 |
183 | } |
184 | |
fa8d1331 |
185 | /* RAM timings */ |
fa8d1331 |
186 | static void set_ram_timings_(void) |
187 | { |
188 | pollux_set_fromenv("POLLUX_RAM_TIMINGS"); |
189 | } |
190 | |
191 | static void unset_ram_timings_(void) |
192 | { |
193 | int i; |
194 | |
71769e27 |
195 | memregs[0x14802>>1] = memtimex_old[0]; |
196 | memregs[0x14804>>1] = memtimex_old[1] | 0x8000; |
fa8d1331 |
197 | |
198 | for (i = 0; i < 0x100000; i++) |
199 | if (!(memregs[0x14804>>1] & 0x8000)) |
200 | break; |
201 | |
202 | printf("RAM timings reset to startup values.\n"); |
203 | } |
204 | |
205 | /* LCD refresh */ |
206 | static void set_lcd_custom_rate_(int is_pal) |
207 | { |
f71361b5 |
208 | /* just remember PAL/NTSC. We always set timings in _changemode_ll() */ |
b7911801 |
209 | last_pal_setting = is_pal; |
fa8d1331 |
210 | } |
211 | |
212 | static void unset_lcd_custom_rate_(void) |
213 | { |
214 | } |
215 | |
216 | static void set_lcd_gamma_(int g100, int A_SNs_curve) |
217 | { |
218 | /* hm, the LCD possibly can do it (but not POLLUX) */ |
219 | } |
d572cbad |
220 | |
053bef76 |
221 | static int gp2x_read_battery_(void) |
222 | { |
223 | unsigned short magic_val = 0; |
224 | |
225 | if (battdev < 0) |
226 | return -1; |
227 | if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val)) |
228 | return -1; |
229 | switch (magic_val) { |
230 | default: |
231 | case 1: return 100; |
232 | case 2: return 66; |
233 | case 3: return 40; |
234 | case 4: return 0; |
235 | } |
236 | } |
237 | |
b5bfb864 |
238 | #define TIMER_BASE3 0x1980 |
239 | #define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2] |
240 | |
f679add7 |
241 | static unsigned int gp2x_get_ticks_us_(void) |
b5bfb864 |
242 | { |
243 | TIMER_REG(0x08) = 0x4b; /* run timer, latch value */ |
244 | return TIMER_REG(0); |
245 | } |
246 | |
f679add7 |
247 | static unsigned int gp2x_get_ticks_ms_(void) |
b5bfb864 |
248 | { |
8af2da72 |
249 | /* approximate /= 1000 */ |
b5bfb864 |
250 | unsigned long long v64; |
8af2da72 |
251 | v64 = (unsigned long long)gp2x_get_ticks_us_() * 4294968; |
252 | return v64 >> 32; |
b5bfb864 |
253 | } |
254 | |
f679add7 |
255 | int pollux_get_real_snd_rate(int req_rate) |
256 | { |
257 | int clk0_src, clk1_src, rate, div; |
258 | |
259 | clk0_src = (memregl[0xdbc4>>2] >> 1) & 7; |
260 | clk1_src = (memregl[0xdbc8>>2] >> 1) & 7; |
261 | if (clk0_src > 1 || clk1_src != 7) { |
262 | fprintf(stderr, "get_real_snd_rate: bad clk sources: %d %d\n", clk0_src, clk1_src); |
263 | return req_rate; |
264 | } |
265 | |
266 | rate = decode_pll(clk0_src ? memregl[0xf008>>2] : memregl[0xf004>>2]); |
267 | |
268 | // apply divisors |
269 | div = ((memregl[0xdbc4>>2] >> 4) & 0x1f) + 1; |
270 | rate /= div; |
271 | div = ((memregl[0xdbc8>>2] >> 4) & 0x1f) + 1; |
272 | rate /= div; |
273 | rate /= 64; |
274 | |
275 | //printf("rate %d\n", rate); |
276 | rate -= rate * timer_drift / 1000000; |
277 | printf("adjusted rate: %d\n", rate); |
278 | |
279 | if (rate < 8000-1000 || rate > 44100+1000) { |
280 | fprintf(stderr, "get_real_snd_rate: got bad rate: %d\n", rate); |
281 | return req_rate; |
282 | } |
283 | |
284 | return rate; |
285 | } |
286 | |
d572cbad |
287 | void pollux_init(void) |
288 | { |
fa8d1331 |
289 | struct fb_fix_screeninfo fbfix; |
f679add7 |
290 | int i, ret, rate, timer_div; |
fa8d1331 |
291 | |
292 | memdev = open("/dev/mem", O_RDWR); |
293 | if (memdev == -1) { |
294 | perror("open(/dev/mem) failed"); |
295 | exit(1); |
296 | } |
297 | |
298 | memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000); |
299 | if (memregs == MAP_FAILED) { |
300 | perror("mmap(memregs) failed"); |
301 | exit(1); |
302 | } |
303 | memregl = (volatile void *)memregs; |
304 | |
305 | fbdev = open("/dev/fb0", O_RDWR); |
306 | if (fbdev < 0) { |
307 | perror("can't open fbdev"); |
308 | exit(1); |
309 | } |
310 | |
311 | ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix); |
312 | if (ret == -1) { |
313 | perror("ioctl(fbdev) failed"); |
314 | exit(1); |
315 | } |
316 | |
317 | printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start); |
318 | fb_paddr[0] = fbfix.smem_start; |
319 | |
320 | gp2x_screens[0] = mmap(0, 320*240*2*fb_buf_count, PROT_READ|PROT_WRITE, |
321 | MAP_SHARED, memdev, fb_paddr[0]); |
322 | if (gp2x_screens[0] == MAP_FAILED) |
323 | { |
324 | perror("mmap(gp2x_screens) failed"); |
325 | exit(1); |
326 | } |
327 | memset(gp2x_screens[0], 0, 320*240*2*fb_buf_count); |
328 | |
329 | printf(" %p -> %08x\n", gp2x_screens[0], fb_paddr[0]); |
330 | for (i = 1; i < fb_buf_count; i++) |
331 | { |
332 | fb_paddr[i] = fb_paddr[i-1] + 320*240*2; |
333 | gp2x_screens[i] = (char *)gp2x_screens[i-1] + 320*240*2; |
334 | printf(" %p -> %08x\n", gp2x_screens[i], fb_paddr[i]); |
335 | } |
336 | fb_work_buf = 0; |
337 | g_screen_ptr = gp2x_screens[0]; |
338 | |
053bef76 |
339 | battdev = open("/dev/pollux_batt", O_RDONLY); |
340 | if (battdev < 0) |
341 | perror("Warning: could't open pollux_batt"); |
342 | |
b6072c17 |
343 | /* find what PLL1 runs at, for the timer */ |
344 | rate = decode_pll(memregl[0xf008>>2]); |
345 | printf("PLL1 @ %dHz\n", rate); |
b6072c17 |
346 | |
b5bfb864 |
347 | /* setup timer */ |
f679add7 |
348 | timer_div = (rate + 500000) / 1000000; |
349 | if (1 <= timer_div && timer_div <= 256) { |
350 | timer_drift = (rate - (timer_div * 1000000)) / timer_div; |
351 | |
b6072c17 |
352 | if (TIMER_REG(0x08) & 8) { |
353 | fprintf(stderr, "warning: timer in use, overriding!\n"); |
354 | timer_cleanup(); |
355 | } |
356 | |
f679add7 |
357 | TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1, divide by it's rate */ |
b6072c17 |
358 | TIMER_REG(0x40) = 0x0c; /* clocks on */ |
359 | TIMER_REG(0x08) = 0x6b; /* run timer, clear irq, latch value */ |
360 | |
361 | gp2x_get_ticks_ms = gp2x_get_ticks_ms_; |
362 | gp2x_get_ticks_us = gp2x_get_ticks_us_; |
363 | } |
364 | else { |
365 | fprintf(stderr, "warning: could not make use of timer\n"); |
b5bfb864 |
366 | |
b6072c17 |
367 | // those functions are actually not good at all on Wiz kernel |
368 | gp2x_get_ticks_ms = plat_get_ticks_ms_good; |
369 | gp2x_get_ticks_us = plat_get_ticks_us_good; |
370 | } |
b5bfb864 |
371 | |
f679add7 |
372 | pllsetreg0_old = memregl[0xf004>>2]; |
71769e27 |
373 | memtimex_old[0] = memregs[0x14802>>1]; |
374 | memtimex_old[1] = memregs[0x14804>>1]; |
fa8d1331 |
375 | |
376 | gp2x_video_flip = gp2x_video_flip_; |
377 | gp2x_video_flip2 = gp2x_video_flip2_; |
378 | gp2x_video_changemode_ll = gp2x_video_changemode_ll_; |
379 | gp2x_video_setpalette = gp2x_video_setpalette_; |
380 | gp2x_video_RGB_setscaling = gp2x_video_RGB_setscaling_; |
381 | gp2x_video_wait_vsync = gp2x_video_wait_vsync_; |
382 | |
b6072c17 |
383 | /* some firmwares have sys clk on PLL0, we can't adjust CPU clock |
384 | * by reprogramming the PLL0 then, as it overclocks system bus */ |
385 | if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000) |
386 | gp2x_set_cpuclk = gp2x_set_cpuclk_; |
387 | else { |
388 | fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n", |
389 | memregl[0xf000>>2]); |
390 | gp2x_set_cpuclk = NULL; |
391 | } |
fa8d1331 |
392 | |
393 | set_lcd_custom_rate = set_lcd_custom_rate_; |
394 | unset_lcd_custom_rate = unset_lcd_custom_rate_; |
395 | set_lcd_gamma = set_lcd_gamma_; |
396 | |
397 | set_ram_timings = set_ram_timings_; |
398 | unset_ram_timings = unset_ram_timings_; |
053bef76 |
399 | gp2x_read_battery = gp2x_read_battery_; |
d572cbad |
400 | } |
401 | |
402 | void pollux_finish(void) |
403 | { |
fa8d1331 |
404 | /* switch to default fb mem, turn portrait off */ |
405 | memregl[0x406C>>2] = fb_paddr[0]; |
406 | memregl[0x4058>>2] |= 0x10; |
fa8d1331 |
407 | close(fbdev); |
408 | |
71769e27 |
409 | gp2x_video_changemode_ll_(16); |
410 | unset_ram_timings_(); |
411 | if (cpuclk_was_changed) { |
f679add7 |
412 | memregl[0xf004>>2] = pllsetreg0_old; |
71769e27 |
413 | memregl[0xf07c>>2] |= 0x8000; |
414 | } |
902972d1 |
415 | timer_cleanup(); |
71769e27 |
416 | |
fa8d1331 |
417 | munmap((void *)memregs, 0x20000); |
418 | close(memdev); |
053bef76 |
419 | if (battdev >= 0) |
420 | close(battdev); |
d572cbad |
421 | } |
afdbb7c8 |
422 | #endif |
423 | |
424 | /* note: both PLLs are programmed the same way, |
425 | * the databook incorrectly states that PLL1 differs */ |
426 | static int decode_pll(unsigned int reg) |
427 | { |
428 | long long v; |
429 | int p, m, s; |
430 | |
431 | p = (reg >> 18) & 0x3f; |
432 | m = (reg >> 8) & 0x3ff; |
433 | s = reg & 0xff; |
434 | |
435 | if (p == 0) |
436 | p = 1; |
437 | |
438 | v = 27000000; // master clock |
439 | v = v * m / (p << s); |
440 | return v; |
441 | } |
442 | |
443 | #define TIMER_BASE3 0x1980 |
444 | #define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2] |
445 | |
446 | static void timer_cleanup(void) |
447 | { |
448 | TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */ |
449 | TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */ |
450 | TIMER_REG(0x00) = 0; /* clear counter */ |
451 | TIMER_REG(0x40) = 0; /* clocks off */ |
452 | TIMER_REG(0x44) = 0; /* dividers back to default */ |
453 | } |
454 | |
455 | static void save_multiple_regs(unsigned int *dest, int base, int count) |
456 | { |
457 | const volatile unsigned int *regs = memregl + base / 4; |
458 | int i; |
459 | |
460 | for (i = 0; i < count; i++) |
461 | dest[i] = regs[i]; |
462 | } |
463 | |
464 | static void restore_multiple_regs(int base, const unsigned int *src, int count) |
465 | { |
466 | volatile unsigned int *regs = memregl + base / 4; |
467 | int i; |
468 | |
469 | for (i = 0; i < count; i++) |
470 | regs[i] = src[i]; |
471 | } |
472 | |
473 | /* newer API */ |
474 | static int pollux_cpu_clock_get(void) |
475 | { |
476 | return decode_pll(memregl[0xf004>>2]) / 1000000; |
477 | } |
478 | |
479 | int pollux_cpu_clock_set(int mhz) |
480 | { |
481 | int adiv, mdiv, pdiv, sdiv = 0; |
482 | int i, vf000, vf004; |
483 | |
484 | if (!cpu_clock_allowed) |
485 | return -1; |
486 | if (mhz == pollux_cpu_clock_get()) |
487 | return 0; |
488 | |
489 | // m = MDIV, p = PDIV, s = SDIV |
490 | #define SYS_CLK_FREQ 27 |
491 | pdiv = 9; |
492 | mdiv = (mhz * pdiv) / SYS_CLK_FREQ; |
493 | if (mdiv & ~0x3ff) |
494 | return -1; |
495 | vf004 = (pdiv<<18) | (mdiv<<8) | sdiv; |
496 | |
497 | // attempt to keep the AHB divider close to 250, but not higher |
498 | for (adiv = 1; mhz / adiv > 250; adiv++) |
499 | ; |
500 | |
501 | vf000 = memregl[0xf000>>2]; |
502 | vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6); |
503 | memregl[0xf000>>2] = vf000; |
504 | memregl[0xf004>>2] = vf004; |
505 | memregl[0xf07c>>2] |= 0x8000; |
506 | for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++) |
507 | ; |
508 | |
509 | printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv); |
510 | return 0; |
511 | } |
512 | |
513 | static int pollux_bat_capacity_get(void) |
514 | { |
515 | unsigned short magic_val = 0; |
516 | |
517 | if (battdev < 0) |
518 | return -1; |
519 | if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val)) |
520 | return -1; |
521 | switch (magic_val) { |
522 | default: |
523 | case 1: return 100; |
524 | case 2: return 66; |
525 | case 3: return 40; |
526 | case 4: return 0; |
527 | } |
528 | } |
529 | |
530 | static int step_volume(int is_up) |
531 | { |
532 | static int volume = 50; |
533 | int ret, val; |
534 | |
535 | if (mixerdev < 0) |
536 | return -1; |
537 | |
538 | if (is_up) { |
539 | volume += 5; |
540 | if (volume > 255) volume = 255; |
541 | } |
542 | else { |
543 | volume -= 5; |
544 | if (volume < 0) volume = 0; |
545 | } |
546 | val = volume; |
547 | val |= val << 8; |
548 | |
549 | ret = ioctl(mixerdev, SOUND_MIXER_WRITE_PCM, &val); |
550 | if (ret == -1) |
551 | perror("WRITE_PCM"); |
552 | |
553 | return ret; |
554 | } |
555 | |
556 | struct plat_target plat_target = { |
557 | pollux_cpu_clock_get, |
558 | pollux_cpu_clock_set, |
559 | pollux_bat_capacity_get, |
560 | |
561 | .step_volume = step_volume, |
562 | }; |
563 | |
564 | int plat_target_init(void) |
565 | { |
566 | int rate, timer_div, timer_div2; |
567 | FILE *f; |
568 | |
569 | memdev = open("/dev/mem", O_RDWR); |
570 | if (memdev == -1) { |
571 | perror("open(/dev/mem) failed"); |
572 | exit(1); |
573 | } |
574 | |
575 | memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, |
576 | memdev, 0xc0000000); |
577 | if (memregs == MAP_FAILED) { |
578 | perror("mmap(memregs) failed"); |
579 | exit(1); |
580 | } |
581 | memregl = (volatile void *)memregs; |
582 | |
583 | // save video regs of both MLCs |
584 | save_multiple_regs(saved_video_regs[0], 0x4058, ARRAY_SIZE(saved_video_regs[0])); |
585 | save_multiple_regs(saved_video_regs[1], 0x4458, ARRAY_SIZE(saved_video_regs[1])); |
586 | |
587 | /* some firmwares have sys clk on PLL0, we can't adjust CPU clock |
588 | * by reprogramming the PLL0 then, as it overclocks system bus */ |
589 | if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000) |
590 | cpu_clock_allowed = 1; |
591 | else { |
592 | cpu_clock_allowed = 0; |
593 | fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n", |
594 | memregl[0xf000>>2]); |
595 | } |
596 | |
597 | /* find what PLL1 runs at, for the timer */ |
598 | rate = decode_pll(memregl[0xf008>>2]); |
599 | printf("PLL1 @ %dHz\n", rate); |
600 | |
601 | /* setup timer */ |
602 | timer_div = (rate + 500000) / 1000000; |
603 | timer_div2 = 0; |
604 | while (timer_div > 256) { |
605 | timer_div /= 2; |
606 | timer_div2++; |
607 | } |
608 | if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) { |
609 | int timer_rate = (rate >> timer_div2) / timer_div; |
610 | if (TIMER_REG(0x08) & 8) { |
611 | fprintf(stderr, "warning: timer in use, overriding!\n"); |
612 | timer_cleanup(); |
613 | } |
614 | if (timer_rate != 1000000) |
615 | fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000); |
616 | |
617 | timer_div2 = (timer_div2 + 3) & 3; |
618 | TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */ |
619 | TIMER_REG(0x40) = 0x0c; /* clocks on */ |
620 | TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */ |
621 | } |
622 | else |
623 | fprintf(stderr, "warning: could not make use of timer\n"); |
624 | |
625 | battdev = open("/dev/pollux_batt", O_RDONLY); |
626 | if (battdev < 0) |
627 | perror("Warning: could't open pollux_batt"); |
628 | |
629 | f = fopen("/dev/accel", "rb"); |
630 | if (f) { |
631 | printf("detected Caanoo\n"); |
632 | gp2x_dev_id = GP2X_DEV_CAANOO; |
633 | fclose(f); |
634 | } |
635 | else { |
636 | printf("detected Wiz\n"); |
637 | gp2x_dev_id = GP2X_DEV_WIZ; |
638 | } |
639 | |
640 | mixerdev = open("/dev/mixer", O_RDWR); |
641 | if (mixerdev == -1) |
642 | perror("open(/dev/mixer)"); |
643 | |
644 | return 0; |
645 | } |
646 | |
647 | /* to be called after in_probe */ |
648 | void plat_target_setup_input(void) |
649 | { |
650 | } |
d572cbad |
651 | |
afdbb7c8 |
652 | void plat_target_finish(void) |
653 | { |
654 | timer_cleanup(); |
655 | |
656 | restore_multiple_regs(0x4058, saved_video_regs[0], |
657 | ARRAY_SIZE(saved_video_regs[0])); |
658 | restore_multiple_regs(0x4458, saved_video_regs[1], |
659 | ARRAY_SIZE(saved_video_regs[1])); |
660 | memregl[0x4058>>2] |= 0x10; |
661 | memregl[0x4458>>2] |= 0x10; |
662 | |
663 | if (battdev >= 0) |
664 | close(battdev); |
665 | if (mixerdev >= 0) |
666 | close(mixerdev); |
667 | munmap((void *)memregs, 0x20000); |
668 | close(memdev); |
669 | } |