f27b1cea |
1 | /* |
f89d8471 |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2009-2010 |
3 | * |
4 | * This work is licensed under the terms of any of these licenses |
5 | * (at your option): |
6 | * - GNU GPL, version 2 or later. |
7 | * - GNU LGPL, version 2.1 or later. |
8 | * - MAME license. |
9 | * See the COPYING file in the top-level directory. |
10 | * |
f27b1cea |
11 | * <random_info=mem_map> |
12 | * 00000000-029fffff linux (42MB) |
13 | * 02a00000-02dfffff fb (4MB, 153600B really used) |
14 | * 02e00000-02ffffff sound dma (2MB) |
15 | * 03000000-03ffffff MPEGDEC (?, 16MB) |
16 | * </random_info> |
17 | */ |
f89d8471 |
18 | |
fa8d1331 |
19 | #include <stdio.h> |
20 | #include <stdlib.h> |
21 | #include <string.h> |
fa8d1331 |
22 | #include <sys/types.h> |
23 | #include <sys/stat.h> |
24 | #include <fcntl.h> |
25 | #include <sys/mman.h> |
26 | #include <unistd.h> |
27 | #include <sys/ioctl.h> |
afdbb7c8 |
28 | #include <linux/soundcard.h> |
fa8d1331 |
29 | |
30 | #include "soc.h" |
31 | #include "plat_gp2x.h" |
9a5a0dc9 |
32 | #include "pollux_set.h" |
a86e9a3e |
33 | #include "../plat.h" |
fa8d1331 |
34 | |
afdbb7c8 |
35 | static int battdev = -1, mixerdev = -1; |
36 | static int cpu_clock_allowed; |
9a5a0dc9 |
37 | static unsigned short saved_memtimex[2]; |
afdbb7c8 |
38 | static unsigned int saved_video_regs[2][6]; |
7ceadd99 |
39 | static unsigned int timer_drift; // count per real second |
afdbb7c8 |
40 | |
41 | #ifndef ARRAY_SIZE |
42 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) |
43 | #endif |
44 | |
7ceadd99 |
45 | /* note: both PLLs are programmed the same way, |
46 | * the databook incorrectly states that PLL1 differs */ |
47 | static int decode_pll(unsigned int reg) |
fa8d1331 |
48 | { |
7ceadd99 |
49 | long long v; |
50 | int p, m, s; |
fa8d1331 |
51 | |
7ceadd99 |
52 | p = (reg >> 18) & 0x3f; |
53 | m = (reg >> 8) & 0x3ff; |
54 | s = reg & 0xff; |
fa8d1331 |
55 | |
7ceadd99 |
56 | if (p == 0) |
57 | p = 1; |
fa8d1331 |
58 | |
7ceadd99 |
59 | v = 27000000; // master clock |
60 | v = v * m / (p << s); |
61 | return v; |
fa8d1331 |
62 | } |
63 | |
9a5a0dc9 |
64 | /* RAM timings */ |
65 | static void set_ram_timings(void) |
66 | { |
67 | pollux_set_fromenv(memregs, "POLLUX_RAM_TIMINGS"); |
68 | } |
69 | |
70 | static void unset_ram_timings(void) |
71 | { |
72 | int i; |
73 | |
74 | memregs[0x14802>>1] = saved_memtimex[0]; |
75 | memregs[0x14804>>1] = saved_memtimex[1] | 0x8000; |
76 | |
77 | for (i = 0; i < 0x100000; i++) |
78 | if (!(memregs[0x14804>>1] & 0x8000)) |
79 | break; |
80 | |
81 | printf("RAM timings reset to startup values.\n"); |
82 | } |
83 | |
7ceadd99 |
84 | #define TIMER_BASE3 0x1980 |
85 | #define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2] |
fa8d1331 |
86 | |
7ceadd99 |
87 | static unsigned int gp2x_get_ticks_us_(void) |
fa8d1331 |
88 | { |
7ceadd99 |
89 | TIMER_REG(0x08) = 0x4b; /* run timer, latch value */ |
90 | return TIMER_REG(0); |
fa8d1331 |
91 | } |
92 | |
7ceadd99 |
93 | static unsigned int gp2x_get_ticks_ms_(void) |
fa8d1331 |
94 | { |
7ceadd99 |
95 | /* approximate /= 1000 */ |
96 | unsigned long long v64; |
97 | v64 = (unsigned long long)gp2x_get_ticks_us_() * 4294968; |
98 | return v64 >> 32; |
fa8d1331 |
99 | } |
100 | |
7ceadd99 |
101 | static void timer_cleanup(void) |
fa8d1331 |
102 | { |
7ceadd99 |
103 | TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */ |
104 | TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */ |
105 | TIMER_REG(0x00) = 0; /* clear counter */ |
106 | TIMER_REG(0x40) = 0; /* clocks off */ |
107 | TIMER_REG(0x44) = 0; /* dividers back to default */ |
fa8d1331 |
108 | } |
109 | |
7ceadd99 |
110 | static void save_multiple_regs(unsigned int *dest, int base, int count) |
fa8d1331 |
111 | { |
7ceadd99 |
112 | const volatile unsigned int *regs = memregl + base / 4; |
fa8d1331 |
113 | int i; |
114 | |
7ceadd99 |
115 | for (i = 0; i < count; i++) |
116 | dest[i] = regs[i]; |
053bef76 |
117 | } |
118 | |
7ceadd99 |
119 | static void restore_multiple_regs(int base, const unsigned int *src, int count) |
b5bfb864 |
120 | { |
7ceadd99 |
121 | volatile unsigned int *regs = memregl + base / 4; |
122 | int i; |
b5bfb864 |
123 | |
7ceadd99 |
124 | for (i = 0; i < count; i++) |
125 | regs[i] = src[i]; |
b5bfb864 |
126 | } |
127 | |
f679add7 |
128 | int pollux_get_real_snd_rate(int req_rate) |
129 | { |
130 | int clk0_src, clk1_src, rate, div; |
131 | |
132 | clk0_src = (memregl[0xdbc4>>2] >> 1) & 7; |
133 | clk1_src = (memregl[0xdbc8>>2] >> 1) & 7; |
134 | if (clk0_src > 1 || clk1_src != 7) { |
135 | fprintf(stderr, "get_real_snd_rate: bad clk sources: %d %d\n", clk0_src, clk1_src); |
136 | return req_rate; |
137 | } |
138 | |
139 | rate = decode_pll(clk0_src ? memregl[0xf008>>2] : memregl[0xf004>>2]); |
140 | |
141 | // apply divisors |
11166a22 |
142 | div = ((memregl[0xdbc4>>2] >> 4) & 0x3f) + 1; |
f679add7 |
143 | rate /= div; |
11166a22 |
144 | div = ((memregl[0xdbc8>>2] >> 4) & 0x3f) + 1; |
f679add7 |
145 | rate /= div; |
146 | rate /= 64; |
147 | |
148 | //printf("rate %d\n", rate); |
149 | rate -= rate * timer_drift / 1000000; |
150 | printf("adjusted rate: %d\n", rate); |
151 | |
152 | if (rate < 8000-1000 || rate > 44100+1000) { |
153 | fprintf(stderr, "get_real_snd_rate: got bad rate: %d\n", rate); |
154 | return req_rate; |
155 | } |
156 | |
157 | return rate; |
158 | } |
159 | |
afdbb7c8 |
160 | /* newer API */ |
161 | static int pollux_cpu_clock_get(void) |
162 | { |
163 | return decode_pll(memregl[0xf004>>2]) / 1000000; |
164 | } |
165 | |
166 | int pollux_cpu_clock_set(int mhz) |
167 | { |
168 | int adiv, mdiv, pdiv, sdiv = 0; |
169 | int i, vf000, vf004; |
170 | |
171 | if (!cpu_clock_allowed) |
172 | return -1; |
173 | if (mhz == pollux_cpu_clock_get()) |
174 | return 0; |
175 | |
176 | // m = MDIV, p = PDIV, s = SDIV |
177 | #define SYS_CLK_FREQ 27 |
178 | pdiv = 9; |
179 | mdiv = (mhz * pdiv) / SYS_CLK_FREQ; |
180 | if (mdiv & ~0x3ff) |
181 | return -1; |
182 | vf004 = (pdiv<<18) | (mdiv<<8) | sdiv; |
183 | |
184 | // attempt to keep the AHB divider close to 250, but not higher |
185 | for (adiv = 1; mhz / adiv > 250; adiv++) |
186 | ; |
187 | |
188 | vf000 = memregl[0xf000>>2]; |
189 | vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6); |
190 | memregl[0xf000>>2] = vf000; |
191 | memregl[0xf004>>2] = vf004; |
192 | memregl[0xf07c>>2] |= 0x8000; |
193 | for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++) |
194 | ; |
195 | |
196 | printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv); |
197 | return 0; |
198 | } |
199 | |
200 | static int pollux_bat_capacity_get(void) |
201 | { |
202 | unsigned short magic_val = 0; |
203 | |
204 | if (battdev < 0) |
205 | return -1; |
206 | if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val)) |
207 | return -1; |
208 | switch (magic_val) { |
209 | default: |
210 | case 1: return 100; |
211 | case 2: return 66; |
212 | case 3: return 40; |
213 | case 4: return 0; |
214 | } |
215 | } |
216 | |
7ceadd99 |
217 | static int step_volume(int *volume, int diff) |
afdbb7c8 |
218 | { |
afdbb7c8 |
219 | int ret, val; |
220 | |
221 | if (mixerdev < 0) |
222 | return -1; |
223 | |
7ceadd99 |
224 | *volume += diff; |
225 | if (*volume > 255) |
226 | *volume = 255; |
227 | else if (*volume < 0) |
228 | *volume = 0; |
229 | |
230 | val = *volume; |
afdbb7c8 |
231 | val |= val << 8; |
232 | |
233 | ret = ioctl(mixerdev, SOUND_MIXER_WRITE_PCM, &val); |
7ceadd99 |
234 | if (ret == -1) { |
afdbb7c8 |
235 | perror("WRITE_PCM"); |
7ceadd99 |
236 | return ret; |
237 | } |
afdbb7c8 |
238 | |
7ceadd99 |
239 | return 0; |
afdbb7c8 |
240 | } |
241 | |
7ceadd99 |
242 | void pollux_init(void) |
afdbb7c8 |
243 | { |
244 | int rate, timer_div, timer_div2; |
afdbb7c8 |
245 | |
246 | memdev = open("/dev/mem", O_RDWR); |
247 | if (memdev == -1) { |
248 | perror("open(/dev/mem) failed"); |
249 | exit(1); |
250 | } |
251 | |
252 | memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, |
253 | memdev, 0xc0000000); |
254 | if (memregs == MAP_FAILED) { |
255 | perror("mmap(memregs) failed"); |
256 | exit(1); |
257 | } |
258 | memregl = (volatile void *)memregs; |
259 | |
9a5a0dc9 |
260 | saved_memtimex[0] = memregs[0x14802>>1]; |
261 | saved_memtimex[1] = memregs[0x14804>>1]; |
262 | |
263 | set_ram_timings(); |
264 | |
afdbb7c8 |
265 | // save video regs of both MLCs |
266 | save_multiple_regs(saved_video_regs[0], 0x4058, ARRAY_SIZE(saved_video_regs[0])); |
267 | save_multiple_regs(saved_video_regs[1], 0x4458, ARRAY_SIZE(saved_video_regs[1])); |
268 | |
269 | /* some firmwares have sys clk on PLL0, we can't adjust CPU clock |
270 | * by reprogramming the PLL0 then, as it overclocks system bus */ |
271 | if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000) |
272 | cpu_clock_allowed = 1; |
273 | else { |
274 | cpu_clock_allowed = 0; |
275 | fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n", |
276 | memregl[0xf000>>2]); |
277 | } |
278 | |
279 | /* find what PLL1 runs at, for the timer */ |
280 | rate = decode_pll(memregl[0xf008>>2]); |
281 | printf("PLL1 @ %dHz\n", rate); |
282 | |
283 | /* setup timer */ |
284 | timer_div = (rate + 500000) / 1000000; |
285 | timer_div2 = 0; |
286 | while (timer_div > 256) { |
287 | timer_div /= 2; |
288 | timer_div2++; |
289 | } |
290 | if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) { |
291 | int timer_rate = (rate >> timer_div2) / timer_div; |
292 | if (TIMER_REG(0x08) & 8) { |
293 | fprintf(stderr, "warning: timer in use, overriding!\n"); |
294 | timer_cleanup(); |
295 | } |
7ceadd99 |
296 | timer_drift = timer_rate - 1000000; |
297 | if (timer_drift != 0) |
298 | fprintf(stderr, "warning: timer drift %d us\n", |
299 | timer_drift); |
afdbb7c8 |
300 | |
301 | timer_div2 = (timer_div2 + 3) & 3; |
302 | TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */ |
303 | TIMER_REG(0x40) = 0x0c; /* clocks on */ |
304 | TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */ |
305 | } |
7ceadd99 |
306 | else { |
afdbb7c8 |
307 | fprintf(stderr, "warning: could not make use of timer\n"); |
308 | |
7ceadd99 |
309 | // those functions are actually not good at all on Wiz kernel |
310 | gp2x_get_ticks_ms = plat_get_ticks_ms_good; |
311 | gp2x_get_ticks_us = plat_get_ticks_us_good; |
312 | } |
313 | |
afdbb7c8 |
314 | battdev = open("/dev/pollux_batt", O_RDONLY); |
315 | if (battdev < 0) |
316 | perror("Warning: could't open pollux_batt"); |
317 | |
afdbb7c8 |
318 | mixerdev = open("/dev/mixer", O_RDWR); |
319 | if (mixerdev == -1) |
320 | perror("open(/dev/mixer)"); |
321 | |
7ceadd99 |
322 | plat_target.cpu_clock_get = pollux_cpu_clock_get; |
323 | plat_target.cpu_clock_set = pollux_cpu_clock_set; |
324 | plat_target.bat_capacity_get = pollux_bat_capacity_get; |
325 | plat_target.step_volume = step_volume; |
afdbb7c8 |
326 | |
7ceadd99 |
327 | gp2x_get_ticks_ms = gp2x_get_ticks_ms_; |
328 | gp2x_get_ticks_us = gp2x_get_ticks_us_; |
afdbb7c8 |
329 | } |
d572cbad |
330 | |
7ceadd99 |
331 | void pollux_finish(void) |
afdbb7c8 |
332 | { |
333 | timer_cleanup(); |
334 | |
9a5a0dc9 |
335 | unset_ram_timings(); |
336 | |
afdbb7c8 |
337 | restore_multiple_regs(0x4058, saved_video_regs[0], |
338 | ARRAY_SIZE(saved_video_regs[0])); |
339 | restore_multiple_regs(0x4458, saved_video_regs[1], |
340 | ARRAY_SIZE(saved_video_regs[1])); |
341 | memregl[0x4058>>2] |= 0x10; |
342 | memregl[0x4458>>2] |= 0x10; |
343 | |
344 | if (battdev >= 0) |
345 | close(battdev); |
346 | if (mixerdev >= 0) |
347 | close(mixerdev); |
348 | munmap((void *)memregs, 0x20000); |
349 | close(memdev); |
350 | } |