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1 | #include "new_dynarec.h" |
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2 | #include "../r3000a.h" |
3 | |
4 | extern char invalid_code[0x100000]; |
5 | |
6 | /* weird stuff */ |
7 | #define EAX 0 |
8 | #define ECX 1 |
9 | |
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10 | extern int dynarec_local[]; |
11 | |
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12 | /* same as psxRegs.GPR.n.* */ |
13 | extern int hi, lo; |
14 | |
15 | /* same as psxRegs.CP0.n.* */ |
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16 | extern int reg_cop0[]; |
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17 | #define Status psxRegs.CP0.n.Status |
18 | #define Cause psxRegs.CP0.n.Cause |
19 | #define EPC psxRegs.CP0.n.EPC |
20 | #define BadVAddr psxRegs.CP0.n.BadVAddr |
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21 | #define Count psxRegs.cycle // psxRegs.CP0.n.Count |
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22 | |
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23 | /* COP2/GTE */ |
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24 | enum gte_opcodes { |
25 | GTE_RTPS = 0x01, |
26 | GTE_NCLIP = 0x06, |
27 | GTE_OP = 0x0c, |
28 | GTE_DPCS = 0x10, |
29 | GTE_INTPL = 0x11, |
30 | GTE_MVMVA = 0x12, |
31 | GTE_NCDS = 0x13, |
32 | GTE_CDP = 0x14, |
33 | GTE_NCDT = 0x16, |
34 | GTE_NCCS = 0x1b, |
35 | GTE_CC = 0x1c, |
36 | GTE_NCS = 0x1e, |
37 | GTE_NCT = 0x20, |
38 | GTE_SQR = 0x28, |
39 | GTE_DCPL = 0x29, |
40 | GTE_DPCT = 0x2a, |
41 | GTE_AVSZ3 = 0x2d, |
42 | GTE_AVSZ4 = 0x2e, |
43 | GTE_RTPT = 0x30, |
44 | GTE_GPF = 0x3d, |
45 | GTE_GPL = 0x3e, |
46 | GTE_NCCT = 0x3f, |
47 | }; |
48 | |
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49 | extern int reg_cop2d[], reg_cop2c[]; |
50 | extern void *gte_handlers[64]; |
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51 | extern void *gte_handlers_nf[64]; |
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52 | extern const char *gte_regnames[64]; |
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53 | extern const uint64_t gte_reg_reads[64]; |
54 | extern const uint64_t gte_reg_writes[64]; |
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55 | |
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56 | /* mem */ |
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57 | extern void *mem_rtab; |
58 | extern void *mem_wtab; |
59 | |
60 | void jump_handler_read8(u32 addr, u32 *table, u32 cycles); |
61 | void jump_handler_read16(u32 addr, u32 *table, u32 cycles); |
62 | void jump_handler_read32(u32 addr, u32 *table, u32 cycles); |
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63 | void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table); |
64 | void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table); |
65 | void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table); |
66 | void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler); |
67 | void jump_handle_swl(u32 addr, u32 data, u32 cycles); |
68 | void jump_handle_swr(u32 addr, u32 data, u32 cycles); |
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69 | u32 rcnt0_read_count_m0(u32 addr, u32, u32 cycles); |
70 | u32 rcnt0_read_count_m1(u32 addr, u32, u32 cycles); |
71 | u32 rcnt1_read_count_m0(u32 addr, u32, u32 cycles); |
72 | u32 rcnt1_read_count_m1(u32 addr, u32, u32 cycles); |
73 | u32 rcnt2_read_count_m0(u32 addr, u32, u32 cycles); |
74 | u32 rcnt2_read_count_m1(u32 addr, u32, u32 cycles); |
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75 | |
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76 | extern unsigned int address; |
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77 | extern unsigned int hack_addr; |
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78 | extern void *psxH_ptr; |
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79 | extern void *zeromem_ptr; |
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80 | extern void *scratch_buf_ptr; |
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81 | |
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82 | // same as invalid_code, just a region for ram write checks (inclusive) |
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83 | // (psx/guest address range) |
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84 | extern u32 inv_code_start, inv_code_end; |
85 | |
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86 | /* cycles/irqs */ |
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87 | extern u32 next_interupt; |
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88 | extern int pending_exception; |
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89 | |
90 | /* called by drc */ |
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91 | void pcsx_mtc0(u32 reg, u32 val); |
92 | void pcsx_mtc0_ds(u32 reg, u32 val); |
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93 | |
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94 | /* misc */ |
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95 | extern void SysPrintf(const char *fmt, ...); |
96 | |
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97 | #define rdram ((u_char *)psxM) |