a151a8d8 |
1 | diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c |
2330734f |
2 | index 90c4660..441eaca 100644 |
a151a8d8 |
3 | --- a/libpcsxcore/new_dynarec/emu_if.c |
4 | +++ b/libpcsxcore/new_dynarec/emu_if.c |
37387d8b |
5 | @@ -424,13 +424,17 @@ static void ari64_shutdown() |
a151a8d8 |
6 | { |
7 | new_dynarec_cleanup(); |
8 | new_dyna_pcsx_mem_shutdown(); |
9 | + (void)ari64_execute; |
10 | } |
11 | |
12 | +extern void intExecuteT(); |
13 | +extern void intExecuteBlockT(); |
14 | + |
15 | R3000Acpu psxRec = { |
16 | ari64_init, |
17 | ari64_reset, |
18 | - ari64_execute, |
19 | - ari64_execute_until, |
20 | + intExecuteT, |
21 | + intExecuteBlockT, |
22 | ari64_clear, |
a151a8d8 |
23 | ari64_notify, |
37387d8b |
24 | ari64_apply_config, |
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25 | @@ -501,7 +505,7 @@ static u32 memcheck_read(u32 a) |
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26 | return *(u32 *)(psxM + (a & 0x1ffffc)); |
27 | } |
28 | |
29 | -#if 0 |
30 | +#if 1 |
31 | void do_insn_trace(void) |
32 | { |
33 | static psxRegisters oldregs; |
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34 | diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c |
35 | index bb471b6..8f68a3b 100644 |
36 | --- a/libpcsxcore/new_dynarec/pcsxmem.c |
37 | +++ b/libpcsxcore/new_dynarec/pcsxmem.c |
38 | @@ -272,6 +272,8 @@ static void write_biu(u32 value) |
39 | if (address != 0xfffe0130) |
40 | return; |
41 | |
42 | +extern u32 handler_cycle; |
43 | +handler_cycle = psxRegs.cycle; |
44 | switch (value) { |
45 | case 0x800: case 0x804: |
46 | unmap_ram_write(); |
47 | diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c |
48 | index b2cc07b..f916580 100644 |
49 | --- a/libpcsxcore/psxcounters.c |
50 | +++ b/libpcsxcore/psxcounters.c |
51 | @@ -378,9 +378,12 @@ void psxRcntUpdate() |
52 | |
53 | /******************************************************************************/ |
54 | |
55 | +extern u32 handler_cycle; |
56 | + |
57 | void psxRcntWcount( u32 index, u32 value ) |
58 | { |
59 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); |
60 | +handler_cycle = psxRegs.cycle; |
61 | |
62 | _psxRcntWcount( index, value ); |
63 | psxRcntSet(); |
64 | @@ -389,6 +392,7 @@ void psxRcntWcount( u32 index, u32 value ) |
65 | void psxRcntWmode( u32 index, u32 value ) |
66 | { |
67 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); |
68 | +handler_cycle = psxRegs.cycle; |
69 | |
70 | _psxRcntWmode( index, value ); |
71 | _psxRcntWcount( index, 0 ); |
72 | @@ -400,6 +404,7 @@ void psxRcntWmode( u32 index, u32 value ) |
73 | void psxRcntWtarget( u32 index, u32 value ) |
74 | { |
75 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); |
76 | +handler_cycle = psxRegs.cycle; |
77 | |
78 | rcnts[index].target = value; |
79 | |
80 | @@ -412,6 +417,7 @@ void psxRcntWtarget( u32 index, u32 value ) |
81 | u32 psxRcntRcount( u32 index ) |
82 | { |
83 | u32 count; |
84 | +handler_cycle = psxRegs.cycle; |
85 | |
86 | count = _psxRcntRcount( index ); |
87 | |
a151a8d8 |
88 | diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c |
89 | index dbcb989..0716f5e 100644 |
90 | --- a/libpcsxcore/psxhw.c |
91 | +++ b/libpcsxcore/psxhw.c |
92 | @@ -373,13 +373,14 @@ void psxHwWrite8(u32 add, u8 value) { |
93 | case 0x1f801803: cdrWrite3(value); break; |
94 | |
95 | default: |
96 | + if (add < 0x1f802000) |
97 | psxHu8(add) = value; |
98 | #ifdef PSXHW_LOG |
99 | PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value); |
100 | #endif |
101 | return; |
102 | } |
103 | - psxHu8(add) = value; |
104 | + //psxHu8(add) = value; |
105 | #ifdef PSXHW_LOG |
106 | PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value); |
107 | #endif |
108 | @@ -504,6 +505,7 @@ void psxHwWrite16(u32 add, u16 value) { |
109 | return; |
110 | } |
111 | |
112 | + if (add < 0x1f802000) |
113 | psxHu16ref(add) = SWAPu16(value); |
114 | #ifdef PSXHW_LOG |
115 | PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value); |
116 | @@ -699,9 +701,9 @@ void psxHwWrite32(u32 add, u32 value) { |
117 | return; |
118 | |
119 | case 0x1f801820: |
120 | - mdecWrite0(value); break; |
121 | + mdecWrite0(value); return; |
122 | case 0x1f801824: |
123 | - mdecWrite1(value); break; |
124 | + mdecWrite1(value); return; |
125 | |
126 | case 0x1f801100: |
127 | #ifdef PSXHW_LOG |
128 | @@ -759,6 +761,7 @@ void psxHwWrite32(u32 add, u32 value) { |
129 | return; |
130 | } |
131 | |
132 | + if (add < 0x1f802000) |
133 | psxHu32ref(add) = SWAPu32(value); |
134 | #ifdef PSXHW_LOG |
135 | PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value); |
136 | diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c |
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137 | index f7898e9..1f125ed 100644 |
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138 | --- a/libpcsxcore/psxinterpreter.c |
139 | +++ b/libpcsxcore/psxinterpreter.c |
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140 | @@ -466,6 +466,8 @@ static void doBranch(u32 tar) { |
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141 | psxRegs.pc += 4; |
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142 | psxRegs.cycle += BIAS; |
a151a8d8 |
143 | |
144 | + (void)tmp; |
145 | +#if 0 |
146 | // check for load delay |
147 | tmp = psxRegs.code >> 26; |
148 | switch (tmp) { |
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149 | @@ -499,13 +501,15 @@ static void doBranch(u32 tar) { |
a151a8d8 |
150 | } |
151 | break; |
152 | } |
153 | - |
154 | +#endif |
155 | psxBSC[psxRegs.code >> 26](); |
156 | |
157 | branch = 0; |
158 | psxRegs.pc = branchPC; |
159 | |
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160 | + psxRegs.cycle += BIAS; |
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161 | psxBranchTest(); |
162 | + psxRegs.cycle -= BIAS; |
a151a8d8 |
163 | } |
164 | |
165 | /********************************************************* |
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166 | @@ -615,12 +619,13 @@ void psxMULTU_stall() { |
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167 | psxMULTU(); |
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168 | } |
169 | |
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170 | +#define doBranchNotTaken() do { psxRegs.cycle += BIAS; execI(); psxBranchTest(); psxRegs.cycle -= BIAS; } while(0) |
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171 | /********************************************************* |
172 | * Register branch logic * |
173 | * Format: OP rs, offset * |
174 | *********************************************************/ |
175 | -#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); |
176 | -#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } } |
177 | +#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); else doBranchNotTaken(); |
178 | +#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } else doBranchNotTaken(); } |
179 | |
180 | void psxBGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0 |
181 | void psxBGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link |
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182 | @@ -702,7 +707,7 @@ void psxRFE() { |
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183 | * Register branch logic * |
184 | * Format: OP rs, rt, offset * |
185 | *********************************************************/ |
186 | -#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); |
187 | +#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); else doBranchNotTaken(); |
188 | |
189 | void psxBEQ() { RepBranchi32(==) } // Branch if Rs == Rt |
190 | void psxBNE() { RepBranchi32(!=) } // Branch if Rs != Rt |
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191 | @@ -886,6 +891,7 @@ void MTC0(int reg, u32 val) { |
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192 | case 12: // Status |
193 | psxRegs.CP0.r[12] = val; |
194 | psxTestSWInts(); |
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195 | + //psxBranchTest(); |
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196 | break; |
197 | |
198 | case 13: // Cause |
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199 | @@ -1027,6 +1033,23 @@ void intExecuteBlock() { |
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200 | while (!branch2) execI(); |
201 | } |
202 | |
203 | +extern void do_insn_trace(void); |
204 | + |
205 | +void intExecuteT() { |
206 | + for (;;) { |
207 | + do_insn_trace(); |
208 | + execI(); |
209 | + } |
210 | +} |
211 | + |
212 | +void intExecuteBlockT() { |
213 | + branch2 = 0; |
214 | + while (!branch2) { |
215 | + do_insn_trace(); |
216 | + execI(); |
217 | + } |
218 | +} |
219 | + |
220 | static void intClear(u32 Addr, u32 Size) { |
221 | } |
222 | |
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223 | @@ -1049,7 +1072,7 @@ void intApplyConfig() { |
224 | assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall); |
225 | assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall); |
226 | |
227 | - if (Config.DisableStalls) { |
228 | + if (1) { |
229 | psxBSC[18] = psxCOP2; |
230 | psxBSC[50] = gteLWC2; |
231 | psxBSC[58] = gteSWC2; |
232 | @@ -1091,9 +1114,10 @@ void execI() { |
233 | if (Config.Debug) ProcessDebug(); |
234 | |
235 | psxRegs.pc += 4; |
236 | - psxRegs.cycle += BIAS; |
237 | |
238 | psxBSC[psxRegs.code >> 26](); |
239 | + |
240 | + psxRegs.cycle += BIAS; |
241 | } |
242 | |
243 | R3000Acpu psxInt = { |
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244 | diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c |
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245 | index 04aeec2..710a379 100644 |
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246 | --- a/libpcsxcore/psxmem.c |
247 | +++ b/libpcsxcore/psxmem.c |
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248 | @@ -217,11 +217,13 @@ void psxMemShutdown() { |
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249 | } |
250 | |
251 | static int writeok = 1; |
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252 | +extern u32 last_io_addr; |
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253 | |
254 | u8 psxMemRead8(u32 mem) { |
255 | char *p; |
256 | u32 t; |
257 | |
258 | + last_io_addr = mem; |
259 | t = mem >> 16; |
260 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
261 | if ((mem & 0xffff) < 0x400) |
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262 | @@ -247,6 +249,7 @@ u16 psxMemRead16(u32 mem) { |
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263 | char *p; |
264 | u32 t; |
265 | |
266 | + last_io_addr = mem; |
267 | t = mem >> 16; |
268 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
269 | if ((mem & 0xffff) < 0x400) |
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270 | @@ -272,6 +275,7 @@ u32 psxMemRead32(u32 mem) { |
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271 | char *p; |
272 | u32 t; |
273 | |
274 | + last_io_addr = mem; |
275 | t = mem >> 16; |
276 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
277 | if ((mem & 0xffff) < 0x400) |
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278 | @@ -297,6 +301,7 @@ void psxMemWrite8(u32 mem, u8 value) { |
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279 | char *p; |
280 | u32 t; |
281 | |
282 | + last_io_addr = mem; |
283 | t = mem >> 16; |
284 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
285 | if ((mem & 0xffff) < 0x400) |
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286 | @@ -324,6 +329,7 @@ void psxMemWrite16(u32 mem, u16 value) { |
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287 | char *p; |
288 | u32 t; |
289 | |
290 | + last_io_addr = mem; |
291 | t = mem >> 16; |
292 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
293 | if ((mem & 0xffff) < 0x400) |
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294 | @@ -351,6 +357,7 @@ void psxMemWrite32(u32 mem, u32 value) { |
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295 | char *p; |
296 | u32 t; |
297 | |
298 | + last_io_addr = mem; |
299 | // if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n"); |
300 | t = mem >> 16; |
301 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
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302 | @@ -380,6 +387,8 @@ void psxMemWrite32(u32 mem, u32 value) { |
303 | } else { |
304 | int i; |
305 | |
306 | +extern u32 handler_cycle; |
307 | +handler_cycle = psxRegs.cycle; |
308 | switch (value) { |
309 | case 0x800: case 0x804: |
310 | if (writeok == 0) break; |
311 | diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c |
312 | index 7e6f16b..0114947 100644 |
313 | --- a/libpcsxcore/r3000a.c |
314 | +++ b/libpcsxcore/r3000a.c |
315 | @@ -120,6 +120,8 @@ void psxException(u32 code, u32 bd) { |
316 | } |
317 | |
318 | void psxBranchTest() { |
319 | + extern u32 irq_test_cycle; |
320 | + irq_test_cycle = psxRegs.cycle; |
321 | if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter) |
322 | psxRcntUpdate(); |
323 | |