[pcsx_rearmed.git] / libpcsxcore / new_dynarec / patches / trace_intr

diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index f879ad8c..0ec366d0 100644
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -323,13 +323,18 @@ static void ari64_shutdown()
 {
 	new_dynarec_cleanup();
 	new_dyna_pcsx_mem_shutdown();
+	(void)ari64_execute;
+	(void)ari64_execute_block;
 }
 
+extern void intExecuteT();
+extern void intExecuteBlockT();
+
 R3000Acpu psxRec = {
 	ari64_init,
 	ari64_reset,
-	ari64_execute,
-	ari64_execute_block,
+	intExecuteT,
+	intExecuteBlockT,
 	ari64_clear,
 	ari64_notify,
 	ari64_apply_config,
@@ -398,7 +403,7 @@ static u32 memcheck_read(u32 a)
 	return *(u32 *)(psxM + (a & 0x1ffffc));
 }
 
-#if 0
+#if 1
 void do_insn_trace(void)
 {
 	static psxRegisters oldregs;
diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index 1f37dc29..357f753e 100644
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -289,6 +289,8 @@ static void write_biu(u32 value)
 		return;
 	}
 
+extern u32 handler_cycle;
+handler_cycle = psxRegs.cycle;
 	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
 	psxRegs.biuReg = value;
 }
diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
index 18bd6a4e..bc2eb3f6 100644
--- a/libpcsxcore/psxcounters.c
+++ b/libpcsxcore/psxcounters.c
@@ -389,9 +389,12 @@ void psxRcntUpdate()
 
 /******************************************************************************/
 
+extern u32 handler_cycle;
+
 void psxRcntWcount( u32 index, u32 value )
 {
     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     _psxRcntWcount( index, value );
     psxRcntSet();
@@ -400,6 +403,7 @@ void psxRcntWcount( u32 index, u32 value )
 void psxRcntWmode( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     _psxRcntWmode( index, value );
     _psxRcntWcount( index, 0 );
@@ -411,6 +415,7 @@ void psxRcntWmode( u32 index, u32 value )
 void psxRcntWtarget( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     rcnts[index].target = value;
 
@@ -423,6 +428,7 @@ void psxRcntWtarget( u32 index, u32 value )
 u32 psxRcntRcount( u32 index )
 {
     u32 count;
+handler_cycle = psxRegs.cycle;
 
     count = _psxRcntRcount( index );
 
diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
index 10a2695f..7e4a64da 100644
--- a/libpcsxcore/psxhw.c
+++ b/libpcsxcore/psxhw.c
@@ -437,13 +437,14 @@ void psxHwWrite8(u32 add, u8 value) {
 				return;
 			}
 
+			if (add < 0x1f802000)
 			psxHu8(add) = value;
 #ifdef PSXHW_LOG
 			PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
 #endif
 			return;
 	}
-	psxHu8(add) = value;
+	//psxHu8(add) = value;
 #ifdef PSXHW_LOG
 	PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
 #endif
@@ -565,6 +566,7 @@ void psxHwWrite16(u32 add, u16 value) {
 				return;
 			}
 
+			if (add < 0x1f802000)
 			psxHu16ref(add) = SWAPu16(value);
 #ifdef PSXHW_LOG
 			PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
@@ -756,9 +758,9 @@ void psxHwWrite32(u32 add, u32 value) {
 			return;
 
 		case 0x1f801820:
-			mdecWrite0(value); break;
+			mdecWrite0(value); return;
 		case 0x1f801824:
-			mdecWrite1(value); break;
+			mdecWrite1(value); return;
 
 		case 0x1f801100:
 #ifdef PSXHW_LOG
@@ -826,6 +828,7 @@ void psxHwWrite32(u32 add, u32 value) {
 				return;
 			}
 
+			if (add < 0x1f802000)
 			psxHu32ref(add) = SWAPu32(value);
 #ifdef PSXHW_LOG
 			PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 5756bee5..4bf9248d 100644
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -238,7 +238,7 @@ static inline void addCycle(psxRegisters *regs)
 {
 	assert(regs->subCycleStep >= 0x10000);
 	regs->subCycle += regs->subCycleStep;
-	regs->cycle += regs->subCycle >> 16;
+	regs->cycle += 2; //regs->subCycle >> 16;
 	regs->subCycle &= 0xffff;
 }
 
@@ -435,7 +435,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
 		regs->CP0.n.Target = pc_final;
 	regs->branching = 0;
 
+	psxRegs.cycle += 2;
 	psxBranchTest();
+	psxRegs.cycle -= 2;
 }
 
 static void doBranchReg(psxRegisters *regs, u32 tar) {
@@ -960,7 +962,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
 	}
 }
 
-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
+OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); }
 
 // no exception
 static inline void psxNULLne(psxRegisters *regs) {
@@ -1120,6 +1122,7 @@ OP(psxHLE) {
 	}
 	psxHLEt[hleCode]();
 	branchSeen = 1;
+	psxRegs.cycle -= 2;
 }
 
 static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
@@ -1169,18 +1172,20 @@ static void intReset() {
 static inline void execI_(u8 **memRLUT, psxRegisters *regs) {
 	u32 pc = regs->pc;
 
-	addCycle(regs);
+	//addCycle(regs);
 	dloadStep(regs);
 
 	regs->pc += 4;
 	regs->code = fetch(regs, memRLUT, pc);
 	psxBSC[regs->code >> 26](regs, regs->code);
+	psxRegs.cycle += 2;
+	fetchNoCache(regs, memRLUT, regs->pc); // bus err check
 }
 
 static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
 	u32 pc = regs->pc;
 
-	addCycle(regs);
+	//addCycle(regs);
 	dloadStep(regs);
 
 	if (execBreakCheck(regs, pc))
@@ -1189,6 +1194,8 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
 	regs->pc += 4;
 	regs->code = fetch(regs, memRLUT, pc);
 	psxBSC[regs->code >> 26](regs, regs->code);
+	psxRegs.cycle += 2;
+	fetchNoCache(regs, memRLUT, regs->pc); // bus err check
 }
 
 static void intExecute() {
@@ -1218,6 +1225,30 @@ void intExecuteBlock(enum blockExecCaller caller) {
 		execI_(memRLUT, regs_);
 }
 
+extern void do_insn_trace(void);
+
+void intExecuteT() {
+	psxRegisters *regs_ = &psxRegs;
+	u8 **memRLUT = psxMemRLUT;
+	extern int stop;
+
+	while (!stop) {
+		do_insn_trace();
+		execIbp(memRLUT, regs_);
+	}
+}
+
+void intExecuteBlockT() {
+	psxRegisters *regs_ = &psxRegs;
+	u8 **memRLUT = psxMemRLUT;
+
+	branchSeen = 0;
+	while (!branchSeen) {
+		do_insn_trace();
+		execIbp(memRLUT, regs_);
+	}
+}
+
 static void intClear(u32 Addr, u32 Size) {
 }
 
@@ -1246,7 +1277,7 @@ static void setupCop(u32 sr)
 	else
 		psxBSC[17] = psxCOPd;
 	if (sr & (1u << 30))
-		psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
+		psxBSC[18] = psxCOP2;
 	else
 		psxBSC[18] = psxCOPd;
 	if (sr & (1u << 31))
@@ -1265,7 +1296,7 @@ void intApplyConfig() {
 	assert(psxSPC[26] == psxDIV   || psxSPC[26] == psxDIV_stall);
 	assert(psxSPC[27] == psxDIVU  || psxSPC[27] == psxDIVU_stall);
 
-	if (Config.DisableStalls) {
+	if (1) {
 		psxBSC[18] = psxCOP2;
 		psxBSC[50] = gteLWC2;
 		psxBSC[58] = gteSWC2;
diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c
index 42755e52..4fa4316b 100644
--- a/libpcsxcore/psxmem.c
+++ b/libpcsxcore/psxmem.c
@@ -289,10 +289,13 @@ void psxMemOnIsolate(int enable)
 			: R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
 }
 
+extern u32 last_io_addr;
+
 u8 psxMemRead8(u32 mem) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -318,6 +321,7 @@ u16 psxMemRead16(u32 mem) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -343,6 +347,7 @@ u32 psxMemRead32(u32 mem) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -370,6 +375,7 @@ void psxMemWrite8(u32 mem, u8 value) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -397,6 +403,7 @@ void psxMemWrite16(u32 mem, u16 value) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -424,6 +431,7 @@ void psxMemWrite32(u32 mem, u32 value) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 //	if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n");
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
@@ -442,6 +450,8 @@ void psxMemWrite32(u32 mem, u32 value) {
 #endif
 		} else {
 			if (mem == 0xfffe0130) {
+extern u32 handler_cycle;
+handler_cycle = psxRegs.cycle;
 				psxRegs.biuReg = value;
 				return;
 			}
diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index 48881068..47c40940 100644
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -127,6 +127,8 @@ void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
 }
 
 void psxBranchTest() {
+ extern u32 irq_test_cycle;
+ irq_test_cycle = psxRegs.cycle;
 	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
 		psxRcntUpdate();
Commit	Line	Data
a151a8d8	1	diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
4f13a577	2	index f879ad8c..0ec366d0 100644
a151a8d8	3	--- a/libpcsxcore/new_dynarec/emu_if.c
a151a8d8	4	+++ b/libpcsxcore/new_dynarec/emu_if.c
90f98e7c	5	@@ -323,13 +323,18 @@ static void ari64_shutdown()
a151a8d8	6	{
	7	new_dynarec_cleanup();
	8	new_dyna_pcsx_mem_shutdown();
	9	+ (void)ari64_execute;
a5cd72d0	10	+ (void)ari64_execute_block;
a151a8d8	11	}
	12
	13	+extern void intExecuteT();
	14	+extern void intExecuteBlockT();
	15	+
	16	R3000Acpu psxRec = {
	17	ari64_init,
	18	ari64_reset,
	19	- ari64_execute,
a5cd72d0	20	- ari64_execute_block,
a151a8d8	21	+ intExecuteT,
	22	+ intExecuteBlockT,
	23	ari64_clear,
a151a8d8	24	ari64_notify,
37387d8b	25	ari64_apply_config,
90f98e7c	26	@@ -398,7 +403,7 @@ static u32 memcheck_read(u32 a)
a151a8d8	27	return (u32 )(psxM + (a & 0x1ffffc));
	28	}
	29
	30	-#if 0
	31	+#if 1
	32	void do_insn_trace(void)
	33	{
	34	static psxRegisters oldregs;
2330734f	35	diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
4f13a577	36	index 1f37dc29..357f753e 100644
2330734f	37	--- a/libpcsxcore/new_dynarec/pcsxmem.c
2330734f	38	+++ b/libpcsxcore/new_dynarec/pcsxmem.c
a5cd72d0	39	@@ -289,6 +289,8 @@ static void write_biu(u32 value)
2330734f	40	return;
a5cd72d0	41	}
2330734f	42
	43	+extern u32 handler_cycle;
	44	+handler_cycle = psxRegs.cycle;
a5cd72d0	45	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
	46	psxRegs.biuReg = value;
	47	}
2330734f	48	diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
a5cd72d0	49	index 18bd6a4e..bc2eb3f6 100644
2330734f	50	--- a/libpcsxcore/psxcounters.c
2330734f	51	+++ b/libpcsxcore/psxcounters.c
a5cd72d0	52	@@ -389,9 +389,12 @@ void psxRcntUpdate()
2330734f	53
	54	/******************************************************************************/
	55
	56	+extern u32 handler_cycle;
	57	+
	58	void psxRcntWcount( u32 index, u32 value )
	59	{
	60	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	61	+handler_cycle = psxRegs.cycle;
	62
	63	_psxRcntWcount( index, value );
	64	psxRcntSet();
a5cd72d0	65	@@ -400,6 +403,7 @@ void psxRcntWcount( u32 index, u32 value )
2330734f	66	void psxRcntWmode( u32 index, u32 value )
	67	{
	68	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	69	+handler_cycle = psxRegs.cycle;
	70
	71	_psxRcntWmode( index, value );
	72	_psxRcntWcount( index, 0 );
a5cd72d0	73	@@ -411,6 +415,7 @@ void psxRcntWmode( u32 index, u32 value )
2330734f	74	void psxRcntWtarget( u32 index, u32 value )
	75	{
	76	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	77	+handler_cycle = psxRegs.cycle;
	78
	79	rcnts[index].target = value;
	80
a5cd72d0	81	@@ -423,6 +428,7 @@ void psxRcntWtarget( u32 index, u32 value )
2330734f	82	u32 psxRcntRcount( u32 index )
	83	{
	84	u32 count;
	85	+handler_cycle = psxRegs.cycle;
	86
	87	count = _psxRcntRcount( index );
	88
a151a8d8	89	diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
4f13a577	90	index 10a2695f..7e4a64da 100644
a151a8d8	91	--- a/libpcsxcore/psxhw.c
a151a8d8	92	+++ b/libpcsxcore/psxhw.c
4f13a577	93	@@ -437,13 +437,14 @@ void psxHwWrite8(u32 add, u8 value) {
	94	return;
	95	}
a151a8d8	96
a151a8d8	97	+ if (add < 0x1f802000)
	98	psxHu8(add) = value;
	99	#ifdef PSXHW_LOG
	100	PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
	101	#endif
	102	return;
	103	}
	104	- psxHu8(add) = value;
	105	+ //psxHu8(add) = value;
	106	#ifdef PSXHW_LOG
	107	PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
	108	#endif
4f13a577	109	@@ -565,6 +566,7 @@ void psxHwWrite16(u32 add, u16 value) {
a151a8d8	110	return;
	111	}
	112
	113	+ if (add < 0x1f802000)
	114	psxHu16ref(add) = SWAPu16(value);
	115	#ifdef PSXHW_LOG
	116	PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
4f13a577	117	@@ -756,9 +758,9 @@ void psxHwWrite32(u32 add, u32 value) {
a151a8d8	118	return;
	119
	120	case 0x1f801820:
	121	- mdecWrite0(value); break;
	122	+ mdecWrite0(value); return;
	123	case 0x1f801824:
	124	- mdecWrite1(value); break;
	125	+ mdecWrite1(value); return;
	126
	127	case 0x1f801100:
	128	#ifdef PSXHW_LOG
4f13a577	129	@@ -826,6 +828,7 @@ void psxHwWrite32(u32 add, u32 value) {
a151a8d8	130	return;
	131	}
	132
	133	+ if (add < 0x1f802000)
	134	psxHu32ref(add) = SWAPu32(value);
	135	#ifdef PSXHW_LOG
	136	PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
	137	diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
4f13a577	138	index 5756bee5..4bf9248d 100644
a151a8d8	139	--- a/libpcsxcore/psxinterpreter.c
a151a8d8	140	+++ b/libpcsxcore/psxinterpreter.c
4f13a577	141	@@ -238,7 +238,7 @@ static inline void addCycle(psxRegisters *regs)
a5cd72d0	142	{
	143	assert(regs->subCycleStep >= 0x10000);
	144	regs->subCycle += regs->subCycleStep;
	145	- regs->cycle += regs->subCycle >> 16;
	146	+ regs->cycle += 2; //regs->subCycle >> 16;
	147	regs->subCycle &= 0xffff;
	148	}
a151a8d8	149
4f13a577	150	@@ -435,7 +435,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
a5cd72d0	151	regs->CP0.n.Target = pc_final;
a5cd72d0	152	regs->branching = 0;
a151a8d8	153
a5cd72d0	154	+ psxRegs.cycle += 2;
2330734f	155	psxBranchTest();
a5cd72d0	156	+ psxRegs.cycle -= 2;
a151a8d8	157	}
a151a8d8	158
a5cd72d0	159	static void doBranchReg(psxRegisters *regs, u32 tar) {
4f13a577	160	@@ -960,7 +962,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
a5cd72d0	161	}
a151a8d8	162	}
a151a8d8	163
a5cd72d0	164	-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
	165	+OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); }
	166
	167	// no exception
	168	static inline void psxNULLne(psxRegisters *regs) {
4f13a577	169	@@ -1120,6 +1122,7 @@ OP(psxHLE) {
	170	}
	171	psxHLEt[hleCode]();
	172	branchSeen = 1;
	173	+ psxRegs.cycle -= 2;
	174	}
	175
	176	static void (INT_ATTR psxBSC[64])(psxRegisters regs_, u32 code) = {
	177	@@ -1169,18 +1172,20 @@ static void intReset() {
a5cd72d0	178	static inline void execI_(u8 *memRLUT, psxRegisters regs) {
	179	u32 pc = regs->pc;
	180
	181	- addCycle(regs);
	182	+ //addCycle(regs);
	183	dloadStep(regs);
	184
	185	regs->pc += 4;
	186	regs->code = fetch(regs, memRLUT, pc);
	187	psxBSC[regs->code >> 26](regs, regs->code);
	188	+ psxRegs.cycle += 2;
de6dbc52	189	+ fetchNoCache(regs, memRLUT, regs->pc); // bus err check
55a695d9	190	}
a151a8d8	191
a5cd72d0	192	static inline void execIbp(u8 *memRLUT, psxRegisters regs) {
	193	u32 pc = regs->pc;
	194
	195	- addCycle(regs);
	196	+ //addCycle(regs);
	197	dloadStep(regs);
	198
	199	if (execBreakCheck(regs, pc))
4f13a577	200	@@ -1189,6 +1194,8 @@ static inline void execIbp(u8 *memRLUT, psxRegisters regs) {
a5cd72d0	201	regs->pc += 4;
	202	regs->code = fetch(regs, memRLUT, pc);
	203	psxBSC[regs->code >> 26](regs, regs->code);
	204	+ psxRegs.cycle += 2;
de6dbc52	205	+ fetchNoCache(regs, memRLUT, regs->pc); // bus err check
a5cd72d0	206	}
55a695d9	207
a5cd72d0	208	static void intExecute() {
4f13a577	209	@@ -1218,6 +1225,30 @@ void intExecuteBlock(enum blockExecCaller caller) {
a5cd72d0	210	execI_(memRLUT, regs_);
a151a8d8	211	}
	212
	213	+extern void do_insn_trace(void);
	214	+
	215	+void intExecuteT() {
a5cd72d0	216	+ psxRegisters *regs_ = &psxRegs;
	217	+ u8 **memRLUT = psxMemRLUT;
	218	+ extern int stop;
	219	+
	220	+ while (!stop) {
a151a8d8	221	+ do_insn_trace();
a5cd72d0	222	+ execIbp(memRLUT, regs_);
a151a8d8	223	+ }
	224	+}
	225	+
	226	+void intExecuteBlockT() {
a5cd72d0	227	+ psxRegisters *regs_ = &psxRegs;
	228	+ u8 **memRLUT = psxMemRLUT;
	229	+
	230	+ branchSeen = 0;
	231	+ while (!branchSeen) {
a151a8d8	232	+ do_insn_trace();
a5cd72d0	233	+ execIbp(memRLUT, regs_);
a151a8d8	234	+ }
	235	+}
	236	+
	237	static void intClear(u32 Addr, u32 Size) {
	238	}
	239
4f13a577	240	@@ -1246,7 +1277,7 @@ static void setupCop(u32 sr)
90f98e7c	241	else
	242	psxBSC[17] = psxCOPd;
	243	if (sr & (1u << 30))
	244	- psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
	245	+ psxBSC[18] = psxCOP2;
	246	else
	247	psxBSC[18] = psxCOPd;
	248	if (sr & (1u << 31))
4f13a577	249	@@ -1265,7 +1296,7 @@ void intApplyConfig() {
2330734f	250	assert(psxSPC[26] == psxDIV \|\| psxSPC[26] == psxDIV_stall);
	251	assert(psxSPC[27] == psxDIVU \|\| psxSPC[27] == psxDIVU_stall);
	252
	253	- if (Config.DisableStalls) {
	254	+ if (1) {
	255	psxBSC[18] = psxCOP2;
	256	psxBSC[50] = gteLWC2;
	257	psxBSC[58] = gteSWC2;
a151a8d8	258	diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c
4f13a577	259	index 42755e52..4fa4316b 100644
a151a8d8	260	--- a/libpcsxcore/psxmem.c
a151a8d8	261	+++ b/libpcsxcore/psxmem.c
4f13a577	262	@@ -289,10 +289,13 @@ void psxMemOnIsolate(int enable)
a5cd72d0	263	: R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
a151a8d8	264	}
a151a8d8	265
2330734f	266	+extern u32 last_io_addr;
a5cd72d0	267	+
a151a8d8	268	u8 psxMemRead8(u32 mem) {
	269	char *p;
	270	u32 t;
	271
	272	+ last_io_addr = mem;
	273	t = mem >> 16;
	274	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	275	if ((mem & 0xffff) < 0x400)
4f13a577	276	@@ -318,6 +321,7 @@ u16 psxMemRead16(u32 mem) {
a151a8d8	277	char *p;
	278	u32 t;
	279
	280	+ last_io_addr = mem;
	281	t = mem >> 16;
	282	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	283	if ((mem & 0xffff) < 0x400)
4f13a577	284	@@ -343,6 +347,7 @@ u32 psxMemRead32(u32 mem) {
a151a8d8	285	char *p;
	286	u32 t;
	287
	288	+ last_io_addr = mem;
	289	t = mem >> 16;
	290	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	291	if ((mem & 0xffff) < 0x400)
4f13a577	292	@@ -370,6 +375,7 @@ void psxMemWrite8(u32 mem, u8 value) {
a151a8d8	293	char *p;
	294	u32 t;
	295
	296	+ last_io_addr = mem;
	297	t = mem >> 16;
	298	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	299	if ((mem & 0xffff) < 0x400)
4f13a577	300	@@ -397,6 +403,7 @@ void psxMemWrite16(u32 mem, u16 value) {
a151a8d8	301	char *p;
	302	u32 t;
	303
	304	+ last_io_addr = mem;
	305	t = mem >> 16;
	306	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	307	if ((mem & 0xffff) < 0x400)
4f13a577	308	@@ -424,6 +431,7 @@ void psxMemWrite32(u32 mem, u32 value) {
a151a8d8	309	char *p;
	310	u32 t;
	311
	312	+ last_io_addr = mem;
	313	// if ((mem&0x1fffff) == 0x71E18 \|\| value == 0x48088800) SysPrintf("t2fix!!\n");
	314	t = mem >> 16;
	315	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
4f13a577	316	@@ -442,6 +450,8 @@ void psxMemWrite32(u32 mem, u32 value) {
a5cd72d0	317	#endif
	318	} else {
	319	if (mem == 0xfffe0130) {
2330734f	320	+extern u32 handler_cycle;
2330734f	321	+handler_cycle = psxRegs.cycle;
a5cd72d0	322	psxRegs.biuReg = value;
	323	return;
	324	}
2330734f	325	diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
4f13a577	326	index 48881068..47c40940 100644
2330734f	327	--- a/libpcsxcore/r3000a.c
2330734f	328	+++ b/libpcsxcore/r3000a.c
4f13a577	329	@@ -127,6 +127,8 @@ void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
2330734f	330	}
	331
	332	void psxBranchTest() {
	333	+ extern u32 irq_test_cycle;
	334	+ irq_test_cycle = psxRegs.cycle;
	335	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
	336	psxRcntUpdate();
	337