a151a8d8 |
1 | diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c |
a5cd72d0 |
2 | index 89716fa0..02a8d7c5 100644 |
a151a8d8 |
3 | --- a/libpcsxcore/new_dynarec/emu_if.c |
4 | +++ b/libpcsxcore/new_dynarec/emu_if.c |
a5cd72d0 |
5 | @@ -320,13 +320,18 @@ static void ari64_shutdown() |
a151a8d8 |
6 | { |
7 | new_dynarec_cleanup(); |
8 | new_dyna_pcsx_mem_shutdown(); |
9 | + (void)ari64_execute; |
a5cd72d0 |
10 | + (void)ari64_execute_block; |
a151a8d8 |
11 | } |
12 | |
13 | +extern void intExecuteT(); |
14 | +extern void intExecuteBlockT(); |
15 | + |
16 | R3000Acpu psxRec = { |
17 | ari64_init, |
18 | ari64_reset, |
19 | - ari64_execute, |
a5cd72d0 |
20 | - ari64_execute_block, |
a151a8d8 |
21 | + intExecuteT, |
22 | + intExecuteBlockT, |
23 | ari64_clear, |
a151a8d8 |
24 | ari64_notify, |
37387d8b |
25 | ari64_apply_config, |
a5cd72d0 |
26 | @@ -395,7 +400,7 @@ static u32 memcheck_read(u32 a) |
a151a8d8 |
27 | return *(u32 *)(psxM + (a & 0x1ffffc)); |
28 | } |
29 | |
30 | -#if 0 |
31 | +#if 1 |
32 | void do_insn_trace(void) |
33 | { |
34 | static psxRegisters oldregs; |
2330734f |
35 | diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c |
a5cd72d0 |
36 | index 190f8fc7..5feb7a02 100644 |
2330734f |
37 | --- a/libpcsxcore/new_dynarec/pcsxmem.c |
38 | +++ b/libpcsxcore/new_dynarec/pcsxmem.c |
a5cd72d0 |
39 | @@ -289,6 +289,8 @@ static void write_biu(u32 value) |
2330734f |
40 | return; |
a5cd72d0 |
41 | } |
2330734f |
42 | |
43 | +extern u32 handler_cycle; |
44 | +handler_cycle = psxRegs.cycle; |
a5cd72d0 |
45 | memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle); |
46 | psxRegs.biuReg = value; |
47 | } |
2330734f |
48 | diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c |
a5cd72d0 |
49 | index 18bd6a4e..bc2eb3f6 100644 |
2330734f |
50 | --- a/libpcsxcore/psxcounters.c |
51 | +++ b/libpcsxcore/psxcounters.c |
a5cd72d0 |
52 | @@ -389,9 +389,12 @@ void psxRcntUpdate() |
2330734f |
53 | |
54 | /******************************************************************************/ |
55 | |
56 | +extern u32 handler_cycle; |
57 | + |
58 | void psxRcntWcount( u32 index, u32 value ) |
59 | { |
60 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); |
61 | +handler_cycle = psxRegs.cycle; |
62 | |
63 | _psxRcntWcount( index, value ); |
64 | psxRcntSet(); |
a5cd72d0 |
65 | @@ -400,6 +403,7 @@ void psxRcntWcount( u32 index, u32 value ) |
2330734f |
66 | void psxRcntWmode( u32 index, u32 value ) |
67 | { |
68 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); |
69 | +handler_cycle = psxRegs.cycle; |
70 | |
71 | _psxRcntWmode( index, value ); |
72 | _psxRcntWcount( index, 0 ); |
a5cd72d0 |
73 | @@ -411,6 +415,7 @@ void psxRcntWmode( u32 index, u32 value ) |
2330734f |
74 | void psxRcntWtarget( u32 index, u32 value ) |
75 | { |
76 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); |
77 | +handler_cycle = psxRegs.cycle; |
78 | |
79 | rcnts[index].target = value; |
80 | |
a5cd72d0 |
81 | @@ -423,6 +428,7 @@ void psxRcntWtarget( u32 index, u32 value ) |
2330734f |
82 | u32 psxRcntRcount( u32 index ) |
83 | { |
84 | u32 count; |
85 | +handler_cycle = psxRegs.cycle; |
86 | |
87 | count = _psxRcntRcount( index ); |
88 | |
a151a8d8 |
89 | diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c |
a5cd72d0 |
90 | index 27ddfeab..d7c6ff05 100644 |
a151a8d8 |
91 | --- a/libpcsxcore/psxhw.c |
92 | +++ b/libpcsxcore/psxhw.c |
a5cd72d0 |
93 | @@ -377,13 +377,14 @@ void psxHwWrite8(u32 add, u8 value) { |
a151a8d8 |
94 | case 0x1f801803: cdrWrite3(value); break; |
95 | |
96 | default: |
97 | + if (add < 0x1f802000) |
98 | psxHu8(add) = value; |
99 | #ifdef PSXHW_LOG |
100 | PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value); |
101 | #endif |
102 | return; |
103 | } |
104 | - psxHu8(add) = value; |
105 | + //psxHu8(add) = value; |
106 | #ifdef PSXHW_LOG |
107 | PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value); |
108 | #endif |
a5cd72d0 |
109 | @@ -506,6 +507,7 @@ void psxHwWrite16(u32 add, u16 value) { |
a151a8d8 |
110 | return; |
111 | } |
112 | |
113 | + if (add < 0x1f802000) |
114 | psxHu16ref(add) = SWAPu16(value); |
115 | #ifdef PSXHW_LOG |
116 | PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value); |
a5cd72d0 |
117 | @@ -701,9 +703,9 @@ void psxHwWrite32(u32 add, u32 value) { |
a151a8d8 |
118 | return; |
119 | |
120 | case 0x1f801820: |
121 | - mdecWrite0(value); break; |
122 | + mdecWrite0(value); return; |
123 | case 0x1f801824: |
124 | - mdecWrite1(value); break; |
125 | + mdecWrite1(value); return; |
126 | |
127 | case 0x1f801100: |
128 | #ifdef PSXHW_LOG |
a5cd72d0 |
129 | @@ -761,6 +763,7 @@ void psxHwWrite32(u32 add, u32 value) { |
a151a8d8 |
130 | return; |
131 | } |
132 | |
133 | + if (add < 0x1f802000) |
134 | psxHu32ref(add) = SWAPu32(value); |
135 | #ifdef PSXHW_LOG |
136 | PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value); |
137 | diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c |
a5cd72d0 |
138 | index be15f782..6f07478f 100644 |
a151a8d8 |
139 | --- a/libpcsxcore/psxinterpreter.c |
140 | +++ b/libpcsxcore/psxinterpreter.c |
a5cd72d0 |
141 | @@ -237,7 +237,7 @@ static inline void addCycle(psxRegisters *regs) |
142 | { |
143 | assert(regs->subCycleStep >= 0x10000); |
144 | regs->subCycle += regs->subCycleStep; |
145 | - regs->cycle += regs->subCycle >> 16; |
146 | + regs->cycle += 2; //regs->subCycle >> 16; |
147 | regs->subCycle &= 0xffff; |
148 | } |
a151a8d8 |
149 | |
a5cd72d0 |
150 | @@ -434,7 +434,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) { |
151 | regs->CP0.n.Target = pc_final; |
152 | regs->branching = 0; |
a151a8d8 |
153 | |
a5cd72d0 |
154 | + psxRegs.cycle += 2; |
2330734f |
155 | psxBranchTest(); |
a5cd72d0 |
156 | + psxRegs.cycle -= 2; |
a151a8d8 |
157 | } |
158 | |
a5cd72d0 |
159 | static void doBranchReg(psxRegisters *regs, u32 tar) { |
160 | @@ -967,7 +969,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) { |
161 | } |
a151a8d8 |
162 | } |
163 | |
a5cd72d0 |
164 | -OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); } |
165 | +OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); } |
166 | |
167 | // no exception |
168 | static inline void psxNULLne(psxRegisters *regs) { |
169 | @@ -1175,18 +1177,19 @@ static void intReset() { |
170 | static inline void execI_(u8 **memRLUT, psxRegisters *regs) { |
171 | u32 pc = regs->pc; |
172 | |
173 | - addCycle(regs); |
174 | + //addCycle(regs); |
175 | dloadStep(regs); |
176 | |
177 | regs->pc += 4; |
178 | regs->code = fetch(regs, memRLUT, pc); |
179 | psxBSC[regs->code >> 26](regs, regs->code); |
180 | + psxRegs.cycle += 2; |
55a695d9 |
181 | } |
a151a8d8 |
182 | |
a5cd72d0 |
183 | static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { |
184 | u32 pc = regs->pc; |
185 | |
186 | - addCycle(regs); |
187 | + //addCycle(regs); |
188 | dloadStep(regs); |
189 | |
190 | if (execBreakCheck(regs, pc)) |
191 | @@ -1195,6 +1198,7 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { |
192 | regs->pc += 4; |
193 | regs->code = fetch(regs, memRLUT, pc); |
194 | psxBSC[regs->code >> 26](regs, regs->code); |
195 | + psxRegs.cycle += 2; |
196 | } |
55a695d9 |
197 | |
a5cd72d0 |
198 | static void intExecute() { |
199 | @@ -1224,6 +1228,30 @@ void intExecuteBlock(enum blockExecCaller caller) { |
200 | execI_(memRLUT, regs_); |
a151a8d8 |
201 | } |
202 | |
203 | +extern void do_insn_trace(void); |
204 | + |
205 | +void intExecuteT() { |
a5cd72d0 |
206 | + psxRegisters *regs_ = &psxRegs; |
207 | + u8 **memRLUT = psxMemRLUT; |
208 | + extern int stop; |
209 | + |
210 | + while (!stop) { |
a151a8d8 |
211 | + do_insn_trace(); |
a5cd72d0 |
212 | + execIbp(memRLUT, regs_); |
a151a8d8 |
213 | + } |
214 | +} |
215 | + |
216 | +void intExecuteBlockT() { |
a5cd72d0 |
217 | + psxRegisters *regs_ = &psxRegs; |
218 | + u8 **memRLUT = psxMemRLUT; |
219 | + |
220 | + branchSeen = 0; |
221 | + while (!branchSeen) { |
a151a8d8 |
222 | + do_insn_trace(); |
a5cd72d0 |
223 | + execIbp(memRLUT, regs_); |
a151a8d8 |
224 | + } |
225 | +} |
226 | + |
227 | static void intClear(u32 Addr, u32 Size) { |
228 | } |
229 | |
a5cd72d0 |
230 | @@ -1271,7 +1299,7 @@ void intApplyConfig() { |
2330734f |
231 | assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall); |
232 | assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall); |
233 | |
234 | - if (Config.DisableStalls) { |
235 | + if (1) { |
236 | psxBSC[18] = psxCOP2; |
237 | psxBSC[50] = gteLWC2; |
238 | psxBSC[58] = gteSWC2; |
a151a8d8 |
239 | diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c |
a5cd72d0 |
240 | index 54219ae0..41168ced 100644 |
a151a8d8 |
241 | --- a/libpcsxcore/psxmem.c |
242 | +++ b/libpcsxcore/psxmem.c |
a5cd72d0 |
243 | @@ -278,10 +278,13 @@ void psxMemOnIsolate(int enable) |
244 | : R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL); |
a151a8d8 |
245 | } |
246 | |
2330734f |
247 | +extern u32 last_io_addr; |
a5cd72d0 |
248 | + |
a151a8d8 |
249 | u8 psxMemRead8(u32 mem) { |
250 | char *p; |
251 | u32 t; |
252 | |
253 | + last_io_addr = mem; |
254 | t = mem >> 16; |
255 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
256 | if ((mem & 0xffff) < 0x400) |
a5cd72d0 |
257 | @@ -307,6 +310,7 @@ u16 psxMemRead16(u32 mem) { |
a151a8d8 |
258 | char *p; |
259 | u32 t; |
260 | |
261 | + last_io_addr = mem; |
262 | t = mem >> 16; |
263 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
264 | if ((mem & 0xffff) < 0x400) |
a5cd72d0 |
265 | @@ -332,6 +336,7 @@ u32 psxMemRead32(u32 mem) { |
a151a8d8 |
266 | char *p; |
267 | u32 t; |
268 | |
269 | + last_io_addr = mem; |
270 | t = mem >> 16; |
271 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
272 | if ((mem & 0xffff) < 0x400) |
a5cd72d0 |
273 | @@ -359,6 +364,7 @@ void psxMemWrite8(u32 mem, u8 value) { |
a151a8d8 |
274 | char *p; |
275 | u32 t; |
276 | |
277 | + last_io_addr = mem; |
278 | t = mem >> 16; |
279 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
280 | if ((mem & 0xffff) < 0x400) |
a5cd72d0 |
281 | @@ -386,6 +392,7 @@ void psxMemWrite16(u32 mem, u16 value) { |
a151a8d8 |
282 | char *p; |
283 | u32 t; |
284 | |
285 | + last_io_addr = mem; |
286 | t = mem >> 16; |
287 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
288 | if ((mem & 0xffff) < 0x400) |
a5cd72d0 |
289 | @@ -413,6 +420,7 @@ void psxMemWrite32(u32 mem, u32 value) { |
a151a8d8 |
290 | char *p; |
291 | u32 t; |
292 | |
293 | + last_io_addr = mem; |
294 | // if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n"); |
295 | t = mem >> 16; |
296 | if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { |
a5cd72d0 |
297 | @@ -431,6 +439,8 @@ void psxMemWrite32(u32 mem, u32 value) { |
298 | #endif |
299 | } else { |
300 | if (mem == 0xfffe0130) { |
2330734f |
301 | +extern u32 handler_cycle; |
302 | +handler_cycle = psxRegs.cycle; |
a5cd72d0 |
303 | psxRegs.biuReg = value; |
304 | return; |
305 | } |
2330734f |
306 | diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c |
a5cd72d0 |
307 | index dffbf6e7..0a3bdb65 100644 |
2330734f |
308 | --- a/libpcsxcore/r3000a.c |
309 | +++ b/libpcsxcore/r3000a.c |
a5cd72d0 |
310 | @@ -124,6 +124,8 @@ void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) { |
2330734f |
311 | } |
312 | |
313 | void psxBranchTest() { |
314 | + extern u32 irq_test_cycle; |
315 | + irq_test_cycle = psxRegs.cycle; |
316 | if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter) |
317 | psxRcntUpdate(); |
318 | |