7e605697 |
1 | /* |
274c4243 |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2010-2011 |
7e605697 |
3 | * |
4 | * This work is licensed under the terms of GNU GPL version 2 or later. |
5 | * See the COPYING file in the top-level directory. |
6 | */ |
7 | |
8 | #include <stdio.h> |
630b122b |
9 | #include "../psxhw.h" |
10 | #include "../cdrom.h" |
11 | #include "../mdec.h" |
12 | #include "../gpu.h" |
13 | #include "../psxmem_map.h" |
7e605697 |
14 | #include "emu_if.h" |
15 | #include "pcsxmem.h" |
16 | |
5905989e |
17 | #ifdef __thumb__ |
9f704290 |
18 | #error the dynarec is incompatible with Thumb functions, |
19 | #error please add -marm to compile flags |
5905989e |
20 | #endif |
21 | |
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22 | //#define memprintf printf |
23 | #define memprintf(...) |
24 | |
630b122b |
25 | static uintptr_t *mem_readtab; |
26 | static uintptr_t *mem_writetab; |
27 | static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4]; |
28 | static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4]; |
c6b7420b |
29 | static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4]; |
630b122b |
30 | static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4]; |
31 | //static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4]; |
32 | static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4]; |
b1be1eee |
33 | |
630b122b |
34 | static |
578c6882 |
35 | #ifdef __clang__ |
630b122b |
36 | // When this is called in a loop, and 'h' is a function pointer, clang will crash. |
37 | __attribute__ ((noinline)) |
578c6882 |
38 | #endif |
630b122b |
39 | void map_item(uintptr_t *out, const void *h, uintptr_t flag) |
b1be1eee |
40 | { |
630b122b |
41 | uintptr_t hv = (uintptr_t)h; |
5905989e |
42 | if (hv & 1) { |
f29fbd53 |
43 | SysPrintf("FATAL: %p has LSB set\n", h); |
5905989e |
44 | abort(); |
45 | } |
630b122b |
46 | *out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1)); |
b1be1eee |
47 | } |
48 | |
49 | // size must be power of 2, at least 4k |
50 | #define map_l1_mem(tab, i, addr, size, base) \ |
c6b7420b |
51 | map_item(&tab[((u32)(addr) >> 12) + i], \ |
54510684 |
52 | (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0) |
b1be1eee |
53 | |
54 | #define IOMEM32(a) (((a) & 0xfff) / 4) |
55 | #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2)) |
56 | #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff)) |
57 | |
c6b7420b |
58 | u32 zero_mem[0x1000/4]; |
59 | static u32 ffff_mem[0x1000/4]; |
7a481d40 |
60 | |
c6b7420b |
61 | static u32 read_mem_dummy(u32 addr) |
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62 | { |
c6b7420b |
63 | // use 'addr' and not 'address', yes the api is weird... |
64 | memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle); |
65 | return 0xffffffff; |
7e605697 |
66 | } |
67 | |
b96d3df7 |
68 | static void write_mem_dummy(u32 data) |
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69 | { |
6d79a06f |
70 | if (!(psxRegs.CP0.n.SR & (1 << 16))) |
c6b7420b |
71 | memprintf("unmapped w %08x, %08x @%08x %u\n", |
72 | address, data, psxRegs.pc, psxRegs.cycle); |
7e605697 |
73 | } |
74 | |
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75 | /* IO handlers */ |
76 | static u32 io_read_sio16() |
77 | { |
78 | return sioRead8() | (sioRead8() << 8); |
79 | } |
80 | |
81 | static u32 io_read_sio32() |
82 | { |
83 | return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24); |
84 | } |
85 | |
86 | static void io_write_sio16(u32 value) |
87 | { |
88 | sioWrite8((unsigned char)value); |
89 | sioWrite8((unsigned char)(value>>8)); |
90 | } |
91 | |
92 | static void io_write_sio32(u32 value) |
93 | { |
94 | sioWrite8((unsigned char)value); |
b96d3df7 |
95 | sioWrite8((unsigned char)(value >> 8)); |
96 | sioWrite8((unsigned char)(value >> 16)); |
97 | sioWrite8((unsigned char)(value >> 24)); |
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98 | } |
99 | |
630b122b |
100 | #if !defined(DRC_DBG) && defined(__arm__) |
19776aef |
101 | |
b1be1eee |
102 | static void map_rcnt_rcount0(u32 mode) |
103 | { |
d3d41455 |
104 | if (mode & 0x001) { // sync mode |
105 | map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1); |
106 | map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1); |
107 | } |
108 | else if (mode & 0x100) { // pixel clock |
b1be1eee |
109 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1); |
110 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1); |
111 | } |
112 | else { |
113 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1); |
114 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1); |
115 | } |
116 | } |
117 | |
118 | static void map_rcnt_rcount1(u32 mode) |
119 | { |
d3d41455 |
120 | if (mode & 0x001) { // sync mode |
121 | map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1); |
122 | map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1); |
123 | } |
124 | else if (mode & 0x100) { // hcnt |
b1be1eee |
125 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1); |
126 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1); |
127 | } |
128 | else { |
129 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1); |
130 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1); |
131 | } |
132 | } |
133 | |
134 | static void map_rcnt_rcount2(u32 mode) |
135 | { |
d3d41455 |
136 | if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode |
b1be1eee |
137 | map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0); |
138 | map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0); |
139 | } |
140 | else if (mode & 0x200) { // clk/8 |
141 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1); |
142 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1); |
143 | } |
144 | else { |
145 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1); |
146 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1); |
147 | } |
148 | } |
149 | |
19776aef |
150 | #else |
151 | #define map_rcnt_rcount0(mode) |
152 | #define map_rcnt_rcount1(mode) |
153 | #define map_rcnt_rcount2(mode) |
154 | #endif |
155 | |
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156 | #define make_rcnt_funcs(i) \ |
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157 | static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \ |
158 | static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \ |
159 | static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \ |
b1be1eee |
160 | static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \ |
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161 | static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); } |
162 | |
163 | make_rcnt_funcs(0) |
164 | make_rcnt_funcs(1) |
165 | make_rcnt_funcs(2) |
166 | |
7e605697 |
167 | #define make_dma_func(n) \ |
168 | static void io_write_chcr##n(u32 value) \ |
169 | { \ |
170 | HW_DMA##n##_CHCR = value; \ |
171 | if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \ |
172 | psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \ |
173 | } \ |
174 | } |
175 | |
176 | make_dma_func(0) |
177 | make_dma_func(1) |
178 | make_dma_func(2) |
179 | make_dma_func(3) |
180 | make_dma_func(4) |
181 | make_dma_func(6) |
182 | |
b96d3df7 |
183 | static void io_spu_write16(u32 value) |
184 | { |
185 | // meh |
650adfd2 |
186 | SPU_writeRegister(address, value, psxRegs.cycle); |
b96d3df7 |
187 | } |
188 | |
189 | static void io_spu_write32(u32 value) |
190 | { |
191 | SPUwriteRegister wfunc = SPU_writeRegister; |
192 | u32 a = address; |
193 | |
650adfd2 |
194 | wfunc(a, value & 0xffff, psxRegs.cycle); |
195 | wfunc(a + 2, value >> 16, psxRegs.cycle); |
b96d3df7 |
196 | } |
197 | |
ddbaf678 |
198 | static u32 io_gpu_read_status(void) |
199 | { |
0486fdc9 |
200 | u32 v; |
201 | |
ddbaf678 |
202 | // meh2, syncing for img bit, might want to avoid it.. |
203 | gpuSyncPluginSR(); |
0486fdc9 |
204 | v = HW_GPU_STATUS; |
205 | |
206 | // XXX: because of large timeslices can't use hSyncCount, using rough |
207 | // approximization instead. Perhaps better use hcounter code here or something. |
208 | if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS) |
209 | v |= PSXGPU_LCF & (psxRegs.cycle << 20); |
210 | return v; |
ddbaf678 |
211 | } |
212 | |
213 | static void io_gpu_write_status(u32 value) |
214 | { |
215 | GPU_writeStatus(value); |
216 | gpuSyncPluginSR(); |
217 | } |
218 | |
c6b7420b |
219 | void new_dyna_pcsx_mem_isolate(int enable) |
b96d3df7 |
220 | { |
221 | int i; |
222 | |
c6b7420b |
223 | // note: apparently 0xa0000000 uncached access still works, |
224 | // at least read does for sure, so assume write does too |
225 | memprintf("mem isolate %d\n", enable); |
226 | if (enable) { |
227 | for (i = 0; i < (0x800000 >> 12); i++) { |
228 | map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1); |
229 | map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1); |
230 | //map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1); |
231 | } |
232 | } |
233 | else { |
234 | for (i = 0; i < (0x800000 >> 12); i++) { |
235 | map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM); |
236 | map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM); |
237 | map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM); |
238 | } |
b96d3df7 |
239 | } |
240 | } |
241 | |
c6b7420b |
242 | static u32 read_biu(u32 addr) |
b96d3df7 |
243 | { |
c6b7420b |
244 | if (addr != 0xfffe0130) |
245 | return read_mem_dummy(addr); |
246 | |
247 | FILE *f = fopen("/tmp/psxbiu.bin", "wb"); |
248 | fwrite(psxM, 1, 0x200000, f); |
249 | fclose(f); |
250 | memprintf("read_biu %08x @%08x %u\n", |
251 | psxRegs.biuReg, psxRegs.pc, psxRegs.cycle); |
252 | return psxRegs.biuReg; |
b96d3df7 |
253 | } |
254 | |
255 | static void write_biu(u32 value) |
256 | { |
c6b7420b |
257 | if (address != 0xfffe0130) { |
258 | write_mem_dummy(value); |
b96d3df7 |
259 | return; |
b96d3df7 |
260 | } |
c6b7420b |
261 | |
262 | memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle); |
263 | psxRegs.biuReg = value; |
b96d3df7 |
264 | } |
265 | |
b1be1eee |
266 | void new_dyna_pcsx_mem_load_state(void) |
267 | { |
268 | map_rcnt_rcount0(rcnts[0].mode); |
269 | map_rcnt_rcount1(rcnts[1].mode); |
270 | map_rcnt_rcount2(rcnts[2].mode); |
271 | } |
272 | |
003cfc63 |
273 | int pcsxmem_is_handler_dynamic(unsigned int addr) |
b1be1eee |
274 | { |
275 | if ((addr & 0xfffff000) != 0x1f801000) |
276 | return 0; |
277 | |
278 | addr &= 0xffff; |
279 | return addr == 0x1100 || addr == 0x1110 || addr == 0x1120; |
280 | } |
281 | |
7e605697 |
282 | void new_dyna_pcsx_mem_init(void) |
283 | { |
284 | int i; |
63cb0298 |
285 | |
c6b7420b |
286 | memset(ffff_mem, 0xff, sizeof(ffff_mem)); |
287 | |
c6c3b1b3 |
288 | // have to map these further to keep tcache close to .text |
630b122b |
289 | mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS); |
87e5b45f |
290 | if (mem_readtab == NULL) { |
f29fbd53 |
291 | SysPrintf("failed to map mem tables\n"); |
c6c3b1b3 |
292 | exit(1); |
293 | } |
294 | mem_writetab = mem_readtab + 0x100000; |
295 | |
296 | // 1st level lookup: |
297 | // 0: direct mem |
298 | // 1: use 2nd lookup |
299 | // 2nd level lookup: |
300 | // 0: direct mem variable |
301 | // 1: memhandler |
302 | |
303 | // default/unmapped memhandlers |
304 | for (i = 0; i < 0x100000; i++) { |
305 | //map_item(&mem_readtab[i], mem_unmrtab, 1); |
c6b7420b |
306 | map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem); |
c6c3b1b3 |
307 | map_item(&mem_writetab[i], mem_unmwtab, 1); |
308 | } |
309 | |
310 | // RAM and it's mirrors |
311 | for (i = 0; i < (0x800000 >> 12); i++) { |
312 | map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM); |
c6c3b1b3 |
313 | map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM); |
c6c3b1b3 |
314 | map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM); |
c6c3b1b3 |
315 | } |
c6b7420b |
316 | new_dyna_pcsx_mem_isolate(0); |
c6c3b1b3 |
317 | |
318 | // BIOS and it's mirrors |
319 | for (i = 0; i < (0x80000 >> 12); i++) { |
320 | map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR); |
321 | map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR); |
322 | } |
323 | |
324 | // scratchpad |
325 | map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH); |
9dd7d179 |
326 | map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH); |
c6c3b1b3 |
327 | map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH); |
9dd7d179 |
328 | map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH); |
c6c3b1b3 |
329 | |
330 | // I/O |
c6b7420b |
331 | map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1); |
332 | map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1); |
333 | map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1); |
334 | map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1); |
335 | map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1); |
336 | map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1); |
7e605697 |
337 | |
c6c3b1b3 |
338 | // L2 |
339 | // unmapped tables |
b96d3df7 |
340 | for (i = 0; i < (1+2+4) * 0x1000 / 4; i++) |
c6c3b1b3 |
341 | map_item(&mem_unmwtab[i], write_mem_dummy, 1); |
342 | |
343 | // fill IO tables |
344 | for (i = 0; i < 0x1000/4; i++) { |
345 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
346 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
347 | } |
348 | for (; i < 0x1000/4 + 0x1000/2; i++) { |
349 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
350 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
351 | } |
352 | for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) { |
353 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
354 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
355 | } |
356 | |
357 | map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1); |
d3d41455 |
358 | map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1); |
c6c3b1b3 |
359 | map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1); |
360 | map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1); |
d3d41455 |
361 | map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1); |
c6c3b1b3 |
362 | map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1); |
363 | map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1); |
d3d41455 |
364 | map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1); |
c6c3b1b3 |
365 | map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1); |
366 | map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1); |
367 | // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
ddbaf678 |
368 | map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1); |
c6c3b1b3 |
369 | map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1); |
370 | map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1); |
371 | |
372 | map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1); |
373 | map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1); |
374 | map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1); |
375 | map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1); |
376 | map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1); |
d3d41455 |
377 | map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1); |
c6c3b1b3 |
378 | map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1); |
379 | map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1); |
d3d41455 |
380 | map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1); |
c6c3b1b3 |
381 | map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1); |
382 | map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1); |
d3d41455 |
383 | map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1); |
c6c3b1b3 |
384 | map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1); |
385 | map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1); |
386 | |
387 | map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1); |
388 | map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1); |
389 | map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1); |
390 | map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1); |
391 | map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1); |
392 | |
b96d3df7 |
393 | // write(u32 data) |
394 | map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1); |
dda1b898 |
395 | map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1); |
396 | map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1); |
b96d3df7 |
397 | map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1); |
398 | map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1); |
399 | map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1); |
400 | map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1); |
401 | map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1); |
402 | map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1); |
dda1b898 |
403 | map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1); |
b96d3df7 |
404 | map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1); |
405 | map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1); |
406 | map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1); |
407 | map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1); |
408 | map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1); |
409 | map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1); |
410 | map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1); |
411 | map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1); |
412 | map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1); |
413 | // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
ddbaf678 |
414 | map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1); |
b96d3df7 |
415 | map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1); |
416 | map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1); |
417 | |
418 | map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1); |
419 | map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1); |
420 | map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1); |
421 | map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1); |
422 | map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1); |
dda1b898 |
423 | map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1); |
424 | map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1); |
b96d3df7 |
425 | map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1); |
426 | map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1); |
427 | map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1); |
428 | map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1); |
429 | map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1); |
430 | map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1); |
431 | map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1); |
432 | map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1); |
433 | map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1); |
434 | |
435 | map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1); |
436 | map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1); |
437 | map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1); |
438 | map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1); |
439 | map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1); |
440 | |
380cbc61 |
441 | for (i = 0x1c00; i < 0x2000; i += 2) { |
b96d3df7 |
442 | map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1); |
443 | map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1); |
444 | } |
445 | |
446 | // misc |
c6b7420b |
447 | map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1); |
448 | map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1); |
449 | for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) { |
450 | map_item(&mem_ffrtab[i], read_biu, 1); |
b96d3df7 |
451 | map_item(&mem_ffwtab[i], write_biu, 1); |
c6b7420b |
452 | } |
b96d3df7 |
453 | |
c6c3b1b3 |
454 | mem_rtab = mem_readtab; |
455 | mem_wtab = mem_writetab; |
b1be1eee |
456 | |
457 | new_dyna_pcsx_mem_load_state(); |
7e605697 |
458 | } |
459 | |
460 | void new_dyna_pcsx_mem_reset(void) |
461 | { |
c6c3b1b3 |
462 | int i; |
463 | |
7e605697 |
464 | // plugins might change so update the pointers |
c6c3b1b3 |
465 | map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
c6c3b1b3 |
466 | |
380cbc61 |
467 | for (i = 0x1c00; i < 0x2000; i += 2) |
c6c3b1b3 |
468 | map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1); |
469 | |
b96d3df7 |
470 | map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
7e605697 |
471 | } |
92879b62 |
472 | |
473 | void new_dyna_pcsx_mem_shutdown(void) |
474 | { |
f3f18aba |
475 | psxUnmap(mem_readtab, 0x200000 * sizeof(mem_readtab[0]), MAP_TAG_LUTS); |
92879b62 |
476 | mem_writetab = mem_readtab = NULL; |
477 | } |