cff531af |
1 | /* |
2 | * PicoDrive |
6a98f03e |
3 | * (C) notaz, 2009,2010,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
be2c4208 |
8 | #include "../pico_int.h" |
974fdb5b |
9 | #include "../sound/ym2612.h" |
51d86e55 |
10 | #include "../../cpu/sh2/compiler.h" |
be2c4208 |
11 | |
12 | struct Pico32x Pico32x; |
83ff19ec |
13 | SH2 sh2s[2]; |
be2c4208 |
14 | |
19886062 |
15 | #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP) |
16 | |
e05b81fc |
17 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
4ea707e1 |
18 | { |
e05b81fc |
19 | if (sh2->pending_irl > sh2->pending_int_irq) { |
f8675e28 |
20 | elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x", |
21 | level, sh2_pc(sh2)); |
e05b81fc |
22 | return 64 + sh2->pending_irl / 2; |
23 | } else { |
f8675e28 |
24 | elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x", |
25 | level, sh2->pending_int_vector, sh2_pc(sh2)); |
e05b81fc |
26 | sh2->pending_int_irq = 0; // auto-clear |
27 | sh2->pending_level = sh2->pending_irl; |
28 | return sh2->pending_int_vector; |
29 | } |
4ea707e1 |
30 | } |
31 | |
c1931173 |
32 | // MUST specify active_sh2 when called from sh2 memhandlers |
4d5dfee8 |
33 | void p32x_update_irls(SH2 *active_sh2, int m68k_cycles) |
4ea707e1 |
34 | { |
35 | int irqs, mlvl = 0, slvl = 0; |
a8fd6e37 |
36 | int mrun, srun; |
4ea707e1 |
37 | |
19886062 |
38 | if (active_sh2 != NULL) |
39 | m68k_cycles = sh2_cycles_done_m68k(active_sh2); |
40 | |
4ea707e1 |
41 | // msh2 |
9e1fa0a6 |
42 | irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0]; |
4ea707e1 |
43 | while ((irqs >>= 1)) |
44 | mlvl++; |
45 | mlvl *= 2; |
46 | |
47 | // ssh2 |
9e1fa0a6 |
48 | irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1]; |
4ea707e1 |
49 | while ((irqs >>= 1)) |
50 | slvl++; |
51 | slvl *= 2; |
52 | |
c1931173 |
53 | mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2); |
54 | if (mrun) { |
19886062 |
55 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles); |
c1931173 |
56 | if (active_sh2 == &msh2) |
57 | sh2_end_run(active_sh2, 1); |
58 | } |
19886062 |
59 | |
c1931173 |
60 | srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2); |
61 | if (srun) { |
19886062 |
62 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles); |
c1931173 |
63 | if (active_sh2 == &ssh2) |
64 | sh2_end_run(active_sh2, 1); |
65 | } |
19886062 |
66 | |
a8fd6e37 |
67 | elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun); |
4ea707e1 |
68 | } |
69 | |
9e1fa0a6 |
70 | // the mask register is inconsistent, CMD is supposed to be a mask, |
71 | // while others are actually irq trigger enables? |
72 | // TODO: test on hw.. |
73 | void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask) |
74 | { |
75 | Pico32x.sh2irqs |= mask & P32XI_VRES; |
76 | Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3); |
77 | Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3); |
78 | |
79 | p32x_update_irls(sh2, m68k_cycles); |
80 | } |
81 | |
82 | void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles) |
83 | { |
84 | if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1)) |
85 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
86 | else |
87 | Pico32x.sh2irqi[0] &= ~P32XI_CMD; |
88 | |
89 | if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2)) |
90 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
91 | else |
92 | Pico32x.sh2irqi[1] &= ~P32XI_CMD; |
93 | |
94 | p32x_update_irls(sh2, m68k_cycles); |
95 | } |
96 | |
be2c4208 |
97 | void Pico32xStartup(void) |
98 | { |
99 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
100 | |
679af8a3 |
101 | // TODO: OOM handling |
93f9619e |
102 | PicoIn.AHW |= PAHW_32X; |
f81107f5 |
103 | sh2_init(&msh2, 0, &ssh2); |
4ea707e1 |
104 | msh2.irq_callback = sh2_irq_cb; |
f81107f5 |
105 | sh2_init(&ssh2, 1, &msh2); |
4ea707e1 |
106 | ssh2.irq_callback = sh2_irq_cb; |
83ff19ec |
107 | |
108 | PicoMemSetup32x(); |
045a4c52 |
109 | p32x_pwm_ctl_changed(); |
a8fd6e37 |
110 | p32x_timers_recalc(); |
acd35d4c |
111 | |
fa8fb754 |
112 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
113 | if (Pico.m.ncart_in) |
114 | Pico32x.sh2_regs[0] |= P32XS_nCART; |
115 | |
be2c4208 |
116 | if (!Pico.m.pal) |
974fdb5b |
117 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
be2c4208 |
118 | |
2446536b |
119 | rendstatus_old = -1; |
120 | |
974fdb5b |
121 | emu_32x_startup(); |
be2c4208 |
122 | } |
123 | |
83ff19ec |
124 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
125 | void p32x_reset_sh2s(void) |
126 | { |
127 | elprintf(EL_32X, "sh2 reset"); |
128 | |
129 | sh2_reset(&msh2); |
130 | sh2_reset(&ssh2); |
cd0ace28 |
131 | sh2_peripheral_reset(&msh2); |
132 | sh2_peripheral_reset(&ssh2); |
83ff19ec |
133 | |
134 | // if we don't have BIOS set, perform it's work here. |
135 | // MSH2 |
136 | if (p32x_bios_m == NULL) { |
83ff19ec |
137 | sh2_set_gbr(0, 0x20004000); |
83ff19ec |
138 | |
93f9619e |
139 | if (!(PicoIn.AHW & PAHW_MCD)) { |
61c4e511 |
140 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
141 | unsigned int vbr; |
142 | |
143 | // initial data |
144 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
145 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
146 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
147 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
148 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
149 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
150 | idl_src, idl_dst, idl_size); |
151 | } |
152 | else |
153 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
154 | |
155 | // VBR |
156 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
157 | sh2_set_vbr(0, vbr); |
158 | |
159 | // checksum and M_OK |
160 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
161 | } |
83ff19ec |
162 | // program will set M_OK |
163 | } |
164 | |
165 | // SSH2 |
166 | if (p32x_bios_s == NULL) { |
167 | unsigned int vbr; |
168 | |
169 | // GBR/VBR |
170 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
171 | sh2_set_gbr(1, 0x20004000); |
172 | sh2_set_vbr(1, vbr); |
173 | // program will set S_OK |
174 | } |
ed4402a7 |
175 | |
ae214f1c |
176 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone(); |
83ff19ec |
177 | } |
178 | |
be2c4208 |
179 | void Pico32xInit(void) |
180 | { |
ed4402a7 |
181 | if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0) |
182 | Pico32xSetClocks(PICO_MSH2_HZ, 0); |
183 | if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0) |
184 | Pico32xSetClocks(0, PICO_MSH2_HZ); |
974fdb5b |
185 | } |
186 | |
187 | void PicoPower32x(void) |
188 | { |
189 | memset(&Pico32x, 0, sizeof(Pico32x)); |
5e49c3a8 |
190 | |
83ff19ec |
191 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
4a1fb183 |
192 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN; |
be2c4208 |
193 | } |
194 | |
5e49c3a8 |
195 | void PicoUnload32x(void) |
196 | { |
197 | if (Pico32xMem != NULL) |
b081408f |
198 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
5e49c3a8 |
199 | Pico32xMem = NULL; |
e898de13 |
200 | sh2_finish(&msh2); |
201 | sh2_finish(&ssh2); |
5e49c3a8 |
202 | |
93f9619e |
203 | PicoIn.AHW &= ~PAHW_32X; |
5e49c3a8 |
204 | } |
205 | |
be2c4208 |
206 | void PicoReset32x(void) |
207 | { |
93f9619e |
208 | if (PicoIn.AHW & PAHW_32X) { |
ae214f1c |
209 | p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES); |
19886062 |
210 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0); |
211 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0); |
045a4c52 |
212 | p32x_pwm_ctl_changed(); |
a8fd6e37 |
213 | p32x_timers_recalc(); |
83ff19ec |
214 | } |
be2c4208 |
215 | } |
216 | |
974fdb5b |
217 | static void p32x_start_blank(void) |
218 | { |
93f9619e |
219 | if (Pico32xDrawMode != PDM32X_OFF && !PicoIn.skipFrame) { |
5aec752d |
220 | int offs, lines; |
221 | |
222 | pprof_start(draw); |
223 | |
224 | offs = 8; lines = 224; |
93f9619e |
225 | if ((Pico.video.reg[1] & 8) && !(PicoIn.opt & POPT_ALT_RENDERER)) { |
7a961c19 |
226 | offs = 0; |
227 | lines = 240; |
228 | } |
229 | |
230 | // XXX: no proper handling of 32col mode.. |
5a681086 |
231 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
232 | (Pico.video.reg[12] & 1) && // 40col mode |
e0bcb7a9 |
233 | (!(Pico.video.debug_p & PVD_KILL_32X))) |
5a681086 |
234 | { |
235 | int md_bg = Pico.video.reg[7] & 0x3f; |
5a681086 |
236 | |
237 | // we draw full layer (not line-by-line) |
238 | PicoDraw32xLayer(offs, lines, md_bg); |
239 | } |
7a961c19 |
240 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
241 | PicoDraw32xLayerMdOnly(offs, lines); |
5aec752d |
242 | |
243 | pprof_end(draw); |
5a681086 |
244 | } |
245 | |
974fdb5b |
246 | // enter vblank |
247 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
248 | |
4ea707e1 |
249 | // FB swap waits until vblank |
974fdb5b |
250 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
251 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
252 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
253 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
254 | } |
4ea707e1 |
255 | |
ae214f1c |
256 | p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT); |
19886062 |
257 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
258 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
974fdb5b |
259 | } |
260 | |
5ac99d9a |
261 | void p32x_schedule_hint(SH2 *sh2, int m68k_cycles) |
262 | { |
263 | // rather rough, 32x hint is useless in practice |
264 | int after; |
265 | |
266 | if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4)) |
267 | return; // nobody cares |
268 | // note: when Pico.m.scanline is 224, SH2s might |
269 | // still be at scanline 93 (or so) |
270 | if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224) |
271 | return; |
272 | |
273 | after = (Pico32x.sh2_regs[4 / 2] + 1) * 488; |
274 | if (sh2 != NULL) |
275 | p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after); |
276 | else |
277 | p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after); |
278 | } |
279 | |
a8fd6e37 |
280 | /* events */ |
a8fd6e37 |
281 | static void fillend_event(unsigned int now) |
282 | { |
283 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN; |
19886062 |
284 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now); |
285 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now); |
a8fd6e37 |
286 | } |
287 | |
5ac99d9a |
288 | static void hint_event(unsigned int now) |
289 | { |
9e1fa0a6 |
290 | p32x_trigger_irq(NULL, now, P32XI_HINT); |
5ac99d9a |
291 | p32x_schedule_hint(NULL, now); |
292 | } |
293 | |
a8fd6e37 |
294 | typedef void (event_cb)(unsigned int now); |
295 | |
ae214f1c |
296 | /* times are in m68k (7.6MHz) cycles */ |
297 | unsigned int p32x_event_times[P32X_EVENT_COUNT]; |
a8fd6e37 |
298 | static unsigned int event_time_next; |
ae214f1c |
299 | static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = { |
24aab4da |
300 | p32x_pwm_irq_event, // P32X_EVENT_PWM |
301 | fillend_event, // P32X_EVENT_FILLEND |
302 | hint_event, // P32X_EVENT_HINT |
a8fd6e37 |
303 | }; |
304 | |
19886062 |
305 | // schedule event at some time 'after', in m68k clocks |
306 | void p32x_event_schedule(unsigned int now, enum p32x_event event, int after) |
a8fd6e37 |
307 | { |
19886062 |
308 | unsigned int when; |
309 | |
310 | when = (now + after) | 1; |
a8fd6e37 |
311 | |
ae214f1c |
312 | elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when); |
313 | p32x_event_times[event] = when; |
a8fd6e37 |
314 | |
19886062 |
315 | if (event_time_next == 0 || CYCLES_GT(event_time_next, when)) |
a8fd6e37 |
316 | event_time_next = when; |
317 | } |
318 | |
19886062 |
319 | void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after) |
320 | { |
321 | unsigned int now = sh2_cycles_done_m68k(sh2); |
322 | int left_to_next; |
323 | |
324 | p32x_event_schedule(now, event, after); |
325 | |
326 | left_to_next = (event_time_next - now) * 3; |
c1931173 |
327 | sh2_end_run(sh2, left_to_next); |
19886062 |
328 | } |
329 | |
ae214f1c |
330 | static void p32x_run_events(unsigned int until) |
a8fd6e37 |
331 | { |
332 | int oldest, oldest_diff, time; |
333 | int i, diff; |
334 | |
335 | while (1) { |
336 | oldest = -1, oldest_diff = 0x7fffffff; |
337 | |
338 | for (i = 0; i < P32X_EVENT_COUNT; i++) { |
ae214f1c |
339 | if (p32x_event_times[i]) { |
340 | diff = p32x_event_times[i] - until; |
a8fd6e37 |
341 | if (diff < oldest_diff) { |
342 | oldest_diff = diff; |
343 | oldest = i; |
344 | } |
345 | } |
346 | } |
347 | |
348 | if (oldest_diff <= 0) { |
ae214f1c |
349 | time = p32x_event_times[oldest]; |
350 | p32x_event_times[oldest] = 0; |
351 | elprintf(EL_32X, "32x: run event #%d %u", oldest, time); |
352 | p32x_event_cbs[oldest](time); |
a8fd6e37 |
353 | } |
354 | else if (oldest_diff < 0x7fffffff) { |
ae214f1c |
355 | event_time_next = p32x_event_times[oldest]; |
a8fd6e37 |
356 | break; |
357 | } |
358 | else { |
359 | event_time_next = 0; |
360 | break; |
361 | } |
362 | } |
363 | |
364 | if (oldest != -1) |
ae214f1c |
365 | elprintf(EL_32X, "32x: next event #%d at %u", |
366 | oldest, event_time_next); |
a8fd6e37 |
367 | } |
368 | |
e9a11abb |
369 | static void run_sh2(SH2 *sh2, int m68k_cycles) |
19886062 |
370 | { |
371 | int cycles, done; |
372 | |
373 | pevt_log_sh2_o(sh2, EVT_RUN_START); |
374 | sh2->state |= SH2_STATE_RUN; |
375 | cycles = C_M68K_TO_SH2(*sh2, m68k_cycles); |
f8675e28 |
376 | elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x", |
377 | sh2->m68krcycles_done, cycles, sh2->pc); |
19886062 |
378 | |
93f9619e |
379 | done = sh2_execute(sh2, cycles, PicoIn.opt & POPT_EN_DRC); |
19886062 |
380 | |
381 | sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done); |
382 | sh2->state &= ~SH2_STATE_RUN; |
383 | pevt_log_sh2_o(sh2, EVT_RUN_END); |
f8675e28 |
384 | elprintf_sh2(sh2, EL_32X, "-run %u %d", |
385 | sh2->m68krcycles_done, done); |
19886062 |
386 | } |
387 | |
388 | // sync other sh2 to this one |
389 | // note: recursive call |
390 | void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target) |
391 | { |
f81107f5 |
392 | SH2 *osh2 = sh2->other_sh2; |
19886062 |
393 | int left_to_event; |
394 | int m68k_cycles; |
395 | |
396 | if (osh2->state & SH2_STATE_RUN) |
397 | return; |
398 | |
399 | m68k_cycles = m68k_target - osh2->m68krcycles_done; |
400 | if (m68k_cycles < 200) |
401 | return; |
402 | |
403 | if (osh2->state & SH2_IDLE_STATES) { |
404 | osh2->m68krcycles_done = m68k_target; |
405 | return; |
406 | } |
407 | |
f8675e28 |
408 | elprintf_sh2(osh2, EL_32X, "sync to %u %d", |
409 | m68k_target, m68k_cycles); |
19886062 |
410 | |
411 | run_sh2(osh2, m68k_cycles); |
412 | |
413 | // there might be new event to schedule current sh2 to |
414 | if (event_time_next) { |
415 | left_to_event = event_time_next - m68k_target; |
416 | left_to_event *= 3; |
417 | if (sh2_cycles_left(sh2) > left_to_event) { |
418 | if (left_to_event < 1) |
419 | left_to_event = 1; |
420 | sh2_end_run(sh2, left_to_event); |
421 | } |
422 | } |
423 | } |
a8fd6e37 |
424 | |
6c2041fe |
425 | #define STEP_LS 24 |
426 | #define STEP_N 440 |
427 | |
ed4402a7 |
428 | #define sync_sh2s_normal p32x_sync_sh2s |
429 | //#define sync_sh2s_lockstep p32x_sync_sh2s |
974fdb5b |
430 | |
a8fd6e37 |
431 | /* most timing is in 68k clock */ |
ed4402a7 |
432 | void sync_sh2s_normal(unsigned int m68k_target) |
433 | { |
a8fd6e37 |
434 | unsigned int now, target, timer_cycles; |
19886062 |
435 | int cycles; |
ed4402a7 |
436 | |
a8fd6e37 |
437 | elprintf(EL_32X, "sh2 sync to %u", m68k_target); |
ed4402a7 |
438 | |
27e26273 |
439 | if (!(Pico32x.regs[0] & P32XS_nRES)) { |
440 | msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target; |
ed4402a7 |
441 | return; // rare |
27e26273 |
442 | } |
ed4402a7 |
443 | |
a8fd6e37 |
444 | now = msh2.m68krcycles_done; |
445 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
446 | now = ssh2.m68krcycles_done; |
447 | timer_cycles = now; |
448 | |
449 | while (CYCLES_GT(m68k_target, now)) |
ed4402a7 |
450 | { |
a8fd6e37 |
451 | if (event_time_next && CYCLES_GE(now, event_time_next)) |
ae214f1c |
452 | p32x_run_events(now); |
ed4402a7 |
453 | |
a8fd6e37 |
454 | target = m68k_target; |
455 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
456 | target = event_time_next; |
6c2041fe |
457 | if (CYCLES_GT(target, now + STEP_N)) |
458 | target = now + STEP_N; |
a8fd6e37 |
459 | |
460 | while (CYCLES_GT(target, now)) |
461 | { |
462 | elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target, |
463 | target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done, |
464 | m68k_target - now, Pico32x.emu_flags); |
ed4402a7 |
465 | |
19886062 |
466 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
a8fd6e37 |
467 | cycles = target - ssh2.m68krcycles_done; |
468 | if (cycles > 0) { |
19886062 |
469 | run_sh2(&ssh2, cycles); |
a8fd6e37 |
470 | |
471 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
472 | target = event_time_next; |
473 | } |
ed4402a7 |
474 | } |
475 | |
19886062 |
476 | if (!(msh2.state & SH2_IDLE_STATES)) { |
a8fd6e37 |
477 | cycles = target - msh2.m68krcycles_done; |
478 | if (cycles > 0) { |
19886062 |
479 | run_sh2(&msh2, cycles); |
a8fd6e37 |
480 | |
481 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
482 | target = event_time_next; |
483 | } |
ed4402a7 |
484 | } |
a8fd6e37 |
485 | |
19886062 |
486 | now = target; |
487 | if (!(msh2.state & SH2_IDLE_STATES)) { |
488 | if (CYCLES_GT(now, msh2.m68krcycles_done)) |
489 | now = msh2.m68krcycles_done; |
490 | } |
491 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
492 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
493 | now = ssh2.m68krcycles_done; |
494 | } |
ed4402a7 |
495 | } |
a8fd6e37 |
496 | |
045a4c52 |
497 | p32x_timers_do(now - timer_cycles); |
a8fd6e37 |
498 | timer_cycles = now; |
ed4402a7 |
499 | } |
19886062 |
500 | |
501 | // advance idle CPUs |
502 | if (msh2.state & SH2_IDLE_STATES) { |
503 | if (CYCLES_GT(m68k_target, msh2.m68krcycles_done)) |
504 | msh2.m68krcycles_done = m68k_target; |
505 | } |
506 | if (ssh2.state & SH2_IDLE_STATES) { |
507 | if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done)) |
508 | ssh2.m68krcycles_done = m68k_target; |
509 | } |
31fbc691 |
510 | |
511 | // everyone is in sync now |
512 | Pico32x.comm_dirty = 0; |
236990cf |
513 | } |
acd35d4c |
514 | |
ed4402a7 |
515 | void sync_sh2s_lockstep(unsigned int m68k_target) |
516 | { |
517 | unsigned int mcycles; |
518 | |
519 | mcycles = msh2.m68krcycles_done; |
520 | if (ssh2.m68krcycles_done < mcycles) |
521 | mcycles = ssh2.m68krcycles_done; |
522 | |
523 | while (mcycles < m68k_target) { |
6c2041fe |
524 | mcycles += STEP_LS; |
ed4402a7 |
525 | sync_sh2s_normal(mcycles); |
526 | } |
87accdf7 |
527 | } |
528 | |
ae214f1c |
529 | #define CPUS_RUN(m68k_cycles) do { \ |
93f9619e |
530 | if (PicoIn.AHW & PAHW_MCD) \ |
fa8fb754 |
531 | pcd_run_cpus(m68k_cycles); \ |
532 | else \ |
533 | SekRunM68k(m68k_cycles); \ |
534 | \ |
ae214f1c |
535 | if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \ |
93f9619e |
536 | && !Pico.m.z80_reset && (PicoIn.opt & POPT_EN_Z80)) \ |
ae214f1c |
537 | PicoSyncZ80(SekCyclesDone()); \ |
19886062 |
538 | if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \ |
ae214f1c |
539 | p32x_sync_sh2s(SekCyclesDone()); \ |
ed4402a7 |
540 | } while (0) |
87accdf7 |
541 | |
ed4402a7 |
542 | #define PICO_32X |
fa8fb754 |
543 | #define PICO_CD |
974fdb5b |
544 | #include "../pico_cmn.c" |
545 | |
546 | void PicoFrame32x(void) |
547 | { |
5ac99d9a |
548 | Pico.m.scanline = 0; |
549 | |
4ea707e1 |
550 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
db1d3564 |
551 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
552 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
4ea707e1 |
553 | |
5ac99d9a |
554 | if (!(Pico32x.sh2_regs[0] & 0x80)) |
ae214f1c |
555 | p32x_schedule_hint(NULL, SekCyclesDone()); |
19886062 |
556 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
557 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
974fdb5b |
558 | |
93f9619e |
559 | if (PicoIn.AHW & PAHW_MCD) |
a6523294 |
560 | pcd_prepare_frame(); |
561 | |
974fdb5b |
562 | PicoFrameStart(); |
563 | PicoFrameHints(); |
51d86e55 |
564 | sh2_drc_frame(); |
565 | |
19886062 |
566 | elprintf(EL_32X, "poll: %02x %02x %02x", |
567 | Pico32x.emu_flags & 3, msh2.state, ssh2.state); |
974fdb5b |
568 | } |
db1d3564 |
569 | |
ed4402a7 |
570 | // calculate multipliers against 68k clock (7670442) |
571 | // normally * 3, but effectively slower due to high latencies everywhere |
572 | // however using something lower breaks MK2 animations |
573 | void Pico32xSetClocks(int msh2_hz, int ssh2_hz) |
574 | { |
575 | float m68k_clk = (float)(OSC_NTSC / 7); |
576 | if (msh2_hz > 0) { |
577 | msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
578 | msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz); |
579 | } |
580 | if (ssh2_hz > 0) { |
581 | ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
582 | ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz); |
583 | } |
584 | } |
585 | |
27e26273 |
586 | void Pico32xStateLoaded(int is_early) |
587 | { |
588 | if (is_early) { |
589 | Pico32xMemStateLoaded(); |
590 | return; |
591 | } |
592 | |
ae214f1c |
593 | sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone(); |
594 | p32x_update_irls(NULL, SekCyclesDone()); |
df63f1a6 |
595 | p32x_pwm_state_loaded(); |
ae214f1c |
596 | p32x_run_events(SekCyclesDone()); |
27e26273 |
597 | } |
598 | |
ed4402a7 |
599 | // vim:shiftwidth=2:ts=2:expandtab |