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1 | #include "../pico_int.h" |
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2 | #include "../sound/ym2612.h" |
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3 | |
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4 | SH2 sh2s[2]; |
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5 | struct Pico32x Pico32x; |
6 | |
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7 | static void sh2_irq_cb(int id, int level) |
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8 | { |
9 | // diagnostic for now |
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10 | elprintf(EL_32X, "%csh2 ack %d @ %08x", id ? 's' : 'm', level, sh2_pc(id)); |
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11 | } |
12 | |
13 | void p32x_update_irls(void) |
14 | { |
15 | int irqs, mlvl = 0, slvl = 0; |
16 | |
17 | // msh2 |
18 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
19 | while ((irqs >>= 1)) |
20 | mlvl++; |
21 | mlvl *= 2; |
22 | |
23 | // ssh2 |
24 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
25 | while ((irqs >>= 1)) |
26 | slvl++; |
27 | slvl *= 2; |
28 | |
29 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
30 | sh2_irl_irq(&msh2, mlvl); |
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31 | sh2_irl_irq(&ssh2, slvl); |
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32 | mlvl = mlvl ? 1 : 0; |
33 | slvl = slvl ? 1 : 0; |
34 | p32x_poll_event(mlvl | (slvl << 1), 0); |
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35 | } |
36 | |
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37 | void Pico32xStartup(void) |
38 | { |
39 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
40 | |
41 | PicoAHW |= PAHW_32X; |
42 | PicoMemSetup32x(); |
43 | |
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44 | sh2_init(&msh2, 0); |
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45 | msh2.irq_callback = sh2_irq_cb; |
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46 | sh2_reset(&msh2); |
47 | |
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48 | sh2_init(&ssh2, 1); |
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49 | ssh2.irq_callback = sh2_irq_cb; |
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50 | sh2_reset(&ssh2); |
51 | |
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52 | if (!Pico.m.pal) |
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53 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
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54 | |
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55 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
56 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
57 | |
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58 | emu_32x_startup(); |
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59 | } |
60 | |
61 | void Pico32xInit(void) |
62 | { |
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63 | } |
64 | |
65 | void PicoPower32x(void) |
66 | { |
67 | memset(&Pico32x, 0, sizeof(Pico32x)); |
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68 | |
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69 | Pico32x.regs[0] = 0x0082; // SH2 reset? |
70 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
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71 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
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72 | } |
73 | |
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74 | void PicoUnload32x(void) |
75 | { |
76 | if (Pico32xMem != NULL) |
77 | free(Pico32xMem); |
78 | Pico32xMem = NULL; |
79 | |
80 | PicoAHW &= ~PAHW_32X; |
81 | } |
82 | |
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83 | void PicoReset32x(void) |
84 | { |
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85 | extern int p32x_csum_faked; |
86 | p32x_csum_faked = 0; // tmp |
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87 | } |
88 | |
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89 | static void p32x_start_blank(void) |
90 | { |
91 | // enter vblank |
92 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
93 | |
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94 | // FB swap waits until vblank |
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95 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
96 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
97 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
98 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
99 | } |
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100 | |
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101 | Pico32x.sh2irqs |= P32XI_VINT; |
102 | p32x_update_irls(); |
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103 | p32x_poll_event(3, 1); |
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104 | } |
105 | |
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106 | static __inline void run_m68k(int cyc) |
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107 | { |
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108 | if (Pico32x.emu_flags & P32XF_68KPOLL) { |
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109 | SekCycleCnt += cyc; |
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110 | return; |
111 | } |
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112 | #if defined(EMU_C68K) |
113 | PicoCpuCM68k.cycles = cyc; |
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114 | CycloneRun(&PicoCpuCM68k); |
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115 | SekCycleCnt += cyc - PicoCpuCM68k.cycles; |
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116 | #elif defined(EMU_M68K) |
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117 | SekCycleCnt += m68k_execute(cyc); |
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118 | #elif defined(EMU_F68K) |
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119 | SekCycleCnt += fm68k_emulate(cyc+1, 0, 0); |
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120 | #endif |
121 | } |
122 | |
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123 | // ~1463.8, but due to cache misses and slow mem |
124 | // it's much lower than that |
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125 | //#define SH2_LINE_CYCLES 735 |
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126 | #define CYCLES_M68K2SH2(x) ((x) * 6 / 4) |
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127 | |
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128 | #define PICO_32X |
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129 | #define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \ |
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130 | { \ |
131 | int slice; \ |
132 | SekCycleAim += m68k_cycles; \ |
133 | while (SekCycleCnt < SekCycleAim) { \ |
134 | slice = SekCycleCnt; \ |
135 | run_m68k(SekCycleAim - SekCycleCnt); \ |
136 | slice = SekCycleCnt - slice; /* real count from 68k */ \ |
137 | if (SekCycleCnt < SekCycleAim) \ |
138 | elprintf(EL_32X, "slice %d", slice); \ |
139 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
140 | sh2_execute(&ssh2, CYCLES_M68K2SH2(slice)); \ |
141 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
142 | sh2_execute(&msh2, CYCLES_M68K2SH2(slice)); \ |
143 | } \ |
144 | } |
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145 | |
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146 | #define STEP_68K 24 |
147 | #define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \ |
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148 | { \ |
149 | int i; \ |
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150 | for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \ |
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151 | run_m68k(STEP_68K); \ |
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152 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
153 | sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \ |
154 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
155 | sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \ |
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156 | } \ |
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157 | /* last step */ \ |
158 | i = (m68k_cycles) - i; \ |
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159 | run_m68k(i); \ |
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160 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
161 | sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \ |
162 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
163 | sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \ |
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164 | } |
165 | |
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166 | #define CPUS_RUN CPUS_RUN_SIMPLE |
167 | //#define CPUS_RUN CPUS_RUN_LOCKSTEP |
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168 | |
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169 | #include "../pico_cmn.c" |
170 | |
171 | void PicoFrame32x(void) |
172 | { |
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173 | pwm_frame_smp_cnt = 0; |
174 | |
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175 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
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176 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
177 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
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178 | |
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179 | p32x_poll_event(3, 1); |
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180 | |
181 | PicoFrameStart(); |
182 | PicoFrameHints(); |
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183 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
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184 | } |
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185 | |