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[picodrive.git] / pico / carthw / svp / compiler.c
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cff531af 1/*
2 * SSP1601 to ARM recompiler
3 * (C) notaz, 2008,2009,2010
7bf552b5 4 * (C) irixxxx, 2019-2023
cff531af 5 *
6 * This work is licensed under the terms of MAME license.
7 * See COPYING file in the top-level directory.
8 */
726bbb3e 9
f821bb70 10#include <pico/pico_int.h>
11#include <cpu/drc/cmn.h>
e807ac75 12#include "compiler.h"
726bbb3e 13
679af8a3 14// FIXME: asm has these hardcoded
15#define SSP_BLOCKTAB_ENTS (0x5090/2)
16#define SSP_BLOCKTAB_IRAM_ONE (0x800/2) // table entries
17#define SSP_BLOCKTAB_IRAM_ENTS (15*SSP_BLOCKTAB_IRAM_ONE)
18
19static u32 **ssp_block_table; // [0x5090/2];
20static u32 **ssp_block_table_iram; // [15][0x800/2];
71bb1b7b 21
71bb1b7b 22static u32 *tcache_ptr = NULL;
726bbb3e 23
726bbb3e 24static int nblocks = 0;
71bb1b7b 25static int n_in_ops = 0;
26
27extern ssp1601_t *ssp;
28
29#define rPC ssp->gr[SSP_PC].h
30#define rPMC ssp->gr[SSP_PMC]
31
32#define SSP_FLAG_Z (1<<0xd)
33#define SSP_FLAG_N (1<<0xf)
726bbb3e 34
d4d62665 35#ifndef __arm__
679af8a3 36//#define DUMP_BLOCK 0x0c9a
45883918 37void ssp_drc_next(void){}
38void ssp_drc_next_patch(void){}
39void ssp_drc_end(void){}
5d817c91 40#endif
41
553c3eaa 42#define COUNT_OP
f821bb70 43#include <cpu/drc/emit_arm.c>
726bbb3e 44
45// -----------------------------------------------------
46
71bb1b7b 47static int get_inc(int mode)
892b1dd2 48{
71bb1b7b 49 int inc = (mode >> 11) & 7;
50 if (inc != 0) {
51 if (inc != 7) inc--;
52 inc = 1 << inc; // 0 1 2 4 8 16 32 128
53 if (mode & 0x8000) inc = -inc; // decrement mode
892b1dd2 54 }
71bb1b7b 55 return inc;
892b1dd2 56}
57
ee9ee9fd 58u32 ssp_pm_read(int reg)
d5276282 59{
60 u32 d = 0, mode;
61
62 if (ssp->emu_status & SSP_PMC_SET)
63 {
64 ssp->pmac_read[reg] = rPMC.v;
65 ssp->emu_status &= ~SSP_PMC_SET;
d5276282 66 return 0;
67 }
68
d5276282 69 // just in case
70 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
71
72 mode = ssp->pmac_read[reg]>>16;
73 if ((mode & 0xfff0) == 0x0800) // ROM
74 {
75 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
76 ssp->pmac_read[reg] += 1;
77 }
78 else if ((mode & 0x47ff) == 0x0018) // DRAM
79 {
80 unsigned short *dram = (unsigned short *)svp->dram;
81 int inc = get_inc(mode);
82 d = dram[ssp->pmac_read[reg]&0xffff];
83 ssp->pmac_read[reg] += inc;
84 }
85
86 // PMC value corresponds to last PMR accessed
87 rPMC.v = ssp->pmac_read[reg];
88
89 return d;
90}
91
71bb1b7b 92#define overwrite_write(dst, d) \
93{ \
94 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
95 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
96 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
97 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
98}
99
ee9ee9fd 100void ssp_pm_write(u32 d, int reg)
d5276282 101{
102 unsigned short *dram;
103 int mode, addr;
104
105 if (ssp->emu_status & SSP_PMC_SET)
106 {
107 ssp->pmac_write[reg] = rPMC.v;
108 ssp->emu_status &= ~SSP_PMC_SET;
109 return;
110 }
111
112 // just in case
113 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
114
115 dram = (unsigned short *)svp->dram;
116 mode = ssp->pmac_write[reg]>>16;
117 addr = ssp->pmac_write[reg]&0xffff;
118 if ((mode & 0x43ff) == 0x0018) // DRAM
119 {
120 int inc = get_inc(mode);
121 if (mode & 0x0400) {
122 overwrite_write(dram[addr], d);
123 } else dram[addr] = d;
124 ssp->pmac_write[reg] += inc;
125 }
126 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
127 {
128 if (mode & 0x0400) {
129 overwrite_write(dram[addr], d);
130 } else dram[addr] = d;
34e243f1 131 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
d5276282 132 }
133 else if ((mode & 0x47ff) == 0x001c) // IRAM
134 {
135 int inc = get_inc(mode);
136 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
137 ssp->pmac_write[reg] += inc;
e122fae6 138 ssp->drc.iram_dirty = 1;
d5276282 139 }
140
141 rPMC.v = ssp->pmac_write[reg];
142}
143
144
892b1dd2 145// -----------------------------------------------------
146
0b5e8296 147// 14 IRAM blocks
df143b36 148static unsigned char iram_context_map[] =
149{
150 0, 0, 0, 0, 1, 0, 0, 0, // 04
151 0, 0, 0, 0, 0, 0, 2, 0, // 0e
152 0, 0, 0, 0, 0, 3, 0, 4, // 15 17
153 5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
154 8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
155 0, 0, 0, 0, 0, 0, 0, 0,
156 0, 0,11, 0, 0,12, 0, 0, // 32 35
157 13,14, 0, 0, 0, 0, 0, 0 // 38 39
158};
159
71bb1b7b 160int ssp_get_iram_context(void)
df143b36 161{
162 unsigned char *ir = (unsigned char *)svp->iram_rom;
163 int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
df143b36 164 val1 = iram_context_map[(val>>1)&0x3f];
165
5c129565 166 if (val1 == 0) {
2d2247c2 167 elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
df143b36 168 //debug_dump2file(name, svp->iram_rom, 0x800);
2d2247c2 169 //exit(1);
df143b36 170 }
df143b36 171 return val1;
172}
173
5d817c91 174// -----------------------------------------------------
0b5e8296 175
5d817c91 176/* regs with known values */
177static struct
178{
179 ssp_reg_t gr[8];
180 unsigned char r[8];
ede7220f 181 unsigned int pmac_read[5];
182 unsigned int pmac_write[5];
d5276282 183 ssp_reg_t pmc;
ede7220f 184 unsigned int emu_status;
bad5731d 185} known_regs;
186
187#define KRREG_X (1 << SSP_X)
188#define KRREG_Y (1 << SSP_Y)
189#define KRREG_A (1 << SSP_A) /* AH only */
190#define KRREG_ST (1 << SSP_ST)
191#define KRREG_STACK (1 << SSP_STACK)
192#define KRREG_PC (1 << SSP_PC)
193#define KRREG_P (1 << SSP_P)
194#define KRREG_PR0 (1 << 8)
195#define KRREG_PR4 (1 << 12)
196#define KRREG_AL (1 << 16)
d5276282 197#define KRREG_PMCM (1 << 18) /* only mode word of PMC */
198#define KRREG_PMC (1 << 19)
ede7220f 199#define KRREG_PM0R (1 << 20)
200#define KRREG_PM1R (1 << 21)
201#define KRREG_PM2R (1 << 22)
202#define KRREG_PM3R (1 << 23)
203#define KRREG_PM4R (1 << 24)
204#define KRREG_PM0W (1 << 25)
205#define KRREG_PM1W (1 << 26)
206#define KRREG_PM2W (1 << 27)
207#define KRREG_PM3W (1 << 28)
208#define KRREG_PM4W (1 << 29)
bad5731d 209
210/* bitfield of known register values */
211static u32 known_regb = 0;
212
213/* known vals, which need to be flushed
d5276282 214 * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
bad5731d 215 * ST means flags are being held in ARM PSR
89fea1e9 216 * P means that it needs to be recalculated
bad5731d 217 */
218static u32 dirty_regb = 0;
5d817c91 219
220/* known values of host regs.
d274c33b 221 * -1 - unknown
222 * 000000-00ffff - 16bit value
223 * 100000-10ffff - base reg (r7) + 16bit val
6e39239f 224 * 0r0000 - means reg (low) eq gr[r].h, r != AL
5d817c91 225 */
226static int hostreg_r[4];
227
228static void hostreg_clear(void)
229{
230 int i;
231 for (i = 0; i < 4; i++)
232 hostreg_r[i] = -1;
233}
234
6e39239f 235static void hostreg_sspreg_changed(int sspreg)
5d817c91 236{
237 int i;
238 for (i = 0; i < 4; i++)
6e39239f 239 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
5d817c91 240}
241
726bbb3e 242
ede7220f 243#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
244#define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
726bbb3e 245
ee9ee9fd 246void tr_unhandled(void)
6e39239f 247{
2d2247c2 248 //FILE *f = fopen("tcache.bin", "wb");
249 //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
250 //fclose(f);
251 elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
252 //exit(1);
6e39239f 253}
254
0e4d7ba5 255/* update P, if needed. Trashes r0 */
d274c33b 256static void tr_flush_dirty_P(void)
257{
258 // TODO: const regs
bad5731d 259 if (!(dirty_regb & KRREG_P)) return;
d274c33b 260 EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
0e4d7ba5 261 EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
262 EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
263 EOP_MUL(10, 0, 10); // mul r10, r0, r10
bad5731d 264 dirty_regb &= ~KRREG_P;
0e4d7ba5 265 hostreg_r[0] = -1;
d274c33b 266}
267
89fea1e9 268/* write dirty pr to host reg. Nothing is trashed */
269static void tr_flush_dirty_pr(int r)
270{
271 int ror = 0, reg;
6e39239f 272
89fea1e9 273 if (!(dirty_regb & (1 << (r+8)))) return;
274
275 switch (r&3) {
276 case 0: ror = 0; break;
277 case 1: ror = 24/2; break;
278 case 2: ror = 16/2; break;
279 }
280 reg = (r < 4) ? 8 : 9;
281 EOP_BIC_IMM(reg,reg,ror,0xff);
282 if (known_regs.r[r] != 0)
283 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
284 dirty_regb &= ~(1 << (r+8));
285}
286
287/* write all dirty pr0-pr7 to host regs. Nothing is trashed */
288static void tr_flush_dirty_prs(void)
5d817c91 289{
290 int i, ror = 0, reg;
bad5731d 291 int dirty = dirty_regb >> 8;
2385f273 292 if ((dirty&7) == 7) {
65c75cb0 293 emith_move_r_imm(8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
2385f273 294 dirty &= ~7;
295 }
296 if ((dirty&0x70) == 0x70) {
65c75cb0 297 emith_move_r_imm(9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
2385f273 298 dirty &= ~0x70;
299 }
5d817c91 300 /* r0-r7 */
bad5731d 301 for (i = 0; dirty && i < 8; i++, dirty >>= 1)
5d817c91 302 {
bad5731d 303 if (!(dirty&1)) continue;
5d817c91 304 switch (i&3) {
305 case 0: ror = 0; break;
306 case 1: ror = 24/2; break;
307 case 2: ror = 16/2; break;
308 }
309 reg = (i < 4) ? 8 : 9;
310 EOP_BIC_IMM(reg,reg,ror,0xff);
bad5731d 311 if (known_regs.r[i] != 0)
312 EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
5d817c91 313 }
bad5731d 314 dirty_regb &= ~0xff00;
315}
316
89fea1e9 317/* write dirty pr and "forget" it. Nothing is trashed. */
318static void tr_release_pr(int r)
319{
320 tr_flush_dirty_pr(r);
321 known_regb &= ~(1 << (r+8));
322}
323
6e39239f 324/* fush ARM PSR to r6. Trashes r1 */
bad5731d 325static void tr_flush_dirty_ST(void)
326{
327 if (!(dirty_regb & KRREG_ST)) return;
328 EOP_BIC_IMM(6,6,0,0x0f);
6e39239f 329 EOP_MRS(1);
330 EOP_ORR_REG_LSR(6,6,1,28);
bad5731d 331 dirty_regb &= ~KRREG_ST;
6e39239f 332 hostreg_r[1] = -1;
333}
334
335/* inverse of above. Trashes r1 */
336static void tr_make_dirty_ST(void)
337{
338 if (dirty_regb & KRREG_ST) return;
339 if (known_regb & KRREG_ST) {
340 int flags = 0;
341 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
342 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
343 EOP_MSR_IMM(4/2, flags);
344 } else {
345 EOP_MOV_REG_LSL(1, 6, 28);
346 EOP_MSR_REG(1);
347 hostreg_r[1] = -1;
348 }
349 dirty_regb |= KRREG_ST;
bad5731d 350}
351
352/* load 16bit val into host reg r0-r3. Nothing is trashed */
353static void tr_mov16(int r, int val)
354{
355 if (hostreg_r[r] != val) {
65c75cb0 356 emith_move_r_imm(r, val);
bad5731d 357 hostreg_r[r] = val;
358 }
359}
360
361static void tr_mov16_cond(int cond, int r, int val)
362{
a80b0b42 363 emith_move_r_imm_c(cond, r, val);
a6fb500b 364 hostreg_r[r] = -1;
5d817c91 365}
366
45883918 367/* trashes r1 */
ede7220f 368static void tr_flush_dirty_pmcrs(void)
369{
370 u32 i, val = (u32)-1;
d5276282 371 if (!(dirty_regb & 0x3ff80000)) return;
ede7220f 372
d5276282 373 if (dirty_regb & KRREG_PMC) {
374 val = known_regs.pmc.v;
65c75cb0 375 emith_move_r_imm(1, val);
e122fae6 376 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
ede7220f 377
d5276282 378 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
2d2247c2 379 elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
d5276282 380 tr_unhandled();
381 }
ede7220f 382 }
383 for (i = 0; i < 5; i++)
384 {
d5276282 385 if (dirty_regb & (1 << (20+i))) {
ede7220f 386 if (val != known_regs.pmac_read[i]) {
387 val = known_regs.pmac_read[i];
65c75cb0 388 emith_move_r_imm(1, val);
ede7220f 389 }
e122fae6 390 EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
ede7220f 391 }
d5276282 392 if (dirty_regb & (1 << (25+i))) {
ede7220f 393 if (val != known_regs.pmac_write[i]) {
394 val = known_regs.pmac_write[i];
65c75cb0 395 emith_move_r_imm(1, val);
ede7220f 396 }
e122fae6 397 EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
ede7220f 398 }
399 }
d5276282 400 dirty_regb &= ~0x3ff80000;
e122fae6 401 hostreg_r[1] = -1;
ede7220f 402}
403
0e4d7ba5 404/* read bank word to r0 (upper bits zero). Thrashes r1. */
5d817c91 405static void tr_bank_read(int addr) /* word addr 0-0x1ff */
406{
bad5731d 407 int breg = 7;
408 if (addr > 0x7f) {
409 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
410 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
411 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
5d817c91 412 }
bad5731d 413 breg = 1;
5d817c91 414 }
bad5731d 415 EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
5d817c91 416 hostreg_r[0] = -1;
417}
418
419/* write r0 to bank. Trashes r1. */
420static void tr_bank_write(int addr)
421{
422 int breg = 7;
423 if (addr > 0x7f) {
d274c33b 424 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
5d817c91 425 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
d274c33b 426 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
5d817c91 427 }
428 breg = 1;
429 }
b9c1d012 430 EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
5d817c91 431}
432
89fea1e9 433/* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
434static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
5d817c91 435{
a6fb500b 436 int modulo_shift = -1; /* unknown */
5d817c91 437
438 if (mod == 0) return;
439
440 if (!need_modulo || mod == 1) // +!
441 modulo_shift = 8;
bad5731d 442 else if (need_modulo && (known_regb & KRREG_ST)) {
443 modulo_shift = known_regs.gr[SSP_ST].h & 7;
5d817c91 444 if (modulo_shift == 0) modulo_shift = 8;
445 }
446
89fea1e9 447 if (modulo_shift == -1)
448 {
a6fb500b 449 int reg = (r < 4) ? 8 : 9;
89fea1e9 450 tr_release_pr(r);
0e4d7ba5 451 if (dirty_regb & KRREG_ST) {
452 // avoid flushing ARM flags
453 EOP_AND_IMM(1, 6, 0, 0x70);
454 EOP_SUB_IMM(1, 1, 0, 0x10);
455 EOP_AND_IMM(1, 1, 0, 0x70);
456 EOP_ADD_IMM(1, 1, 0, 0x10);
457 } else {
458 EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
459 EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
460 }
89fea1e9 461 EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
462 EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
463 EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
464 if (r&3)
465 EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
466 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
467 if (mod == 2)
468 EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
469 else EOP_ADD_REG2_LSL(reg,reg,3,2);
470 EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
471 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
472 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
a6fb500b 473 }
474 else if (known_regb & (1 << (r + 8)))
475 {
476 int modulo = (1 << modulo_shift) - 1;
5d817c91 477 if (mod == 2)
89fea1e9 478 known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
479 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
a833e78c 480 dirty_regb |= (1 << (r + 8));
a6fb500b 481 }
482 else
483 {
5d817c91 484 int reg = (r < 4) ? 8 : 9;
485 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
486 EOP_MOV_REG_ROR(reg,reg,ror);
487 // {add|sub} reg, reg, #1<<shift
89fea1e9 488 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
5d817c91 489 EOP_MOV_REG_ROR(reg,reg,32-ror);
490 }
491}
492
bad5731d 493/* handle writes r0 to (rX). Trashes r1.
494 * fortunately we can ignore modulo increment modes for writes. */
0e4d7ba5 495static void tr_rX_write(int op)
bad5731d 496{
497 if ((op&3) == 3)
498 {
499 int mod = (op>>2) & 3; // direct addressing
500 tr_bank_write((op & 0x100) + mod);
501 }
502 else
503 {
504 int r = (op&3) | ((op>>6)&4);
505 if (known_regb & (1 << (r + 8))) {
506 tr_bank_write((op&0x100) | known_regs.r[r]);
507 } else {
508 int reg = (r < 4) ? 8 : 9;
509 int ror = ((4 - (r&3))*8) & 0x1f;
510 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
511 if (r >= 4)
512 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
513 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
514 else EOP_ADD_REG_LSL(1,7,1,1);
515 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
516 hostreg_r[1] = -1;
517 }
89fea1e9 518 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
519 }
520}
521
522/* read (rX) to r0. Trashes r1-r3. */
523static void tr_rX_read(int r, int mod)
524{
525 if ((r&3) == 3)
526 {
527 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
528 }
529 else
530 {
531 if (known_regb & (1 << (r + 8))) {
6e39239f 532 tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
89fea1e9 533 } else {
534 int reg = (r < 4) ? 8 : 9;
535 int ror = ((4 - (r&3))*8) & 0x1f;
536 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
537 if (r >= 4)
538 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
539 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
540 else EOP_ADD_REG_LSL(1,7,1,1);
541 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
0e4d7ba5 542 hostreg_r[0] = hostreg_r[1] = -1;
89fea1e9 543 }
544 tr_ptrr_mod(r, mod, 1, 1);
bad5731d 545 }
546}
547
0e4d7ba5 548/* read ((rX)) to r0. Trashes r1,r2. */
549static void tr_rX_read2(int op)
550{
551 int r = (op&3) | ((op>>6)&4); // src
552
553 if ((r&3) == 3) {
554 tr_bank_read((op&0x100) | ((op>>2)&3));
555 } else if (known_regb & (1 << (r+8))) {
556 tr_bank_read((op&0x100) | known_regs.r[r]);
557 } else {
558 int reg = (r < 4) ? 8 : 9;
559 int ror = ((4 - (r&3))*8) & 0x1f;
560 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
561 if (r >= 4)
562 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
563 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
564 else EOP_ADD_REG_LSL(1,7,1,1);
565 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
566 }
567 EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
568 EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
569 EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
570 if ((r&3) == 3) {
571 tr_bank_write((op&0x100) | ((op>>2)&3));
572 } else if (known_regb & (1 << (r+8))) {
573 tr_bank_write((op&0x100) | known_regs.r[r]);
574 } else {
575 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
576 hostreg_r[1] = -1;
577 }
578 EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
579 hostreg_r[0] = hostreg_r[2] = -1;
580}
89fea1e9 581
2385f273 582// check if AL is going to be used later in block
583static int tr_predict_al_need(void)
584{
585 int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
586
587 while (1)
588 {
589 op = PROGRAM(pc);
590 switch (op >> 9)
591 {
592 // ld d, s
593 case 0x00:
594 tmpv2 = (op >> 4) & 0xf; // dst
595 tmpv = op & 0xf; // src
596 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
597 return 0;
598 break;
599
600 // ld (ri), s
601 case 0x02:
602 // ld ri, s
603 case 0x0a:
604 // OP a, s
605 case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
606 tmpv = op & 0xf; // src
607 if (tmpv == SSP_AL) // OP *, AL
608 return 1;
609 break;
610
611 case 0x04:
612 case 0x06:
613 case 0x14:
614 case 0x34:
615 case 0x44:
616 case 0x64:
617 case 0x74: pc++; break;
618
619 // call cond, addr
620 case 0x24:
621 // bra cond, addr
622 case 0x26:
623 // mod cond, op
624 case 0x48:
625 // mpys?
626 case 0x1b:
627 // mpya (rj), (ri), b
628 case 0x4b: return 1;
629
630 // mld (rj), (ri), b
631 case 0x5b: return 0; // cleared anyway
632
633 // and A, *
634 case 0x50:
635 tmpv = op & 0xf; // src
636 if (tmpv == SSP_AL) return 1;
637 case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
638 return 0;
639 }
640 pc++;
641 }
642}
643
644
bad5731d 645/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
646static int tr_cond_check(int op)
647{
6e39239f 648 int f = (op & 0x100) >> 8;
bad5731d 649 switch (op&0xf0) {
650 case 0x00: return A_COND_AL; /* always true */
651 case 0x50: /* Z matches f(?) bit */
652 if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
653 EOP_TST_IMM(6, 0, 4);
654 return f ? A_COND_NE : A_COND_EQ;
655 case 0x70: /* N matches f(?) bit */
656 if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
657 EOP_TST_IMM(6, 0, 8);
658 return f ? A_COND_NE : A_COND_EQ;
659 default:
2d2247c2 660 elprintf(EL_ANOMALY, "unimplemented cond?\n");
6e39239f 661 tr_unhandled();
bad5731d 662 return 0;
663 }
664}
665
666static int tr_neg_cond(int cond)
667{
668 switch (cond) {
2d2247c2 669 case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
bad5731d 670 case A_COND_EQ: return A_COND_NE;
671 case A_COND_NE: return A_COND_EQ;
672 case A_COND_MI: return A_COND_PL;
673 case A_COND_PL: return A_COND_MI;
2d2247c2 674 default: elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
bad5731d 675 }
676 return 0;
677}
678
ede7220f 679static int tr_aop_ssp2arm(int op)
680{
681 switch (op) {
682 case 1: return A_OP_SUB;
683 case 3: return A_OP_CMP;
684 case 4: return A_OP_ADD;
685 case 5: return A_OP_AND;
686 case 6: return A_OP_ORR;
687 case 7: return A_OP_EOR;
688 }
689
690 tr_unhandled();
691 return 0;
692}
693
989ba52a 694#ifdef __MACH__
695/* spacial version of call for calling C needed on ios, since we use r9.. */
696static void emith_call_c_func(void *target)
697{
35984c21 698 EOP_STMFD_SP(M2(7,9));
989ba52a 699 emith_call(target);
35984c21 700 EOP_LDMFD_SP(M2(7,9));
989ba52a 701}
702#else
703#define emith_call_c_func emith_call
704#endif
705
ede7220f 706// -----------------------------------------------------
707
b9c1d012 708//@ r4: XXYY
709//@ r5: A
710//@ r6: STACK and emu flags
711//@ r7: SSP context
712//@ r10: P
713
bad5731d 714// read general reg to r0. Trashes r1
d5276282 715static void tr_GR0_to_r0(int op)
d274c33b 716{
717 tr_mov16(0, 0xffff);
718}
719
d5276282 720static void tr_X_to_r0(int op)
d274c33b 721{
722 if (hostreg_r[0] != (SSP_X<<16)) {
723 EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
724 hostreg_r[0] = SSP_X<<16;
725 }
726}
727
d5276282 728static void tr_Y_to_r0(int op)
d274c33b 729{
d274c33b 730 if (hostreg_r[0] != (SSP_Y<<16)) {
731 EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
732 hostreg_r[0] = SSP_Y<<16;
733 }
734}
735
d5276282 736static void tr_A_to_r0(int op)
d274c33b 737{
738 if (hostreg_r[0] != (SSP_A<<16)) {
739 EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
740 hostreg_r[0] = SSP_A<<16;
741 }
742}
743
d5276282 744static void tr_ST_to_r0(int op)
d274c33b 745{
746 // VR doesn't need much accuracy here..
747 EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
748 EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
749 hostreg_r[0] = -1;
750}
751
d5276282 752static void tr_STACK_to_r0(int op)
d274c33b 753{
754 // 448
755 EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
756 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
757 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
758 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
759 EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
760 hostreg_r[0] = hostreg_r[1] = -1;
761}
762
d5276282 763static void tr_PC_to_r0(int op)
d274c33b 764{
bad5731d 765 tr_mov16(0, known_regs.gr[SSP_PC].h);
d274c33b 766}
767
d5276282 768static void tr_P_to_r0(int op)
d274c33b 769{
770 tr_flush_dirty_P();
771 EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
772 hostreg_r[0] = -1;
773}
d5276282 774
775static void tr_AL_to_r0(int op)
ede7220f 776{
d5276282 777 if (op == 0x000f) {
778 if (known_regb & KRREG_PMC) {
779 known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
780 } else {
781 EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status
782 EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
783 EOP_STR_IMM(0,7,0x484);
784 }
785 }
786
787 if (hostreg_r[0] != (SSP_AL<<16)) {
788 EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5
789 hostreg_r[0] = SSP_AL<<16;
790 }
ede7220f 791}
ede7220f 792
d5276282 793static void tr_PMX_to_r0(int reg)
ede7220f 794{
ede7220f 795 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
796 {
d5276282 797 known_regs.pmac_read[reg] = known_regs.pmc.v;
ede7220f 798 known_regs.emu_status &= ~SSP_PMC_SET;
0336d643 799 known_regb |= 1 << (20+reg);
d5276282 800 dirty_regb |= 1 << (20+reg);
801 return;
ede7220f 802 }
803
d5276282 804 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
ede7220f 805 {
d5276282 806 u32 pmcv = known_regs.pmac_read[reg];
807 int mode = pmcv>>16;
808 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
809
ede7220f 810 if ((mode & 0xfff0) == 0x0800)
811 {
ede7220f 812 EOP_LDR_IMM(1,7,0x488); // rom_ptr
65c75cb0 813 emith_move_r_imm(0, (pmcv&0xfffff)<<1);
ede7220f 814 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
d5276282 815 known_regs.pmac_read[reg] += 1;
ede7220f 816 }
817 else if ((mode & 0x47ff) == 0x0018) // DRAM
818 {
819 int inc = get_inc(mode);
ede7220f 820 EOP_LDR_IMM(1,7,0x490); // dram_ptr
65c75cb0 821 emith_move_r_imm(0, (pmcv&0xffff)<<1);
ede7220f 822 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
d5276282 823 if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
ede7220f 824 {
825 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
826 tr_flush_dirty_ST();
827 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
828 EOP_TST_REG_SIMPLE(0,0);
71bb1b7b 829 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024
d5276282 830 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
ede7220f 831 EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
832 }
d5276282 833 known_regs.pmac_read[reg] += inc;
ede7220f 834 }
835 else
836 {
837 tr_unhandled();
838 }
d5276282 839 known_regs.pmc.v = known_regs.pmac_read[reg];
840 //known_regb |= KRREG_PMC;
841 dirty_regb |= KRREG_PMC;
842 dirty_regb |= 1 << (20+reg);
843 hostreg_r[0] = hostreg_r[1] = -1;
844 return;
845 }
ede7220f 846
a833e78c 847 tr_flush_dirty_pmcrs();
d5276282 848 known_regb &= ~KRREG_PMC;
849 dirty_regb &= ~KRREG_PMC;
850 known_regb &= ~(1 << (20+reg));
851 dirty_regb &= ~(1 << (20+reg));
852
853 // call the C code to handle this
854 tr_flush_dirty_ST();
d5276282 855 tr_mov16(0, reg);
989ba52a 856 emith_call_c_func(ssp_pm_read);
d5276282 857 hostreg_clear();
858}
859
860static void tr_PM0_to_r0(int op)
861{
862 tr_PMX_to_r0(0);
863}
864
865static void tr_PM1_to_r0(int op)
866{
867 tr_PMX_to_r0(1);
868}
869
870static void tr_PM2_to_r0(int op)
871{
872 tr_PMX_to_r0(2);
873}
874
875static void tr_XST_to_r0(int op)
876{
877 EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400
878 EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
879}
880
881static void tr_PM4_to_r0(int op)
882{
883 tr_PMX_to_r0(4);
884}
885
886static void tr_PMC_to_r0(int op)
887{
888 if (known_regb & KRREG_PMC)
889 {
890 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
891 known_regs.emu_status |= SSP_PMC_SET;
892 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
893 // do nothing - this is handled elsewhere
894 } else {
895 tr_mov16(0, known_regs.pmc.l);
896 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
897 }
898 }
899 else
900 {
901 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
902 tr_flush_dirty_ST();
903 if (op != 0x000e)
904 EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
905 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
906 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
907 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
908 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
909 EOP_STR_IMM(1,7,0x484);
910 hostreg_r[0] = hostreg_r[1] = -1;
ede7220f 911 }
ede7220f 912}
913
d274c33b 914
d5276282 915typedef void (tr_read_func)(int op);
d274c33b 916
d5276282 917static tr_read_func *tr_read_funcs[16] =
d274c33b 918{
919 tr_GR0_to_r0,
920 tr_X_to_r0,
921 tr_Y_to_r0,
922 tr_A_to_r0,
923 tr_ST_to_r0,
924 tr_STACK_to_r0,
925 tr_PC_to_r0,
d5276282 926 tr_P_to_r0,
927 tr_PM0_to_r0,
928 tr_PM1_to_r0,
929 tr_PM2_to_r0,
930 tr_XST_to_r0,
931 tr_PM4_to_r0,
932 (tr_read_func *)tr_unhandled,
933 tr_PMC_to_r0,
934 tr_AL_to_r0
d274c33b 935};
936
937
b9c1d012 938// write r0 to general reg handlers. Trashes r1
6e39239f 939#define TR_WRITE_R0_TO_REG(reg) \
940{ \
941 hostreg_sspreg_changed(reg); \
942 hostreg_r[0] = (reg)<<16; \
943 if (const_val != -1) { \
944 known_regs.gr[reg].h = const_val; \
945 known_regb |= 1 << (reg); \
946 } else { \
947 known_regb &= ~(1 << (reg)); \
948 } \
b9c1d012 949}
950
6e39239f 951static void tr_r0_to_GR0(int const_val)
b9c1d012 952{
953 // do nothing
954}
955
6e39239f 956static void tr_r0_to_X(int const_val)
b9c1d012 957{
958 EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
959 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
960 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
6e39239f 961 dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
962 TR_WRITE_R0_TO_REG(SSP_X);
b9c1d012 963}
964
6e39239f 965static void tr_r0_to_Y(int const_val)
b9c1d012 966{
967 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
968 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
969 EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
bad5731d 970 dirty_regb |= KRREG_P;
6e39239f 971 TR_WRITE_R0_TO_REG(SSP_Y);
b9c1d012 972}
973
6e39239f 974static void tr_r0_to_A(int const_val)
b9c1d012 975{
2385f273 976 if (tr_predict_al_need()) {
977 EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
978 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
979 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
980 }
981 else
982 EOP_MOV_REG_LSL(5, 0, 16);
6e39239f 983 TR_WRITE_R0_TO_REG(SSP_A);
b9c1d012 984}
985
6e39239f 986static void tr_r0_to_ST(int const_val)
b9c1d012 987{
988 // VR doesn't need much accuracy here..
989 EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
990 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
991 EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
6e39239f 992 TR_WRITE_R0_TO_REG(SSP_ST);
b9c1d012 993 hostreg_r[1] = -1;
5daf7021 994 known_regb &= ~KRREG_ST;
6e39239f 995 dirty_regb &= ~KRREG_ST;
b9c1d012 996}
997
6e39239f 998static void tr_r0_to_STACK(int const_val)
b9c1d012 999{
1000 // 448
1001 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
1002 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
d274c33b 1003 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
b9c1d012 1004 EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
d274c33b 1005 EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
b9c1d012 1006 hostreg_r[1] = -1;
1007}
1008
6e39239f 1009static void tr_r0_to_PC(int const_val)
b9c1d012 1010{
45883918 1011/*
1012 * do nothing - dispatcher will take care of this
b9c1d012 1013 EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
d274c33b 1014 EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
b9c1d012 1015 hostreg_r[1] = -1;
45883918 1016*/
b9c1d012 1017}
1018
d5276282 1019static void tr_r0_to_AL(int const_val)
1020{
1021 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16
1022 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
1023 EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16
1024 hostreg_sspreg_changed(SSP_AL);
1025 if (const_val != -1) {
1026 known_regs.gr[SSP_A].l = const_val;
a833e78c 1027 known_regb |= KRREG_AL;
d5276282 1028 } else
a833e78c 1029 known_regb &= ~KRREG_AL;
d5276282 1030}
1031
1032static void tr_r0_to_PMX(int reg)
1033{
d5276282 1034 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1035 {
1036 known_regs.pmac_write[reg] = known_regs.pmc.v;
1037 known_regs.emu_status &= ~SSP_PMC_SET;
1038 known_regb |= 1 << (25+reg);
1039 dirty_regb |= 1 << (25+reg);
1040 return;
1041 }
0b5e8296 1042
d5276282 1043 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1044 {
1045 int mode, addr;
1046
1047 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1048
1049 mode = known_regs.pmac_write[reg]>>16;
1050 addr = known_regs.pmac_write[reg]&0xffff;
1051 if ((mode & 0x43ff) == 0x0018) // DRAM
1052 {
1053 int inc = get_inc(mode);
1054 if (mode & 0x0400) tr_unhandled();
1055 EOP_LDR_IMM(1,7,0x490); // dram_ptr
65c75cb0 1056 emith_move_r_imm(2, addr << 1);
d5276282 1057 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1058 known_regs.pmac_write[reg] += inc;
1059 }
1060 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1061 {
1062 if (mode & 0x0400) tr_unhandled();
1063 EOP_LDR_IMM(1,7,0x490); // dram_ptr
65c75cb0 1064 emith_move_r_imm(2, addr << 1);
d5276282 1065 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1066 known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1067 }
1068 else if ((mode & 0x47ff) == 0x001c) // IRAM
1069 {
1070 int inc = get_inc(mode);
1071 EOP_LDR_IMM(1,7,0x48c); // iram_ptr
65c75cb0 1072 emith_move_r_imm(2, (addr&0x3ff) << 1);
d5276282 1073 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
e122fae6 1074 EOP_MOV_IMM(1,0,1);
1075 EOP_STR_IMM(1,7,0x494); // iram_dirty
d5276282 1076 known_regs.pmac_write[reg] += inc;
1077 }
1078 else
1079 tr_unhandled();
1080
1081 known_regs.pmc.v = known_regs.pmac_write[reg];
1082 //known_regb |= KRREG_PMC;
1083 dirty_regb |= KRREG_PMC;
1084 dirty_regb |= 1 << (25+reg);
1085 hostreg_r[1] = hostreg_r[2] = -1;
e122fae6 1086 return;
d5276282 1087 }
1088
a833e78c 1089 tr_flush_dirty_pmcrs();
d5276282 1090 known_regb &= ~KRREG_PMC;
1091 dirty_regb &= ~KRREG_PMC;
1092 known_regb &= ~(1 << (25+reg));
1093 dirty_regb &= ~(1 << (25+reg));
d5276282 1094
1095 // call the C code to handle this
1096 tr_flush_dirty_ST();
d5276282 1097 tr_mov16(1, reg);
989ba52a 1098 emith_call_c_func(ssp_pm_write);
d5276282 1099 hostreg_clear();
1100}
1101
1102static void tr_r0_to_PM0(int const_val)
1103{
1104 tr_r0_to_PMX(0);
1105}
1106
1107static void tr_r0_to_PM1(int const_val)
1108{
1109 tr_r0_to_PMX(1);
1110}
1111
1112static void tr_r0_to_PM2(int const_val)
1113{
1114 tr_r0_to_PMX(2);
1115}
1116
1117static void tr_r0_to_PM4(int const_val)
1118{
1119 tr_r0_to_PMX(4);
1120}
1121
1122static void tr_r0_to_PMC(int const_val)
1123{
1124 if ((known_regb & KRREG_PMC) && const_val != -1)
1125 {
1126 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1127 known_regs.emu_status |= SSP_PMC_SET;
1128 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1129 known_regs.pmc.h = const_val;
1130 } else {
1131 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1132 known_regs.pmc.l = const_val;
1133 }
a833e78c 1134 dirty_regb |= KRREG_PMC;
d5276282 1135 }
1136 else
1137 {
1138 tr_flush_dirty_ST();
a833e78c 1139 if (dirty_regb & KRREG_PMC) {
65c75cb0 1140 emith_move_r_imm(1, known_regs.pmc.v);
d5276282 1141 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
d5276282 1142 dirty_regb &= ~KRREG_PMC;
1143 }
a833e78c 1144 known_regb &= ~KRREG_PMC;
d5276282 1145 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
1146 EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400
1147 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1148 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC]
1149 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1150 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1151 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1152 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
1153 EOP_STR_IMM(1,7,0x484);
1154 hostreg_r[1] = hostreg_r[2] = -1;
1155 }
1156}
1157
6e39239f 1158typedef void (tr_write_func)(int const_val);
b9c1d012 1159
d5276282 1160static tr_write_func *tr_write_funcs[16] =
b9c1d012 1161{
1162 tr_r0_to_GR0,
1163 tr_r0_to_X,
1164 tr_r0_to_Y,
1165 tr_r0_to_A,
1166 tr_r0_to_ST,
1167 tr_r0_to_STACK,
1168 tr_r0_to_PC,
d5276282 1169 (tr_write_func *)tr_unhandled,
1170 tr_r0_to_PM0,
1171 tr_r0_to_PM1,
1172 tr_r0_to_PM2,
1173 (tr_write_func *)tr_unhandled,
1174 tr_r0_to_PM4,
1175 (tr_write_func *)tr_unhandled,
1176 tr_r0_to_PMC,
1177 tr_r0_to_AL
b9c1d012 1178};
1179
0e4d7ba5 1180static void tr_mac_load_XY(int op)
1181{
1182 tr_rX_read(op&3, (op>>2)&3); // X
1183 EOP_MOV_REG_LSL(4, 0, 16);
1184 tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1185 EOP_ORR_REG_SIMPLE(4, 0);
1186 dirty_regb |= KRREG_P;
1187 hostreg_sspreg_changed(SSP_X);
1188 hostreg_sspreg_changed(SSP_Y);
1189 known_regb &= ~KRREG_X;
1190 known_regb &= ~KRREG_Y;
1191}
1192
ede7220f 1193// -----------------------------------------------------
1194
ede7220f 1195static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
0e4d7ba5 1196{
ede7220f 1197 u32 pmcv, tmpv;
1198 if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1199
1200 // programming PMC:
1201 // ldi PMC, imm1
1202 // ldi PMC, imm2
1203 (*pc)++;
1204 pmcv = imm | (PROGRAM((*pc)++) << 16);
d5276282 1205 known_regs.pmc.v = pmcv;
ede7220f 1206 known_regb |= KRREG_PMC;
d5276282 1207 dirty_regb |= KRREG_PMC;
ede7220f 1208 known_regs.emu_status |= SSP_PMC_SET;
71bb1b7b 1209 n_in_ops++;
ede7220f 1210
1211 // check for possible reg programming
1212 tmpv = PROGRAM(*pc);
1213 if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1214 {
1215 int is_write = (tmpv & 0xff8f) == 0x80;
1216 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1217 if (reg > 4) tr_unhandled();
d5276282 1218 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
b8a1c09a 1219 if (is_write)
1220 known_regs.pmac_write[reg] = pmcv;
1221 else
1222 known_regs.pmac_read[reg] = pmcv;
ede7220f 1223 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
d5276282 1224 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
ede7220f 1225 known_regs.emu_status &= ~SSP_PMC_SET;
1226 (*pc)++;
71bb1b7b 1227 n_in_ops++;
ede7220f 1228 return 5;
0e4d7ba5 1229 }
1230
d5276282 1231 tr_unhandled();
ede7220f 1232 return 4;
1233}
1234
1235static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1236
1237static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1238{
1239 // ldi ST, 0
1240 // ldi PM0, 0
1241 // ldi PM0, 0
1242 // ldi ST, 60h
1243 unsigned short *pp;
1244 if (op != 0x0840 || imm != 0) return 0;
1245 pp = PROGRAM_P(*pc);
1246 if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1247
1248 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
1249 EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
1250 hostreg_sspreg_changed(SSP_ST);
1251 known_regs.gr[SSP_ST].h = 0x60;
a833e78c 1252 known_regb |= KRREG_ST;
ede7220f 1253 dirty_regb &= ~KRREG_ST;
1254 (*pc) += 3*2;
71bb1b7b 1255 n_in_ops += 3;
ede7220f 1256 return 4*2;
0e4d7ba5 1257}
5d817c91 1258
d5276282 1259static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1260{
1261 // @ 3DA2 and 426A
1262 // ld PMC, (r3|00)
1263 // ld (r3|00), PMC
1264 // ld -, AL
1265 if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1266
1267 tr_bank_read(0);
1268 EOP_MOV_REG_LSL(0, 0, 4);
1269 EOP_ORR_REG_LSR(0, 0, 0, 16);
1270 tr_bank_write(0);
1271 (*pc) += 2;
71bb1b7b 1272 n_in_ops += 2;
d5276282 1273 return 3;
1274}
1275
ede7220f 1276// -----------------------------------------------------
1277
45883918 1278static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
5d817c91 1279{
0e4d7ba5 1280 u32 tmpv, tmpv2, tmpv3;
5d817c91 1281 int ret = 0;
bad5731d 1282 known_regs.gr[SSP_PC].h = *pc;
5d817c91 1283
e807ac75 1284 switch (op >> 9)
1285 {
1286 // ld d, s
f48f5e3b 1287 case 0x00:
5d817c91 1288 if (op == 0) { ret++; break; } // nop
d274c33b 1289 tmpv = op & 0xf; // src
1290 tmpv2 = (op >> 4) & 0xf; // dst
d274c33b 1291 if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1292 tr_flush_dirty_P();
1293 EOP_MOV_REG_SIMPLE(5, 10);
d5276282 1294 hostreg_sspreg_changed(SSP_A);
bad5731d 1295 known_regb &= ~(KRREG_A|KRREG_AL);
d274c33b 1296 ret++; break;
1297 }
d5276282 1298 tr_read_funcs[tmpv](op);
6e39239f 1299 tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
45883918 1300 if (tmpv2 == SSP_PC) {
1301 ret |= 0x10000;
1302 *end_cond = -A_COND_AL;
1303 }
bad5731d 1304 ret++; break;
1305
1306 // ld d, (ri)
89fea1e9 1307 case 0x01: {
89fea1e9 1308 int r = (op&3) | ((op>>6)&4);
1309 int mod = (op>>2)&3;
1310 tmpv = (op >> 4) & 0xf; // dst
d5276282 1311 ret = tr_detect_rotate(op, pc, imm);
1312 if (ret > 0) break;
89fea1e9 1313 if (tmpv != 0)
2385f273 1314 tr_rX_read(r, mod);
1315 else {
1316 int cnt = 1;
1317 while (PROGRAM(*pc) == op) {
1318 (*pc)++; cnt++; ret++;
1319 n_in_ops++;
1320 }
1321 tr_ptrr_mod(r, mod, 1, cnt); // skip
1322 }
6e39239f 1323 tr_write_funcs[tmpv](-1);
45883918 1324 if (tmpv == SSP_PC) {
1325 ret |= 0x10000;
1326 *end_cond = -A_COND_AL;
1327 }
89fea1e9 1328 ret++; break;
1329 }
bad5731d 1330
1331 // ld (ri), s
1332 case 0x02:
1333 tmpv = (op >> 4) & 0xf; // src
d5276282 1334 tr_read_funcs[tmpv](op);
0e4d7ba5 1335 tr_rX_write(op);
d274c33b 1336 ret++; break;
f48f5e3b 1337
1338 // ld a, adr
1339 case 0x03:
5d817c91 1340 tr_bank_read(op&0x1ff);
6e39239f 1341 tr_r0_to_A(-1);
5d817c91 1342 ret++; break;
1343
b9c1d012 1344 // ldi d, imm
1345 case 0x04:
ede7220f 1346 tmpv = (op & 0xf0) >> 4; // dst
1347 ret = tr_detect_pm0_block(op, pc, imm);
1348 if (ret > 0) break;
ede7220f 1349 ret = tr_detect_set_pm(op, pc, imm);
1350 if (ret > 0) break;
0b5e8296 1351 tr_mov16(0, imm);
1352 tr_write_funcs[tmpv](imm);
45883918 1353 if (tmpv == SSP_PC) {
1354 ret |= 0x10000;
1355 *jump_pc = imm;
1356 }
0b5e8296 1357 ret += 2; break;
b9c1d012 1358
bad5731d 1359 // ld d, ((ri))
0e4d7ba5 1360 case 0x05:
bad5731d 1361 tmpv2 = (op >> 4) & 0xf; // dst
0e4d7ba5 1362 tr_rX_read2(op);
6e39239f 1363 tr_write_funcs[tmpv2](-1);
45883918 1364 if (tmpv2 == SSP_PC) {
1365 ret |= 0x10000;
1366 *end_cond = -A_COND_AL;
1367 }
0e4d7ba5 1368 ret += 3; break;
b9c1d012 1369
5d817c91 1370 // ldi (ri), imm
1371 case 0x06:
5d817c91 1372 tr_mov16(0, imm);
0e4d7ba5 1373 tr_rX_write(op);
a6fb500b 1374 ret += 2; break;
f48f5e3b 1375
1376 // ld adr, a
1377 case 0x07:
d5276282 1378 tr_A_to_r0(op);
5d817c91 1379 tr_bank_write(op&0x1ff);
1380 ret++; break;
1381
d274c33b 1382 // ld d, ri
1383 case 0x09: {
bad5731d 1384 int r;
d274c33b 1385 r = (op&3) | ((op>>6)&4); // src
bad5731d 1386 tmpv2 = (op >> 4) & 0xf; // dst
bad5731d 1387 if ((r&3) == 3) tr_unhandled();
d274c33b 1388
bad5731d 1389 if (known_regb & (1 << (r+8))) {
1390 tr_mov16(0, known_regs.r[r]);
6e39239f 1391 tr_write_funcs[tmpv2](known_regs.r[r]);
d274c33b 1392 } else {
bad5731d 1393 int reg = (r < 4) ? 8 : 9;
d274c33b 1394 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1395 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1396 hostreg_r[0] = -1;
6e39239f 1397 tr_write_funcs[tmpv2](-1);
d274c33b 1398 }
d274c33b 1399 ret++; break;
1400 }
1401
bad5731d 1402 // ld ri, s
1403 case 0x0a: {
1404 int r;
1405 r = (op&3) | ((op>>6)&4); // dst
1406 tmpv = (op >> 4) & 0xf; // src
bad5731d 1407 if ((r&3) == 3) tr_unhandled();
1408
1409 if (known_regb & (1 << tmpv)) {
1410 known_regs.r[r] = known_regs.gr[tmpv].h;
1411 known_regb |= 1 << (r + 8);
1412 dirty_regb |= 1 << (r + 8);
1413 } else {
1414 int reg = (r < 4) ? 8 : 9;
1415 int ror = ((4 - (r&3))*8) & 0x1f;
d5276282 1416 tr_read_funcs[tmpv](op);
bad5731d 1417 EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask>
1418 EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff
1419 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl
1420 hostreg_r[0] = -1;
1421 known_regb &= ~(1 << (r+8));
1422 dirty_regb &= ~(1 << (r+8));
1423 }
1424 ret++; break;
1425 }
1426
5d817c91 1427 // ldi ri, simm
67c81ee2 1428 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
5d817c91 1429 tmpv = (op>>8)&7;
bad5731d 1430 known_regs.r[tmpv] = op;
1431 known_regb |= 1 << (tmpv + 8);
5d817c91 1432 dirty_regb |= 1 << (tmpv + 8);
1433 ret++; break;
bad5731d 1434
a6fb500b 1435 // call cond, addr
6e39239f 1436 case 0x24: {
1437 u32 *jump_op = NULL;
a6fb500b 1438 tmpv = tr_cond_check(op);
6e39239f 1439 if (tmpv != A_COND_AL) {
1440 jump_op = tcache_ptr;
a80b0b42 1441 EOP_C_B(tmpv, 0, 0); // placeholder for branch
6e39239f 1442 }
1443 tr_mov16(0, *pc);
1444 tr_r0_to_STACK(*pc);
d260165a 1445 if (tmpv != A_COND_AL)
1446 EOP_C_B_PTR(jump_op, tr_neg_cond(tmpv), 0,
1447 tcache_ptr - jump_op - 2);
a6fb500b 1448 tr_mov16_cond(tmpv, 0, imm);
45883918 1449 if (tmpv != A_COND_AL)
a6fb500b 1450 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
6e39239f 1451 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ede7220f 1452 ret |= 0x10000;
45883918 1453 *end_cond = tmpv;
1454 *jump_pc = imm;
a6fb500b 1455 ret += 2; break;
6e39239f 1456 }
a6fb500b 1457
bad5731d 1458 // ld d, (a)
1459 case 0x25:
bad5731d 1460 tmpv2 = (op >> 4) & 0xf; // dst
d5276282 1461 tr_A_to_r0(op);
bad5731d 1462 EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
1463 EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
1464 EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
1465 hostreg_r[0] = hostreg_r[1] = -1;
6e39239f 1466 tr_write_funcs[tmpv2](-1);
45883918 1467 if (tmpv2 == SSP_PC) {
1468 ret |= 0x10000;
1469 *end_cond = -A_COND_AL;
1470 }
a6fb500b 1471 ret += 3; break;
bad5731d 1472
1473 // bra cond, addr
a6fb500b 1474 case 0x26:
bad5731d 1475 tmpv = tr_cond_check(op);
1476 tr_mov16_cond(tmpv, 0, imm);
45883918 1477 if (tmpv != A_COND_AL)
bad5731d 1478 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
6e39239f 1479 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ede7220f 1480 ret |= 0x10000;
45883918 1481 *end_cond = tmpv;
1482 *jump_pc = imm;
a6fb500b 1483 ret += 2; break;
bad5731d 1484
89fea1e9 1485 // mod cond, op
89fea1e9 1486 case 0x48: {
1487 // check for repeats of this op
1488 tmpv = 1; // count
1489 while (PROGRAM(*pc) == op && (op & 7) != 6) {
1490 (*pc)++; tmpv++;
71bb1b7b 1491 n_in_ops++;
89fea1e9 1492 }
6e39239f 1493 if ((op&0xf0) != 0) // !always
1494 tr_make_dirty_ST();
1495
89fea1e9 1496 tmpv2 = tr_cond_check(op);
1497 switch (op & 7) {
1498 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1499 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1500 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
6e39239f 1501 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
1502 EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
89fea1e9 1503 hostreg_r[1] = -1; break; // abs
1504 default: tr_unhandled();
1505 }
6e39239f 1506
1507 hostreg_sspreg_changed(SSP_A);
1508 dirty_regb |= KRREG_ST;
1509 known_regb &= ~KRREG_ST;
1510 known_regb &= ~(KRREG_A|KRREG_AL);
89fea1e9 1511 ret += tmpv; break;
1512 }
0e4d7ba5 1513
bad5731d 1514 // mpys?
1515 case 0x1b:
0e4d7ba5 1516 tr_flush_dirty_P();
1517 tr_mac_load_XY(op);
1518 tr_make_dirty_ST();
1519 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1520 hostreg_sspreg_changed(SSP_A);
0e4d7ba5 1521 dirty_regb |= KRREG_ST;
a833e78c 1522 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
0e4d7ba5 1523 ret++; break;
bad5731d 1524
1525 // mpya (rj), (ri), b
1526 case 0x4b:
0e4d7ba5 1527 tr_flush_dirty_P();
1528 tr_mac_load_XY(op);
1529 tr_make_dirty_ST();
1530 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1531 hostreg_sspreg_changed(SSP_A);
0e4d7ba5 1532 dirty_regb |= KRREG_ST;
a833e78c 1533 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
0e4d7ba5 1534 ret++; break;
bad5731d 1535
1536 // mld (rj), (ri), b
1537 case 0x5b:
0e4d7ba5 1538 EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1539 hostreg_sspreg_changed(SSP_A);
1540 known_regs.gr[SSP_A].v = 0;
0e4d7ba5 1541 dirty_regb |= KRREG_ST;
a833e78c 1542 known_regb &= ~KRREG_ST;
1543 known_regb |= (KRREG_A|KRREG_AL);
0e4d7ba5 1544 tr_mac_load_XY(op);
1545 ret++; break;
1546
1547 // OP a, s
1548 case 0x10:
1549 case 0x30:
1550 case 0x40:
1551 case 0x50:
1552 case 0x60:
1553 case 0x70:
1554 tmpv = op & 0xf; // src
1555 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1556 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
0e4d7ba5 1557 if (tmpv == SSP_P) {
1558 tr_flush_dirty_P();
1559 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1560 } else if (tmpv == SSP_A) {
1561 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1562 } else {
d5276282 1563 tr_read_funcs[tmpv](op);
0e4d7ba5 1564 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1565 }
1566 hostreg_sspreg_changed(SSP_A);
1567 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1568 dirty_regb |= KRREG_ST;
1569 ret++; break;
1570
1571 // OP a, (ri)
1572 case 0x11:
1573 case 0x31:
1574 case 0x41:
1575 case 0x51:
1576 case 0x61:
1577 case 0x71:
1578 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1579 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1580 tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1581 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1582 hostreg_sspreg_changed(SSP_A);
1583 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1584 dirty_regb |= KRREG_ST;
1585 ret++; break;
1586
1587 // OP a, adr
1588 case 0x13:
1589 case 0x33:
1590 case 0x43:
1591 case 0x53:
1592 case 0x63:
1593 case 0x73:
1594 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1595 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1596 tr_bank_read(op&0x1ff);
1597 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1598 hostreg_sspreg_changed(SSP_A);
1599 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1600 dirty_regb |= KRREG_ST;
1601 ret++; break;
1602
1603 // OP a, imm
1604 case 0x14:
1605 case 0x34:
1606 case 0x44:
1607 case 0x54:
1608 case 0x64:
1609 case 0x74:
1610 tmpv = (op & 0xf0) >> 4;
1611 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1612 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1613 tr_mov16(0, imm);
1614 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1615 hostreg_sspreg_changed(SSP_A);
1616 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1617 dirty_regb |= KRREG_ST;
1618 ret += 2; break;
1619
1620 // OP a, ((ri))
1621 case 0x15:
1622 case 0x35:
1623 case 0x45:
1624 case 0x55:
1625 case 0x65:
1626 case 0x75:
1627 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1628 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1629 tr_rX_read2(op);
1630 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1631 hostreg_sspreg_changed(SSP_A);
1632 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1633 dirty_regb |= KRREG_ST;
1634 ret += 3; break;
1635
1636 // OP a, ri
1637 case 0x19:
1638 case 0x39:
1639 case 0x49:
1640 case 0x59:
1641 case 0x69:
1642 case 0x79: {
1643 int r;
1644 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1645 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1646 r = (op&3) | ((op>>6)&4); // src
1647 if ((r&3) == 3) tr_unhandled();
1648
1649 if (known_regb & (1 << (r+8))) {
1650 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
1651 } else {
1652 int reg = (r < 4) ? 8 : 9;
1653 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1654 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1655 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1656 hostreg_r[0] = -1;
1657 }
1658 hostreg_sspreg_changed(SSP_A);
1659 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1660 dirty_regb |= KRREG_ST;
1661 ret++; break;
1662 }
1663
1664 // OP simm
1665 case 0x1c:
1666 case 0x3c:
1667 case 0x4c:
1668 case 0x5c:
1669 case 0x6c:
1670 case 0x7c:
1671 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1672 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1673 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
1674 hostreg_sspreg_changed(SSP_A);
1675 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1676 dirty_regb |= KRREG_ST;
bad5731d 1677 ret++; break;
e807ac75 1678 }
1679
71bb1b7b 1680 n_in_ops++;
1681
5d817c91 1682 return ret;
e807ac75 1683}
1684
45883918 1685static void emit_block_prologue(void)
1686{
1687 // check if there are enough cycles..
1688 // note: r0 must contain PC of current block
1689 EOP_CMP_IMM(11,0,0); // cmp r11, #0
65c75cb0 1690 emith_jump_cond(A_COND_LE, ssp_drc_end);
45883918 1691}
1692
1693/* cond:
1694 * >0: direct (un)conditional jump
1695 * <0: indirect jump
1696 */
3b708898 1697static void *emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
45883918 1698{
3b708898 1699 void *end_ptr = NULL;
1700
1701 if (cycles > 0xff) {
1702 elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles);
1703 cycles = 0xff;
1704 }
45883918 1705 EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles
1706
1707 if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1708 // indirect jump, or rom -> iram jump, must use dispatcher
65c75cb0 1709 emith_jump(ssp_drc_next);
45883918 1710 }
1711 else if (cond == A_COND_AL) {
679af8a3 1712 u32 *target = (pc < 0x400) ?
1713 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
1714 ssp_block_table[pc];
45883918 1715 if (target != NULL)
65c75cb0 1716 emith_jump(target);
d260165a 1717 else
1718 emith_jump(ssp_drc_next);
45883918 1719 }
1720 else {
679af8a3 1721 u32 *target1 = (pc < 0x400) ?
1722 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
1723 ssp_block_table[pc];
1724 u32 *target2 = (end_pc < 0x400) ?
1725 ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + end_pc] :
1726 ssp_block_table[end_pc];
45883918 1727 if (target1 != NULL)
65c75cb0 1728 emith_jump_cond(cond, target1);
45883918 1729 if (target2 != NULL)
65c75cb0 1730 emith_jump_cond(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
f8af9634 1731#ifndef __EPOC32__
1732 // emit patchable branches
1733 if (target1 == NULL)
65c75cb0 1734 emith_call_cond(cond, ssp_drc_next_patch);
f8af9634 1735 if (target2 == NULL)
65c75cb0 1736 emith_call_cond(tr_neg_cond(cond), ssp_drc_next_patch);
f8af9634 1737#else
1738 // won't patch indirect jumps
1739 if (target1 == NULL || target2 == NULL)
65c75cb0 1740 emith_jump(ssp_drc_next);
f8af9634 1741#endif
45883918 1742 }
3b708898 1743
1744 if (end_ptr == NULL)
1745 end_ptr = tcache_ptr;
1746
1747 return end_ptr;
45883918 1748}
1749
71bb1b7b 1750void *ssp_translate_block(int pc)
726bbb3e 1751{
e807ac75 1752 unsigned int op, op1, imm, ccount = 0;
3b708898 1753 unsigned int *block_start, *block_end;
45883918 1754 int ret, end_cond = A_COND_AL, jump_pc = -1;
5c129565 1755
2d2247c2 1756 //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
f8af9634 1757
5c129565 1758 block_start = tcache_ptr;
bad5731d 1759 known_regb = 0;
1760 dirty_regb = KRREG_P;
d5276282 1761 known_regs.emu_status = 0;
5d817c91 1762 hostreg_clear();
5c129565 1763
1764 emit_block_prologue();
726bbb3e 1765
e807ac75 1766 for (; ccount < 100;)
726bbb3e 1767 {
1768 op = PROGRAM(pc++);
1769 op1 = op >> 9;
e807ac75 1770 imm = (u32)-1;
5c129565 1771
e807ac75 1772 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1773 imm = PROGRAM(pc++); // immediate
5c129565 1774
45883918 1775 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
e807ac75 1776 if (ret <= 0)
1777 {
2d2247c2 1778 elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
1779 //exit(1);
892b1dd2 1780 }
ede7220f 1781
45883918 1782 ccount += ret & 0xffff;
1783 if (ret & 0x10000) break;
726bbb3e 1784 }
5c129565 1785
45883918 1786 if (ccount >= 100) {
1787 end_cond = A_COND_AL;
1788 jump_pc = pc;
65c75cb0 1789 emith_move_r_imm(0, pc);
45883918 1790 }
0b5e8296 1791
89fea1e9 1792 tr_flush_dirty_prs();
1793 tr_flush_dirty_ST();
ede7220f 1794 tr_flush_dirty_pmcrs();
3b708898 1795 block_end = emit_block_epilogue(ccount, end_cond, jump_pc, pc);
e01deede 1796 emith_flush();
a80b0b42 1797 emith_pool_commit(-1);
726bbb3e 1798
f4bb5d6b 1799 if (tcache_ptr - (u32 *)tcache > DRC_TCACHE_SIZE/4) {
f8af9634 1800 elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n");
726bbb3e 1801 exit(1);
1802 }
1803
1804 // stats
1805 nblocks++;
a80b0b42 1806 //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (u8 *)tcache_ptr - tcache,
1807 // (double)((u8 *)tcache_ptr - tcache) / (double)n_in_ops);
df143b36 1808
5d817c91 1809#ifdef DUMP_BLOCK
5c129565 1810 {
1811 FILE *f = fopen("tcache.bin", "wb");
1812 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1813 fclose(f);
1814 }
43e6eaad 1815 printf("dumped tcache.bin\n");
5c129565 1816 exit(0);
1817#endif
259ed0ea 1818
d4d62665 1819#ifdef __arm__
3b708898 1820 cache_flush_d_inval_i(block_start, block_end);
553c3eaa 1821#endif
259ed0ea 1822
5c129565 1823 return block_start;
726bbb3e 1824}
1825
1826
1827
1828// -----------------------------------------------------
1829
fad24893 1830static void ssp1601_state_load(void)
1831{
1832 ssp->drc.iram_dirty = 1;
1833 ssp->drc.iram_context = 0;
1834}
1835
679af8a3 1836void ssp1601_dyn_exit(void)
1837{
1838 free(ssp_block_table);
1839 free(ssp_block_table_iram);
1840 ssp_block_table = ssp_block_table_iram = NULL;
1841
1842 drc_cmn_cleanup();
1843}
1844
e807ac75 1845int ssp1601_dyn_startup(void)
726bbb3e 1846{
41397701 1847 drc_cmn_init();
1848
679af8a3 1849 ssp_block_table = calloc(sizeof(ssp_block_table[0]), SSP_BLOCKTAB_ENTS);
1850 if (ssp_block_table == NULL)
1851 return -1;
1852 ssp_block_table_iram = calloc(sizeof(ssp_block_table_iram[0]), SSP_BLOCKTAB_IRAM_ENTS);
1853 if (ssp_block_table_iram == NULL) {
1854 free(ssp_block_table);
1855 return -1;
1856 }
1857
1858 memset(tcache, 0, DRC_TCACHE_SIZE);
f4bb5d6b 1859 tcache_ptr = (void *)tcache;
726bbb3e 1860
fad24893 1861 PicoLoadStateHook = ssp1601_state_load;
1862
f5d1115f 1863 n_in_ops = 0;
d4d62665 1864#ifdef __arm__
d5276282 1865 // hle'd blocks
1ca2ea4f 1866 ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1867 ssp_block_table[0x902/2] = (void *) ssp_hle_902;
72f63cf0 1868 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x030/2] = (void *) ssp_hle_07_030;
1869 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x036/2] = (void *) ssp_hle_07_036;
1870 ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x6d6/2] = (void *) ssp_hle_07_6d6;
1871 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x12c/2] = (void *) ssp_hle_11_12c;
1872 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x384/2] = (void *) ssp_hle_11_384;
1873 ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x38a/2] = (void *) ssp_hle_11_38a;
d5276282 1874#endif
1875
726bbb3e 1876 return 0;
1877}
1878
1879
1880void ssp1601_dyn_reset(ssp1601_t *ssp)
1881{
71bb1b7b 1882 ssp1601_reset(ssp);
1883 ssp->drc.iram_dirty = 1;
1884 ssp->drc.iram_context = 0;
1885 // must do this here because ssp is not available @ startup()
1886 ssp->drc.ptr_rom = (u32) Pico.rom;
1887 ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1888 ssp->drc.ptr_dram = (u32) svp->dram;
1ca2ea4f 1889 ssp->drc.ptr_btable = (u32) ssp_block_table;
1890 ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
45883918 1891
1892 // prevent new versions of IRAM from appearing
1893 memset(svp->iram_rom, 0, 0x800);
726bbb3e 1894}
1895
f8af9634 1896
726bbb3e 1897void ssp1601_dyn_run(int cycles)
1898{
b9c1d012 1899 if (ssp->emu_status & SSP_WAIT_MASK) return;
b9c1d012 1900
fad24893 1901#ifdef DUMP_BLOCK
1902 ssp_translate_block(DUMP_BLOCK >> 1);
1903#endif
d4d62665 1904#ifdef __arm__
f3fe3e5b 1905 ssp_drc_entry(ssp, cycles);
fad24893 1906#endif
726bbb3e 1907}
1908
fast MegaDrive/MegaCD/32X emulator