32x: improved lockstep mode, allows compatibility over 50%
[picodrive.git] / pico / pico_cmn.c
CommitLineData
8b99ab90 1// common code for Pico.c and cd/Pico.c
acd35d4c 2// (c) Copyright 2007-2009 Grazvydas "notaz" Ignotas
8b99ab90 3
69996cb7 4#define CYCLES_M68K_LINE 488 // suitable for both PAL/NTSC
5#define CYCLES_M68K_VINT_LAG 68
6#define CYCLES_M68K_ASD 148
bf5fbbb4 7#define CYCLES_S68K_LINE 795
8#define CYCLES_S68K_ASD 241
69996cb7 9
10// pad delay (for 6 button pads)
11#define PAD_DELAY \
602133e1 12 if (PicoOpt&POPT_6BTN_PAD) { \
69996cb7 13 if(Pico.m.padDelay[0]++ > 25) Pico.m.padTHPhase[0]=0; \
14 if(Pico.m.padDelay[1]++ > 25) Pico.m.padTHPhase[1]=0; \
15 }
16
bf5fbbb4 17// CPUS_RUN
c987bb5c 18#ifndef CPUS_RUN
538a6098 19#define CPUS_RUN(m68k_cycles,s68k_cycles) \
c987bb5c 20 SekRunM68k(m68k_cycles)
bf5fbbb4 21#endif
22
69996cb7 23static int PicoFrameHints(void)
24{
25 struct PicoVideo *pv=&Pico.video;
9761a7d0 26 int lines, y, lines_vis = 224, line_sample, skip, vcnt_wrap;
69996cb7 27 int hint; // Hint counter
28
9761a7d0 29 pv->v_counter = Pico.m.scanline = 0;
538a6098 30
602133e1 31 if ((PicoOpt&POPT_ALT_RENDERER) && !PicoSkipFrame && (pv->reg[1]&0x40)) { // fast rend., display enabled
03e4f2a3 32 // draw a frame just after vblank in alternative render mode
33 // yes, this will cause 1 frame lag, but this is inaccurate mode anyway.
34 PicoFrameFull();
35#ifdef DRAW_FINISH_FUNC
36 DRAW_FINISH_FUNC();
37#endif
38 skip = 1;
39 }
40 else skip=PicoSkipFrame;
41
69996cb7 42 if (Pico.m.pal) {
69996cb7 43 line_sample = 68;
9761a7d0 44 if (pv->reg[1]&8) lines_vis = 240;
69996cb7 45 } else {
69996cb7 46 line_sample = 93;
47 }
48
49 SekCyclesReset();
4b9c5888 50 z80_resetCycles();
bf5fbbb4 51#ifdef PICO_CD
52 SekCyclesResetS68k();
53#endif
4b9c5888 54 PsndDacLine = 0;
7b3f44c6 55 emustatus &= ~1;
69996cb7 56
57 pv->status&=~0x88; // clear V-Int, come out of vblank
58
59 hint=pv->reg[10]; // Load H-Int counter
60 //dprintf("-hint: %i", hint);
61
62 // This is to make active scan longer (needed for Double Dragon 2, mainly)
538a6098 63 CPUS_RUN(CYCLES_M68K_ASD, CYCLES_S68K_ASD);
69996cb7 64
b6d7ac70 65 for (y = 0; y < lines_vis; y++)
69996cb7 66 {
9761a7d0 67 pv->v_counter = Pico.m.scanline = y;
68 if ((pv->reg[12]&6) == 6) { // interlace mode 2
69 pv->v_counter <<= 1;
70 pv->v_counter |= pv->v_counter >> 8;
71 pv->v_counter &= 0xff;
72 }
69996cb7 73
74 // VDP FIFO
75 pv->lwrite_cnt -= 12;
76 if (pv->lwrite_cnt <= 0) {
77 pv->lwrite_cnt=0;
78 Pico.video.status|=0x200;
79 }
80
81 PAD_DELAY
bf5fbbb4 82#ifdef PICO_CD
83 check_cd_dma();
84#endif
db1d3564 85#ifdef PICO_32X
be20816c 86 p32x_pwm_irq_check(1);
db1d3564 87#endif
69996cb7 88
89 // H-Interrupts:
90 if (--hint < 0) // y <= lines_vis: Comix Zone, Golden Axe
91 {
92 hint=pv->reg[10]; // Reload H-Int counter
93 pv->pending_ints|=0x10;
94 if (pv->reg[0]&0x10) {
95 elprintf(EL_INTS, "hint: @ %06x [%i]", SekPc, SekCycleCnt);
96 SekInterrupt(4);
97 }
98 }
99
100 // decide if we draw this line
b6d7ac70 101 if (!skip && (PicoOpt & POPT_ALT_RENDERER))
fad24893 102 {
b6d7ac70 103 // find the right moment for frame renderer, when display is no longer blanked
104 if ((pv->reg[1]&0x40) || y > 100) {
105 PicoFrameFull();
fad24893 106#ifdef DRAW_FINISH_FUNC
b6d7ac70 107 DRAW_FINISH_FUNC();
fad24893 108#endif
b6d7ac70 109 skip = 1;
fad24893 110 }
111 }
69996cb7 112
69996cb7 113 // get samples from sound chips
7b3f44c6 114 if ((y == 224 || y == line_sample) && PsndOut)
4b9c5888 115 {
be297089 116 if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
4b9c5888 117 PicoSyncZ80(SekCycleCnt);
118 if (ym2612.dacen && PsndDacLine <= y)
119 PsndDoDAC(y);
7b3f44c6 120 PsndGetSamples(y);
4b9c5888 121 }
69996cb7 122
123 // Run scanline:
124 if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
538a6098 125 CPUS_RUN(CYCLES_M68K_LINE, CYCLES_S68K_LINE);
bf5fbbb4 126
127#ifdef PICO_CD
128 update_chips();
017512f2 129#else
b0677887 130 if (PicoLineHook) PicoLineHook();
bf5fbbb4 131#endif
69996cb7 132 }
133
03e4f2a3 134 if (!skip)
b6d7ac70 135 {
136 if (DrawScanline < y)
137 PicoDrawSync(y - 1, 0);
138#ifdef DRAW_FINISH_FUNC
03e4f2a3 139 DRAW_FINISH_FUNC();
8ab3e3c1 140#endif
b6d7ac70 141 }
8ab3e3c1 142
947fb5f9 143 // V-int line (224 or 240)
144 Pico.m.scanline = y;
145 pv->v_counter = 0xe0; // bad for 240 mode
146 if ((pv->reg[12]&6) == 6) pv->v_counter = 0xc1;
147
69996cb7 148 // VDP FIFO
149 pv->lwrite_cnt=0;
150 Pico.video.status|=0x200;
151
5f9a0d16 152 memcpy(PicoPadInt, PicoPad, sizeof(PicoPadInt));
69996cb7 153 PAD_DELAY
bf5fbbb4 154#ifdef PICO_CD
155 check_cd_dma();
156#endif
db1d3564 157#ifdef PICO_32X
be20816c 158 p32x_pwm_irq_check(1);
db1d3564 159#endif
69996cb7 160
161 // Last H-Int:
162 if (--hint < 0)
163 {
164 hint=pv->reg[10]; // Reload H-Int counter
165 pv->pending_ints|=0x10;
166 //printf("rhint: %i @ %06x [%i|%i]\n", hint, SekPc, y, SekCycleCnt);
167 if (pv->reg[0]&0x10) SekInterrupt(4);
168 }
169
69996cb7 170 pv->status|=0x08; // go into vblank
171 pv->pending_ints|=0x20;
172
974fdb5b 173#ifdef PICO_32X
174 p32x_start_blank();
175#endif
176
69996cb7 177 // the following SekRun is there for several reasons:
178 // there must be a delay after vblank bit is set and irq is asserted (Mazin Saga)
179 // also delay between F bit (bit 7) is set in SR and IRQ happens (Ex-Mutants)
180 // also delay between last H-int and V-int (Golden Axe 3)
bf5fbbb4 181 SekRunM68k(CYCLES_M68K_VINT_LAG);
4b9c5888 182
69996cb7 183 if (pv->reg[1]&0x20) {
184 elprintf(EL_INTS, "vint: @ %06x [%i]", SekPc, SekCycleCnt);
185 SekInterrupt(6);
186 }
be297089 187 if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80)) {
4b9c5888 188 PicoSyncZ80(SekCycleCnt);
583ab72c 189 elprintf(EL_INTS, "zint");
69996cb7 190 z80_int();
583ab72c 191 }
69996cb7 192
69996cb7 193 // get samples from sound chips
7b3f44c6 194 if (y == 224 && PsndOut)
195 {
196 if (ym2612.dacen && PsndDacLine <= y)
197 PsndDoDAC(y);
198 PsndGetSamples(y);
199 }
69996cb7 200
201 // Run scanline:
202 if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
bf5fbbb4 203 CPUS_RUN(CYCLES_M68K_LINE - CYCLES_M68K_VINT_LAG - CYCLES_M68K_ASD,
538a6098 204 CYCLES_S68K_LINE - CYCLES_S68K_ASD);
bf5fbbb4 205
206#ifdef PICO_CD
017512f2 207 update_chips();
208#else
b0677887 209 if (PicoLineHook) PicoLineHook();
bf5fbbb4 210#endif
69996cb7 211
5e128c6d 212 lines = scanlines_total;
213 vcnt_wrap = Pico.m.pal ? 0x103 : 0xEB; // based on Gens, TODO: verify
69996cb7 214
b6d7ac70 215 for (y++; y < lines; y++)
69996cb7 216 {
9761a7d0 217 pv->v_counter = Pico.m.scanline = y;
218 if (y >= vcnt_wrap)
219 pv->v_counter -= Pico.m.pal ? 56 : 6;
220 if ((pv->reg[12]&6) == 6)
221 pv->v_counter = (pv->v_counter << 1) | 1;
222 pv->v_counter &= 0xff;
69996cb7 223
224 PAD_DELAY
bf5fbbb4 225#ifdef PICO_CD
226 check_cd_dma();
227#endif
db1d3564 228#ifdef PICO_32X
be20816c 229 p32x_pwm_irq_check(1);
db1d3564 230#endif
69996cb7 231
69996cb7 232 // Run scanline:
233 if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
538a6098 234 CPUS_RUN(CYCLES_M68K_LINE, CYCLES_S68K_LINE);
bf5fbbb4 235
236#ifdef PICO_CD
237 update_chips();
017512f2 238#else
b0677887 239 if (PicoLineHook) PicoLineHook();
bf5fbbb4 240#endif
69996cb7 241 }
242
4b9c5888 243 // sync z80
be297089 244 if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
e53704e6 245 PicoSyncZ80(Pico.m.pal ? 151809 : 127671); // cycles adjusted for converter
4b9c5888 246 if (PsndOut && ym2612.dacen && PsndDacLine <= lines-1)
247 PsndDoDAC(lines-1);
248
e53704e6 249 timers_cycle();
250
69996cb7 251 return 0;
252}
253
254#undef PAD_DELAY
bf5fbbb4 255#undef CPUS_RUN
69996cb7 256