testpico: check irq vector also
[megadrive.git] / testpico / main.c
CommitLineData
ffd4b35c 1/*
2 * This software is released into the public domain.
3 * See UNLICENSE file in top level directory.
4 */
5#include <stdlib.h>
6#include <stdarg.h>
9d39a80e 7#include "common.h"
ffd4b35c 8#include "asmtools.h"
5073ab5a 9//#pragma GCC diagnostic ignored "-Wunused-function"
ffd4b35c 10
11#define VDP_DATA_PORT 0xC00000
12#define VDP_CTRL_PORT 0xC00004
a385208c 13#define VDP_HV_COUNTER 0xC00008
ffd4b35c 14
15#define TILE_MEM_END 0xB000
16
17#define FONT_LEN 128
a385208c 18#define TILE_FONT_BASE (TILE_MEM_END - FONT_LEN * 32)
ffd4b35c 19
20/* note: using ED menu's layout here.. */
21#define WPLANE (TILE_MEM_END + 0x0000)
22#define HSCRL (TILE_MEM_END + 0x0800)
23#define SLIST (TILE_MEM_END + 0x0C00)
24#define APLANE (TILE_MEM_END + 0x1000)
25#define BPLANE (TILE_MEM_END + 0x3000)
26
ffd4b35c 27#define write16_z80le(a, d) \
28 ((volatile u8 *)(a))[0] = (u8)(d), \
29 ((volatile u8 *)(a))[1] = ((d) >> 8)
30
31static inline u16 read16_z80le(const void *a_)
32{
33 volatile const u8 *a = (volatile const u8 *)a_;
34 return a[0] | ((u16)a[1] << 8);
35}
36
37#define CTL_WRITE_VRAM(adr) \
38 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
39#define CTL_WRITE_VSRAM(adr) \
40 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
41#define CTL_WRITE_CRAM(adr) \
42 (((0xC000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
43#define CTL_READ_VRAM(adr) \
44 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
45#define CTL_READ_VSRAM(adr) \
46 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
47#define CTL_READ_CRAM(adr) \
48 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x20)
49
50#define CTL_WRITE_DMA 0x80
51
52#define VDP_setReg(r, v) \
53 write16(VDP_CTRL_PORT, 0x8000 | ((r) << 8) | ((v) & 0xff))
54
55enum {
56 VDP_MODE1 = 0x00,
57 VDP_MODE2 = 0x01,
58 VDP_NT_SCROLLA = 0x02,
59 VDP_NT_WIN = 0x03,
60 VDP_NT_SCROLLB = 0x04,
61 VDP_SAT_BASE = 0x05,
62 VDP_BACKDROP = 0x07,
63 VDP_MODE3 = 0x0b,
64 VDP_MODE4 = 0x0c,
65 VDP_HSCROLL = 0x0d,
66 VDP_AUTOINC = 0x0f,
67 VDP_SCROLLSZ = 0x10,
68 VDP_DMA_LEN0 = 0x13,
69 VDP_DMA_LEN1 = 0x14,
70 VDP_DMA_SRC0 = 0x15,
71 VDP_DMA_SRC1 = 0x16,
72 VDP_DMA_SRC2 = 0x17,
73};
74
75#define VDP_MODE1_PS 0x04
76#define VDP_MODE1_IE1 0x10 // h int
77#define VDP_MODE2_MD 0x04
78#define VDP_MODE2_PAL 0x08 // 30 col
79#define VDP_MODE2_DMA 0x10
80#define VDP_MODE2_IE0 0x20 // v int
81#define VDP_MODE2_DISP 0x40
a385208c 82#define VDP_MODE2_128K 0x80
83
84#define SR_PAL (1 << 0)
85#define SR_DMA (1 << 1)
86#define SR_HB (1 << 2)
87#define SR_VB (1 << 3)
88#define SR_ODD (1 << 4)
89#define SR_C (1 << 5)
90#define SR_SOVR (1 << 6)
91#define SR_F (1 << 7)
92#define SR_FULL (1 << 8)
93#define SR_EMPT (1 << 9)
ffd4b35c 94
95/* cell counts */
96#define LEFT_BORDER 1 /* lame TV */
97#define PLANE_W 64
98#define PLANE_H 32
99#define CSCREEN_H 28
100
101/* data.s */
102extern const u32 font_base[];
103extern const u8 z80_test[];
104extern const u8 z80_test_end[];
105
106static int text_pal;
107
108static noinline void VDP_drawTextML(const char *str, u16 plane_base,
109 u16 x, u16 y)
110{
111 const u8 *src = (const u8 *)str;
112 u16 basetile = text_pal << 13;
113 int max_len = 40 - LEFT_BORDER;
114 int len;
115 u32 addr;
116
117 x += LEFT_BORDER;
118
119 for (len = 0; str[len] && len < max_len; len++)
120 ;
121 if (len > (PLANE_W - x))
122 len = PLANE_W - x;
123
124 addr = plane_base + ((x + (PLANE_W * y)) << 1);
125 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
126
127 while (len-- > 0) {
128 write16(VDP_DATA_PORT,
129 basetile | ((*src++) - 32 + TILE_FONT_BASE / 32));
130 }
131}
132
133static int printf_ypos;
134
135static void printf_line(int x, const char *buf)
136{
137 u32 addr;
138 int i;
139
140 VDP_drawTextML(buf, APLANE, x, printf_ypos++ & (PLANE_H - 1));
141
142 if (printf_ypos >= CSCREEN_H) {
143 /* clear next line */
144 addr = APLANE;
145 addr += (PLANE_W * (printf_ypos & (PLANE_H - 1))) << 1;
146 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
147 for (i = 0; i < 40 / 2; i++)
148 write32(VDP_DATA_PORT, 0);
149
150 /* scroll plane */
151 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
152 write16(VDP_DATA_PORT, (printf_ypos - CSCREEN_H + 1) * 8);
153 }
154}
155
156#define PRINTF_LEN 40
157
158static int printf_xpos;
159
160static noinline int printf(const char *fmt, ...)
161{
162 static const char hexchars[] = "0123456789abcdef";
163 char c, buf[PRINTF_LEN + 11 + 1];
164 const char *s;
165 va_list ap;
166 int ival;
167 u32 uval;
168 int d = 0;
169 int i, j;
170
171 va_start(ap, fmt);
172 for (d = 0; *fmt; ) {
173 int prefix0 = 0;
174 int fwidth = 0;
175
176 c = *fmt++;
177 if (d < PRINTF_LEN)
178 buf[d] = c;
179
180 if (c != '%') {
181 if (c == '\n') {
182 buf[d] = 0;
183 printf_line(printf_xpos, buf);
184 d = 0;
185 printf_xpos = 0;
186 continue;
187 }
188 d++;
189 continue;
190 }
191 if (d >= PRINTF_LEN)
192 continue;
193
194 if (*fmt == '0') {
195 prefix0 = 1;
196 fmt++;
197 }
198
199 while ('1' <= *fmt && *fmt <= '9') {
200 fwidth = fwidth * 10 + *fmt - '0';
201 fmt++;
202 }
203
204 switch (*fmt++) {
205 case '%':
206 d++;
207 break;
208 case 'd':
209 case 'i':
210 ival = va_arg(ap, int);
211 if (ival < 0) {
212 buf[d++] = '-';
213 ival = -ival;
214 }
215 for (i = 1000000000; i >= 10; i /= 10)
216 if (ival >= i)
217 break;
218 for (; i >= 10; i /= 10) {
219 buf[d++] = '0' + ival / i;
220 ival %= i;
221 }
222 buf[d++] = '0' + ival;
223 break;
224 case 'x':
225 uval = va_arg(ap, int);
226 while (fwidth > 1 && uval < (1 << (fwidth - 1) * 4)) {
227 buf[d++] = prefix0 ? '0' : ' ';
228 fwidth--;
229 }
230 for (j = 1; j < 8 && uval >= (1 << j * 4); j++)
231 ;
232 for (j--; j >= 0; j--)
233 buf[d++] = hexchars[(uval >> j * 4) & 0x0f];
234 break;
5073ab5a 235 case 'c':
236 buf[d++] = va_arg(ap, int);
237 break;
ffd4b35c 238 case 's':
239 s = va_arg(ap, char *);
240 while (*s && d < PRINTF_LEN)
241 buf[d++] = *s++;
242 break;
243 default:
244 // don't handle, for now
245 d++;
246 va_arg(ap, void *);
247 break;
248 }
249 }
250 buf[d] = 0;
251 va_end(ap);
252
253 if (d != 0) {
254 // line without \n
255 VDP_drawTextML(buf, APLANE, printf_xpos,
256 printf_ypos & (PLANE_H - 1));
257 printf_xpos += d;
258 }
259
260 return d; // wrong..
261}
262
263static const char *exc_names[] = {
264 NULL,
265 NULL,
266 "Bus Error",
267 "Address Error",
268 "Illegal Instruction",
269 "Zero Divide",
270 "CHK Instruction",
271 "TRAPV Instruction",
272 "Privilege Violation", /* 8 8 */
273 "Trace",
274 "Line 1010 Emulator",
275 "Line 1111 Emulator",
276 NULL,
277 NULL,
278 NULL,
279 "Uninitialized Interrupt",
280 NULL, /* 10 16 */
281 NULL,
282 NULL,
283 NULL,
284 NULL,
285 NULL,
286 NULL,
287 NULL,
288 "Spurious Interrupt", /* 18 24 */
289 "l1 irq",
290 "l2 irq",
291 "l3 irq",
292 "l4 irq",
293 "l5 irq",
294 "l6 irq",
295 "l7 irq",
296};
297
298struct exc_frame {
299 u32 dr[8];
300 u32 ar[8];
301 u16 ecxnum; // from handler
302 union {
303 struct {
304 u16 sr;
305 u32 pc;
306 } g _packed;
307 struct {
308 u16 fc;
309 u32 addr;
310 u16 ir;
311 u16 sr;
312 u32 pc;
313 } bae _packed; // bus/address error frame
314 };
315} _packed;
316
ffd4b35c 317void exception(const struct exc_frame *f)
318{
234c4556 319 u32 *sp, sp_add;
ffd4b35c 320 int i;
321
322 while (read16(VDP_CTRL_PORT) & 2)
323 ;
324 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
325 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DISP);
326 /* adjust scroll */
327 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
328 write16(VDP_DATA_PORT,
329 printf_ypos >= CSCREEN_H ?
330 (printf_ypos - CSCREEN_H + 1) * 8 : 0);
331
332 printf("exception %i ", f->ecxnum);
333 if (f->ecxnum < ARRAY_SIZE(exc_names) && exc_names[f->ecxnum] != NULL)
334 printf("(%s)", exc_names[f->ecxnum]);
335 if (f->ecxnum < 4)
336 printf(" (%s)", (f->bae.fc & 0x10) ? "r" : "w");
337 printf(" \n");
338
339 if (f->ecxnum < 4) {
234c4556 340 printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
ffd4b35c 341 printf("addr: %08x IR: %04x FC: %02x \n",
342 f->bae.addr, f->bae.ir, f->bae.fc);
234c4556 343 sp_add = 14;
ffd4b35c 344 }
345 else {
234c4556 346 printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
347 sp_add = 6;
ffd4b35c 348 }
349 for (i = 0; i < 8; i++)
350 printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]);
234c4556 351 printf(" \n");
352 sp = (u32 *)(f->ar[7] + sp_add);
353 printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]);
354 printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]);
ffd4b35c 355}
356
357// ---
358
359static void setup_default_palette(void)
360{
361 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
362 write32(VDP_DATA_PORT, 0);
363 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(15 * 2)); // font normal
364 write16(VDP_DATA_PORT, 0xeee);
365 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(31 * 2)); // green
366 write16(VDP_DATA_PORT, 0x0e0);
367 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(47 * 2)); // red
368 write16(VDP_DATA_PORT, 0x00e);
369}
370
371static void do_setup_dma(const void *src_, u16 words)
372{
373 u32 src = (u32)src_;
374 // VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
375 VDP_setReg(VDP_DMA_LEN0, words);
376 VDP_setReg(VDP_DMA_LEN1, words >> 8);
377 VDP_setReg(VDP_DMA_SRC0, src >> 1);
378 VDP_setReg(VDP_DMA_SRC1, src >> 9);
379 VDP_setReg(VDP_DMA_SRC2, src >> 17);
380 // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA);
381}
382
a385208c 383static void vdp_wait_for_fifo_empty(void)
384{
385 while (!(read16(VDP_CTRL_PORT) & 0x200))
386 /* fifo not empty */;
387}
388
389static void vdp_wait_for_dma_idle(void)
390{
391 while (read16(VDP_CTRL_PORT) & 2)
392 /* dma busy */;
393}
394
395static void vdp_wait_for_line_0(void)
396{
397 // in PAL vcounter reports 0 twice in a frame,
398 // so wait for vblank to clear first
399 while (!(read16(VDP_CTRL_PORT) & 8))
400 /* not blanking */;
401 while (read16(VDP_CTRL_PORT) & 8)
402 /* blanking */;
403 while (read8(VDP_HV_COUNTER) != 0)
404 ;
405}
406
ffd4b35c 407static void t_dma_zero_wrap_early(void)
408{
409 const u32 *src = (const u32 *)0x3c0000;
410 u32 *ram = (u32 *)0xff0000;
411
412 do_setup_dma(src + 4, 2);
413 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
414 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
415
416 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
417 ram[0] = read32(VDP_DATA_PORT);
418 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfffc));
419 ram[1] = read32(VDP_DATA_PORT);
420}
421
422static void t_dma_zero_fill_early(void)
423{
424 u32 *ram = (u32 *)0xff0000;
425
426 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
427 write32(VDP_DATA_PORT, 0);
428 write32(VDP_DATA_PORT, 0);
429 write32(VDP_DATA_PORT, 0);
430 write32(VDP_DATA_PORT, 0);
431
432 VDP_setReg(VDP_AUTOINC, 1);
433 VDP_setReg(VDP_DMA_SRC2, 0x80);
434 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA);
435 write16(VDP_DATA_PORT, 0x1122);
436 ram[2] = read16(VDP_CTRL_PORT);
a385208c 437 vdp_wait_for_dma_idle();
ffd4b35c 438
439 VDP_setReg(VDP_AUTOINC, 2);
440 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
441 ram[3] = read32(VDP_DATA_PORT);
442}
443
5073ab5a 444#define R_SKIP 0x5a5a
445
ffd4b35c 446#define expect(ok_, v0_, v1_) \
e71680d5 447do { if ((v0_) != (v1_)) { \
ffd4b35c 448 printf("%s: %08x %08x\n", #v0_, v0_, v1_); \
449 ok_ = 0; \
e71680d5 450}} while (0)
ffd4b35c 451
5073ab5a 452#define expect_sh2(ok_, sh2_, v0_, v1_) \
453do { if ((v0_) != (v1_)) { \
454 printf("%csh2: %08x %08x\n", sh2_ ? 's' : 'm', v0_, v1_); \
455 ok_ = 0; \
456}} while (0)
457
a385208c 458#define expect_range(ok_, v0_, vmin_, vmax_) \
e71680d5 459do { if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \
a385208c 460 printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \
461 ok_ = 0; \
e71680d5 462}} while (0)
a385208c 463
464#define expect_bits(ok_, v0_, val_, mask_) \
e71680d5 465do { if (((v0_) & (mask_)) != (val_)) { \
a385208c 466 printf("%s: %04x & %04x != %04x\n", #v0_, v0_, mask_, val_); \
467 ok_ = 0; \
e71680d5 468}} while (0)
a385208c 469
ffd4b35c 470static int t_dma_zero_wrap(void)
471{
472 const u32 *src = (const u32 *)0x3c0000;
473 const u32 *ram = (const u32 *)0xff0000;
474 int ok = 1;
475
476 expect(ok, ram[0], src[5 + 0x10000/4]);
477 expect(ok, ram[1], src[4]);
478 return ok;
479}
480
481static int t_dma_zero_fill(void)
482{
483 const u32 *ram = (const u32 *)0xff0000;
484 u32 v0 = ram[2] & 2;
485 int ok = 1;
486
487 expect(ok, v0, 2);
488 expect(ok, ram[3], 0x11111111);
489 return ok;
490}
491
492static int t_dma_ram_wrap(void)
493{
494 u32 *ram = (u32 *)0xff0000;
495 u32 saved, v0, v1;
496 int ok = 1;
497
498 saved = read32(&ram[0x10000/4 - 1]);
499 ram[0x10000/4 - 1] = 0x01020304;
500 ram[0] = 0x05060708;
501 do_setup_dma(&ram[0x10000/4 - 1], 4);
502 mem_barrier();
503 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
504
505 mem_barrier();
506 write32(&ram[0x10000/4 - 1], saved);
507
508 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
509 v0 = read32(VDP_DATA_PORT);
510 v1 = read32(VDP_DATA_PORT);
511
512 expect(ok, v0, 0x01020304);
513 expect(ok, v1, 0x05060708);
514 return ok;
515}
516
517// test no src reprogram, only len0
518static int t_dma_multi(void)
519{
520 const u32 *src = (const u32 *)0x3c0000;
521 u32 v0, v1;
522 int ok = 1;
523
524 do_setup_dma(src, 2);
525 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
526 VDP_setReg(VDP_DMA_LEN0, 2);
527 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
528
529 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
530 v0 = read32(VDP_DATA_PORT);
531 v1 = read32(VDP_DATA_PORT);
532
533 expect(ok, v0, src[0]);
534 expect(ok, v1, src[1]);
535 return ok;
536}
537
538static int t_dma_cram_wrap(void)
539{
540 u32 *ram = (u32 *)0xff0000;
541 u32 v0, v1;
542 int ok = 1;
543
544 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
545 write32(VDP_DATA_PORT, 0);
546
547 ram[0] = 0x0ec20ec4;
548 ram[1] = 0x0ec60ec8;
549 mem_barrier();
550 do_setup_dma(ram, 4);
551 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0x7c | 0xff81) | CTL_WRITE_DMA);
552
553 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0x7c));
554 v0 = read32(VDP_DATA_PORT) & 0x0eee0eee;
555 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0));
556 v1 = read32(VDP_DATA_PORT) & 0x0eee0eee;
557
558 setup_default_palette();
559
560 expect(ok, v0, ram[0]);
561 expect(ok, v1, ram[1]);
562 return ok;
563}
564
565static int t_dma_vsram_wrap(void)
566{
567 u32 *ram32 = (u32 *)0xff0000;
568 u16 *ram16 = (u16 *)0xff0000;
569 u32 v0, v1;
570 int ok = 1;
571 int i;
572
573 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
574 write32(VDP_DATA_PORT, 0);
575
576 for (i = 0; i < 0x48/2; i++)
577 ram16[i] = i + 1;
578 mem_barrier();
579 do_setup_dma(ram16, 0x48/2);
580 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0x3c | 0xff81) | CTL_WRITE_DMA);
581
582 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0x3c));
583 v0 = read32(VDP_DATA_PORT) & 0x03ff03ff;
584 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
585 v1 = read32(VDP_DATA_PORT) & 0x03ff03ff;
586
587 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
588 write32(VDP_DATA_PORT, 0);
589
590 expect(ok, v0, ram32[0]);
591 expect(ok, v1, ram32[0x48/4 - 1]);
592 return ok;
593}
594
595static int t_dma_and_data(void)
596{
597 const u32 *src = (const u32 *)0x3c0000;
a385208c 598 u32 v0, v1;
ffd4b35c 599 int ok = 1;
600
601 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
602 write32(VDP_DATA_PORT, 0);
603
604 do_setup_dma(src, 2);
605 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA);
606 write32(VDP_DATA_PORT, 0x5ec8a248);
607
a385208c 608 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfc));
ffd4b35c 609 v0 = read32(VDP_DATA_PORT);
a385208c 610 v1 = read32(VDP_DATA_PORT);
ffd4b35c 611
a385208c 612 expect(ok, v0, src[0]);
613 expect(ok, v1, 0x5ec8a248);
614 return ok;
615}
616
617static int t_dma_short_cmd(void)
618{
619 const u32 *src = (const u32 *)0x3c0000;
620 u32 v0, v1, v2;
621 int ok = 1;
622
623 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4));
624 write32(VDP_DATA_PORT, 0x10111213);
625 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0));
626 write32(VDP_DATA_PORT, 0x20212223);
627 write32(VDP_DATA_PORT, 0x30313233);
cc7e5122 628 vdp_wait_for_fifo_empty();
a385208c 629
630 do_setup_dma(src, 2);
631 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0) | CTL_WRITE_DMA);
632 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4) >> 16);
633 write32(VDP_DATA_PORT, 0x40414243);
634
635 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x3ff4));
636 v0 = read32(VDP_DATA_PORT);
637 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfff0));
638 v1 = read32(VDP_DATA_PORT);
639 v2 = read32(VDP_DATA_PORT);
640
641 expect(ok, v0, 0x10111213);
642 expect(ok, v1, src[0]);
643 expect(ok, v2, 0x40414243);
ffd4b35c 644 return ok;
645}
646
647static int t_dma_fill3_odd(void)
648{
649 u32 v0, v1, v2;
650 int ok = 1;
651
652 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
653 write32(VDP_DATA_PORT, 0);
654 write32(VDP_DATA_PORT, 0);
655 write32(VDP_DATA_PORT, 0);
cc7e5122 656 vdp_wait_for_fifo_empty();
ffd4b35c 657
658 VDP_setReg(VDP_AUTOINC, 3);
659 VDP_setReg(VDP_DMA_LEN0, 3);
660 VDP_setReg(VDP_DMA_SRC2, 0x80);
661 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA);
662 write16(VDP_DATA_PORT, 0x1122);
a385208c 663 vdp_wait_for_dma_idle();
ffd4b35c 664
665 VDP_setReg(VDP_AUTOINC, 2);
666 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
667 v0 = read32(VDP_DATA_PORT);
668 v1 = read32(VDP_DATA_PORT);
669 v2 = read32(VDP_DATA_PORT);
670
671 expect(ok, v0, 0x22110000);
672 expect(ok, v1, 0x00111100);
673 expect(ok, v2, 0x00000011);
674 return ok;
675}
676
677static int t_dma_fill3_even(void)
678{
679 u32 v0, v1, v2;
680 int ok = 1;
681
682 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
683 write32(VDP_DATA_PORT, 0);
684 write32(VDP_DATA_PORT, 0);
685 write32(VDP_DATA_PORT, 0);
cc7e5122 686 vdp_wait_for_fifo_empty();
ffd4b35c 687
688 VDP_setReg(VDP_AUTOINC, 3);
689 VDP_setReg(VDP_DMA_LEN0, 3);
690 VDP_setReg(VDP_DMA_SRC2, 0x80);
691 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
692 write16(VDP_DATA_PORT, 0x1122);
a385208c 693 vdp_wait_for_dma_idle();
ffd4b35c 694
695 VDP_setReg(VDP_AUTOINC, 2);
696 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
697 v0 = read32(VDP_DATA_PORT);
698 v1 = read32(VDP_DATA_PORT);
699 v2 = read32(VDP_DATA_PORT);
700
701 expect(ok, v0, 0x11221100);
702 expect(ok, v1, 0x00000011);
703 expect(ok, v2, 0x11000000);
704 return ok;
705}
706
707static unused int t_dma_fill3_vsram(void)
708{
709 u32 v0, v1, v2;
710 int ok = 1;
711
712 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
713 write32(VDP_DATA_PORT, 0);
714 write32(VDP_DATA_PORT, 0);
715 write32(VDP_DATA_PORT, 0);
716
717 write16(VDP_DATA_PORT, 0x0111);
718 write16(VDP_DATA_PORT, 0x0222);
719 write16(VDP_DATA_PORT, 0x0333);
a385208c 720 vdp_wait_for_fifo_empty();
ffd4b35c 721
722 VDP_setReg(VDP_AUTOINC, 3);
723 VDP_setReg(VDP_DMA_LEN0, 3);
724 VDP_setReg(VDP_DMA_SRC2, 0x80);
725 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA);
726 write16(VDP_DATA_PORT, 0x0102);
a385208c 727 vdp_wait_for_dma_idle();
ffd4b35c 728
729 VDP_setReg(VDP_AUTOINC, 2);
730 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
731 v0 = read32(VDP_DATA_PORT);
732 v1 = read32(VDP_DATA_PORT);
733 v2 = read32(VDP_DATA_PORT);
734
735 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
736 write32(VDP_DATA_PORT, 0);
737
738 expect(ok, v0, 0x01020000);
739 expect(ok, v1, 0x01110111);
740 expect(ok, v2, 0x00000111);
741 return ok;
742}
743
744static int t_dma_fill_dis(void)
745{
746 u32 v0, v1;
747 int ok = 1;
748
749 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
750 write32(VDP_DATA_PORT, 0);
751 write32(VDP_DATA_PORT, 0);
752
753 VDP_setReg(VDP_DMA_LEN0, 1);
754 VDP_setReg(VDP_DMA_SRC2, 0x80);
755 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
756 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
757 write16(VDP_DATA_PORT, 0x1122);
a385208c 758 vdp_wait_for_dma_idle();
ffd4b35c 759
760 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
761 write16(VDP_DATA_PORT, 0x3344);
a385208c 762 vdp_wait_for_dma_idle();
ffd4b35c 763
764 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
765 v0 = read32(VDP_DATA_PORT);
766 v1 = read32(VDP_DATA_PORT);
767
768 expect(ok, v0, 0);
769 expect(ok, v1, 0);
770 return ok;
771}
772
773static int t_dma_fill_src(void)
774{
775 const u32 *src = (const u32 *)0x3c0000;
776 u32 v0, v1;
777 int ok = 1;
778
779 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
780 write32(VDP_DATA_PORT, 0);
781
782 // do_setup_dma(src, 2); // hang, can't write src2 twice
783 VDP_setReg(VDP_DMA_LEN0, 2);
784 VDP_setReg(VDP_DMA_SRC0, (u32)src >> 1);
785 VDP_setReg(VDP_DMA_SRC1, (u32)src >> 9);
786 VDP_setReg(VDP_DMA_SRC2, 0x80);
787 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
788 write16(VDP_DATA_PORT, 0x1122);
a385208c 789 vdp_wait_for_dma_idle();
ffd4b35c 790
791 VDP_setReg(VDP_DMA_LEN0, 2);
792 VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17);
793 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
794
795 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
796 v0 = read32(VDP_DATA_PORT);
797 v1 = read32(VDP_DATA_PORT);
798
799 expect(ok, v0, 0x11220011);
800 expect(ok, v1, src[1]);
801 return ok;
802}
803
a385208c 804// (((a & 2) >> 1) ^ 1) | ((a & $400) >> 9) | (a & $3FC) | ((a & $1F800) >> 1)
805static int t_dma_128k(void)
806{
807 u16 *ram = (u16 *)0xff0000;
808 u32 v0, v1;
809 int ok = 1;
810
811 ram[0] = 0x5a11;
812 ram[1] = 0x5a22;
813 ram[2] = 0x5a33;
814
815 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
816 write32(VDP_DATA_PORT, 0x01020304);
817 write32(VDP_DATA_PORT, 0x05060708);
818 vdp_wait_for_fifo_empty();
819
820 mem_barrier();
821 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
822 do_setup_dma(ram, 3);
823 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
824 vdp_wait_for_fifo_empty();
825
826 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
827 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
828 v0 = read32(VDP_DATA_PORT);
829 v1 = read32(VDP_DATA_PORT);
830
831 expect(ok, v0, 0x22110304);
832 expect(ok, v1, 0x05330708);
833 return ok;
834}
835
836static int t_vdp_128k_b16(void)
837{
838 u32 v0, v1;
839 int ok = 1;
840
841 VDP_setReg(VDP_AUTOINC, 0);
842 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8100));
843 write32(VDP_DATA_PORT, 0x01020304);
844 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10100));
845 write32(VDP_DATA_PORT, 0x05060708);
846 vdp_wait_for_fifo_empty();
847
848 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
849 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) >> 16); // note: upper cmd
850 write32(VDP_DATA_PORT, 0x11223344);
851 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10102));
852 write32(VDP_DATA_PORT, 0x55667788);
853 vdp_wait_for_fifo_empty();
854
855 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
856 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8100));
857 v0 = read16(VDP_DATA_PORT);
858 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
859 v1 = read16(VDP_DATA_PORT);
860
861 VDP_setReg(VDP_AUTOINC, 2);
862
863 expect(ok, v0, 0x8844);
864 expect(ok, v1, 0x0708);
865 return ok;
866}
867
868static unused int t_vdp_128k_b16_inc(void)
869{
870 u32 v0, v1;
871 int ok = 1;
872
873 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
874 write32(VDP_DATA_PORT, 0x01020304);
875 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
876 write32(VDP_DATA_PORT, 0x05060708);
877 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfffe));
878 write32(VDP_DATA_PORT, 0x090a0b0c);
879 vdp_wait_for_fifo_empty();
880
881 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
882 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) >> 16); // note: upper cmd
883 write16(VDP_DATA_PORT, 0x1122);
884 vdp_wait_for_fifo_empty();
885
886 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
887 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
888 v0 = read32(VDP_DATA_PORT);
889 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8000));
890 v1 = read32(VDP_DATA_PORT);
891 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
892 write32(VDP_DATA_PORT, 0);
893 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
894 write32(VDP_DATA_PORT, 0);
895
896 expect(ok, v0, 0x0b0c0304); // XXX: no 22 anywhere?
897 expect(ok, v1, 0x05060708);
898 return ok;
899}
900
901static int t_vdp_reg_cmd(void)
902{
903 u32 v0;
904 int ok = 1;
905
906 VDP_setReg(VDP_AUTOINC, 0);
907 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
908 write32(VDP_DATA_PORT, 0x01020304);
909 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
910 write32(VDP_DATA_PORT, 0x05060708);
911
912 VDP_setReg(VDP_AUTOINC, 2);
913 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
914 v0 = read16(VDP_DATA_PORT);
915
916 expect(ok, v0, 0x0304);
917 return ok;
918}
919
cc7e5122 920static int t_vdp_sr_vb(void)
921{
922 u16 sr[4];
923 int ok = 1;
924
925 while (read8(VDP_HV_COUNTER) != 242)
926 ;
927 sr[0] = read16(VDP_CTRL_PORT);
928 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
929 sr[1] = read16(VDP_CTRL_PORT);
930 while (read8(VDP_HV_COUNTER) != 4)
931 ;
932 sr[2] = read16(VDP_CTRL_PORT);
933 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
934 sr[3] = read16(VDP_CTRL_PORT);
935
936 expect_bits(ok, sr[0], SR_VB, SR_VB);
937 expect_bits(ok, sr[1], SR_VB, SR_VB);
938 expect_bits(ok, sr[2], SR_VB, SR_VB);
939 expect_bits(ok, sr[3], 0, SR_VB);
940 return ok;
941}
942
ffd4b35c 943/* z80 tests assume busreq state */
944static int t_z80mem_long_mirror(void)
945{
946 u8 *zram = (u8 *)0xa00000;
947 int ok = 1;
948
949 write8(&zram[0x1100], 0x11);
950 write8(&zram[0x1101], 0x22);
951 write8(&zram[0x1102], 0x33);
952 write8(&zram[0x1103], 0x44);
953 mem_barrier();
954 write32(&zram[0x3100], 0x55667788);
955 mem_barrier();
956
957 expect(ok, zram[0x1100], 0x55);
958 expect(ok, zram[0x1101], 0x22);
959 expect(ok, zram[0x1102], 0x77);
960 expect(ok, zram[0x1103], 0x44);
961 return ok;
962}
963
a385208c 964static int t_z80mem_noreq_w(void)
965{
966 u8 *zram = (u8 *)0xa00000;
967 int ok = 1;
968
969 write8(&zram[0x1100], 0x11);
970 mem_barrier();
971 write16(0xa11100, 0x000);
972 write8(&zram[0x1100], 0x22);
973 mem_barrier();
974
975 write16(0xa11100, 0x100);
976 while (read16(0xa11100) & 0x100)
977 ;
978
979 expect(ok, zram[0x1100], 0x11);
980 return ok;
981}
982
e71680d5 983#define Z80_C_DISPATCH 113 // see z80_test.s80
984#define Z80_C_END 17
985#define Z80_C_END_VCNT 67
986
987#define Z80_CYLES_TEST1(b) (Z80_C_DISPATCH + ((b) - 1) * 21 + 26 + Z80_C_END)
a385208c 988
ffd4b35c 989static int t_z80mem_vdp_r(void)
990{
991 u8 *zram = (u8 *)0xa00000;
992 int ok = 1;
993
994 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
995 write32(VDP_DATA_PORT, 0x11223344);
996 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
997
998 zram[0x1000] = 1; // cp
ffd4b35c 999 write16_z80le(&zram[0x1002], 0x7f00); // src
a385208c 1000 write16_z80le(&zram[0x1004], 0x1100); // dst
1001 write16_z80le(&zram[0x1006], 2); // len
1002 zram[0x1100] = zram[0x1101] = zram[0x1102] = 0x5a;
ffd4b35c 1003 mem_barrier();
1004 write16(0xa11100, 0x000);
e71680d5 1005 burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10);
ffd4b35c 1006
1007 write16(0xa11100, 0x100);
1008 while (read16(0xa11100) & 0x100)
1009 ;
1010
1011 expect(ok, zram[0x1000], 0);
a385208c 1012 expect(ok, zram[0x1100], 0x11);
1013 expect(ok, zram[0x1101], 0x44);
1014 expect(ok, zram[0x1102], 0x5a);
ffd4b35c 1015 return ok;
1016}
1017
1018static unused int t_z80mem_vdp_w(void)
1019{
1020 u8 *zram = (u8 *)0xa00000;
1021 u32 v0;
1022 int ok = 1;
1023
1024 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1025 write32(VDP_DATA_PORT, 0x11223344);
1026 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
a385208c 1027 vdp_wait_for_fifo_empty();
ffd4b35c 1028
1029 zram[0x1000] = 1; // cp
a385208c 1030 write16_z80le(&zram[0x1002], 0x1100); // src
ffd4b35c 1031 write16_z80le(&zram[0x1004], 0x7f00); // dst
a385208c 1032 write16_z80le(&zram[0x1006], 2); // len
1033 zram[0x1100] = 0x55;
1034 zram[0x1101] = 0x66;
ffd4b35c 1035 mem_barrier();
1036 write16(0xa11100, 0x000);
e71680d5 1037 burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10);
ffd4b35c 1038
1039 write16(0xa11100, 0x100);
1040 while (read16(0xa11100) & 0x100)
1041 ;
1042
1043 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
1044 v0 = read32(VDP_DATA_PORT);
1045
1046 expect(ok, zram[0x1000], 0);
1047 expect(ok, v0, 0x55556666);
1048 return ok;
1049}
1050
a385208c 1051static int t_tim_loop(void)
1052{
1053 u8 vcnt;
1054 int ok = 1;
1055
1056 vdp_wait_for_line_0();
1057 burn10(488*220/10);
1058 vcnt = read8(VDP_HV_COUNTER);
1059 mem_barrier();
1060
1061 //expect_range(ok, vcnt, 0x80, 0x80);
1062 expect(ok, vcnt, 223);
1063 return ok;
1064}
1065
e71680d5 1066static int t_tim_z80_loop(void)
1067{
1068 u8 pal = read8(0xa10001) & 0x40;
1069 u8 *zram = (u8 *)0xa00000;
1070 u16 z80_loops = pal ? 3420*(313*2+1)/15/100 : 3420*(262*2+1)/15/100; // 2fr + 1ln
1071 u16 _68k_loops = pal ? 3420*(313*2+1)/7/10 : 3420*(262*2+1)/7/10;
1072 int ok = 1;
1073
1074 zram[0x1000] = 3; // idle loop, save vcnt
1075 write16_z80le(&zram[0x1002], 0); // src (unused)
1076 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1077 write16_z80le(&zram[0x1006], z80_loops); // x100 cycles
1078 zram[0x1100] = 0;
1079 mem_barrier();
1080
1081 vdp_wait_for_line_0();
1082 write16(0xa11100, 0x000);
1083 burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
1084
1085 write16(0xa11100, 0x100);
1086 while (read16(0xa11100) & 0x100)
1087 ;
1088 expect(ok, zram[0x1000], 0);
1089 expect(ok, zram[0x1100], 1);
1090 return ok;
1091}
1092
1093#define Z80_CYCLES_TEST2(b) (Z80_C_DISPATCH + (b) * 38 + Z80_C_END_VCNT)
a385208c 1094
1095// 80 80 91 95-96
1096static void z80_read_loop(u8 *zram, u16 src)
1097{
1098 const int pairs = 512 + 256;
1099
1100 zram[0x1000] = 2; // read loop, save vcnt
1101 write16_z80le(&zram[0x1002], src); // src
1102 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1103 write16_z80le(&zram[0x1006], pairs); // reads/2
1104 zram[0x1100] = 0;
1105 mem_barrier();
1106
1107 vdp_wait_for_line_0();
1108 write16(0xa11100, 0x000);
e71680d5 1109 burn10(Z80_CYCLES_TEST2(pairs) * 15 / 7 * 2 / 10);
a385208c 1110
1111 write16(0xa11100, 0x100);
1112 while (read16(0xa11100) & 0x100)
1113 ;
1114}
1115
1116static int t_tim_z80_ram(void)
1117{
1118 u8 *zram = (u8 *)0xa00000;
1119 int ok = 1;
1120
1121 z80_read_loop(zram, 0);
1122
1123 expect(ok, zram[0x1000], 0);
1124 expect_range(ok, zram[0x1100], 0x80, 0x80);
1125 return ok;
1126}
1127
1128static int t_tim_z80_ym(void)
1129{
1130 u8 *zram = (u8 *)0xa00000;
1131 int ok = 1;
1132
1133 z80_read_loop(zram, 0x4000);
1134
1135 expect(ok, zram[0x1000], 0);
1136 expect_range(ok, zram[0x1100], 0x80, 0x80);
1137 return ok;
1138}
1139
1140static int t_tim_z80_vdp(void)
1141{
1142 u8 *zram = (u8 *)0xa00000;
1143 int ok = 1;
1144
1145 z80_read_loop(zram, 0x7f08);
1146
1147 expect(ok, zram[0x1000], 0);
a385208c 1148 expect_range(ok, zram[0x1100], 0x91, 0x91);
a385208c 1149 return ok;
1150}
1151
1152static int t_tim_z80_bank_rom(void)
1153{
1154 u8 *zram = (u8 *)0xa00000;
1155 int i, ok = 1;
1156
1157 for (i = 0; i < 17; i++)
1158 write8(0xa06000, 0); // bank 0
1159
1160 z80_read_loop(zram, 0x8000);
1161
1162 expect(ok, zram[0x1000], 0);
a385208c 1163 expect_range(ok, zram[0x1100], 0x95, 0x96);
a385208c 1164 return ok;
1165}
1166
1167/* borderline too slow */
1168#if 0
cc7e5122 1169static void test_vcnt_vb(void)
a385208c 1170{
1171 const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter
1172 u32 *ram = (u32 *)0xff0000;
1173 u16 vcnt, vcnt_expect = 0;
1174 u16 sr, count = 0;
1175 u32 val, old;
1176
1177 vdp_wait_for_line_0();
1178 old = read32(srhv);
1179 *ram++ = old;
1180 for (;;) {
1181 val = read32(srhv);
1182 vcnt = val & 0xff00;
1183 if (vcnt == vcnt_expect)
1184 continue;
1185 sr = val >> 16;
1186 if (vcnt == 0 && !(sr & SR_VB)) // not VB
1187 break; // wrapped to start of frame
1188// count++;
1189 vcnt_expect += 0x100;
1190 if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) {
1191 old = val;
1192 continue;
1193 }
1194 // should have a vcnt jump here
1195 *ram++ = old;
1196 *ram++ = val;
1197 vcnt_expect = vcnt;
1198 old = val;
1199 }
1200 *ram++ = val;
1201 *ram = count;
1202 mem_barrier();
1203}
1204#endif
1205
1206static int t_tim_vcnt(void)
1207{
1208 const u32 *ram32 = (u32 *)0xff0000;
1209 const u8 *ram = (u8 *)0xff0000;
1210 u8 pal = read8(0xa10001) & 0x40;
1211 u8 vc_jmp_b = pal ? 0x02 : 0xea;
1212 u8 vc_jmp_a = pal ? 0xca : 0xe5;
1213 u16 lines = pal ? 313 : 262;
1214 int ok = 1;
1215
cc7e5122 1216 test_vcnt_vb();
a385208c 1217 expect(ok, ram[0*4+2], 0); // line 0
1218 expect_bits(ok, ram[0*4+1], 0, SR_VB);
1219 expect(ok, ram[1*4+2], 223); // last no blank
1220 expect_bits(ok, ram[1*4+1], 0, SR_VB);
1221 expect(ok, ram[2*4+2], 224); // 1st blank
1222 expect_bits(ok, ram[2*4+1], SR_VB, SR_VB);
1223 expect(ok, ram[3*4+2], vc_jmp_b); // before jump
1224 expect_bits(ok, ram[3*4+1], SR_VB, SR_VB);
1225 expect(ok, ram[4*4+2], vc_jmp_a); // after jump
1226 expect_bits(ok, ram[4*4+1], SR_VB, SR_VB);
1227 expect(ok, ram[5*4+2], 0xfe); // before vb clear
1228 expect_bits(ok, ram[5*4+1], SR_VB, SR_VB);
1229 expect(ok, ram[6*4+2], 0xff); // after vb clear
1230 expect_bits(ok, ram[6*4+1], 0, SR_VB);
1231 expect(ok, ram[7*4+2], 0); // next line 0
1232 expect_bits(ok, ram[7*4+1], 0, SR_VB);
1233 expect(ok, ram32[8], lines - 1);
1234 return ok;
1235}
1236
e71680d5 1237static int t_tim_vcnt_loops(void)
1238{
1239 const u16 *ram16 = (u16 *)0xfff004;
1240 u8 pal = read8(0xa10001) & 0x40;
1241 u16 i, lines = pal ? 313 : 262;
1242 int ok = 1;
1243
1244 test_vcnt_loops();
1245 expect(ok, ram16[-1*2+0], 0xff);
1246 expect_range(ok, ram16[-1*2+1], 21, 22);
1247 for (i = 0; i < lines; i++)
1248 expect_range(ok, ram16[i*2+1], 19, 21);
1249 expect(ok, ram16[lines*2+0], 0);
635f2450 1250 expect_range(ok, ram16[lines*2+1], 19, 21);
e71680d5 1251 return ok;
1252}
1253
cc7e5122 1254static int t_tim_hblank_h40(void)
1255{
1256 const u8 *r = (u8 *)0xff0000;
1257 int ok = 1;
1258
1259 test_hb();
1260
1261 // set: 0-2
1262 expect_bits(ok, r[2], SR_HB, SR_HB);
1263 expect_bits(ok, r[5], SR_HB, SR_HB);
1264 // <wait>
1265 expect_bits(ok, r[7], SR_HB, SR_HB);
1266 // clear: 8-11
1267 expect_bits(ok, r[12], 0, SR_HB);
1268 return ok;
1269}
1270
1271static int t_tim_hblank_h32(void)
1272{
1273 const u8 *r = (u8 *)0xff0000;
1274 int ok = 1;
1275
1276 VDP_setReg(VDP_MODE4, 0x00);
1277 test_hb();
1278 VDP_setReg(VDP_MODE4, 0x81);
1279
cc7e5122 1280 expect_bits(ok, r[0], 0, SR_HB);
cc7e5122 1281 // set: 1-4
1282 expect_bits(ok, r[4], SR_HB, SR_HB);
1283 expect_bits(ok, r[5], SR_HB, SR_HB);
1284 // <wait>
1285 expect_bits(ok, r[8], SR_HB, SR_HB);
1286 // clear: 9-11
1287 expect_bits(ok, r[12], 0, SR_HB);
1288 return ok;
1289}
1290
a385208c 1291static int t_tim_vdp_as_vram_w(void)
1292{
1293 int ok = 1;
1294 u8 vcnt;
1295
1296 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1297 vdp_wait_for_line_0();
1298 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1299 vcnt = read8(VDP_HV_COUNTER);
1300 mem_barrier();
1301
1302 expect(ok, vcnt, 112*2-1);
1303 return ok;
1304}
1305
1306static int t_tim_vdp_as_cram_w(void)
1307{
1308 int ok = 1;
1309 u8 vcnt;
1310
1311 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
1312 vdp_wait_for_line_0();
1313 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1314 vcnt = read8(VDP_HV_COUNTER);
1315 mem_barrier();
1316
1317 setup_default_palette();
1318
a385208c 1319 expect(ok, vcnt, 112);
a385208c 1320 return ok;
1321}
1322
e71680d5 1323static const u8 hcnt2tm[] =
1324{
1325 0x0a, 0x1d, 0x31, 0x44, 0x58, 0x6b, 0x7f, 0x92,
1326 0xa6, 0xb9, 0xcc, 0x00, 0x00, 0x00, 0xe2, 0xf6
1327};
1328
1329static int t_tim_ym_timer_z80(int is_b)
1330{
1331 u8 pal = read8(0xa10001) & 0x40;
1332 u8 *zram = (u8 *)0xa00000;
1333 u8 *z80 = zram;
1334 u16 _68k_loops = 3420*(302+5+1)/7/10; // ~ (72*1024*2)/(3420./7)
1335 u16 start, end, diff;
1336 int ok = 1;
1337
1338 zram[0x1000] = 4 + is_b; // ym2612 timer a/b test
1339 zram[0x1100] = zram[0x1101] = zram[0x1102] = zram[0x1103] = 0;
1340 mem_barrier();
1341
1342 vdp_wait_for_line_0();
1343 write16(0xa11100, 0x000);
1344
1345 burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
1346
1347 write16(0xa11100, 0x100);
1348 while (read16(0xa11100) & 0x100)
1349 ;
1350 mem_barrier();
1351 expect(ok, zram[0x1000], 0);
1352 (void)hcnt2tm;
1353 //start = ((u16)zram[0x1102] << 8) | hcnt2tm[zram[0x1103] >> 4];
1354 //end = ((u16)zram[0x1100] << 8) | hcnt2tm[zram[0x1101] >> 4];
1355 start = zram[0x1102];
1356 end = zram[0x1100];
1357 diff = end - start;
1358 if (pal)
1359 expect_range(ok, diff, 0xf4, 0xf6);
1360 else
1361 expect_range(ok, diff, 0x27, 0x29);
1362 write8(&z80[0x4001], 0); // stop, but should keep the flag
1363 mem_barrier();
1364 burn10(32*6/10); // busy bit, 32 FM ticks (M/7/6)
1365 if (is_b) {
1366 expect(ok, z80[0x4000], 2);
1367 write8(&z80[0x4001], 0x20); // reset flag (reg 0x27, set up by z80)
1368 }
1369 else {
1370 expect(ok, z80[0x4000], 1);
1371 write8(&z80[0x4001], 0x10);
1372 }
1373 mem_barrier();
1374 burn10(32*6/10);
1375 expect(ok, z80[0x4000], 0);
1376 return ok;
1377}
1378
1379static int t_tim_ym_timera_z80(void)
1380{
1381 return t_tim_ym_timer_z80(0);
1382}
1383
1384static int t_tim_ym_timerb_z80(void)
1385{
1386 return t_tim_ym_timer_z80(1);
1387}
1388
1389static int t_tim_ym_timerb_stop(void)
1390{
1391 const struct {
1392 //u8 vcnt_start;
1393 //u8 hcnt_start;
1394 u16 vcnt_start;
1395 u16 stat0;
1396 //u8 vcnt_end;
1397 //u8 hcnt_end;
1398 u16 vcnt_end;
1399 u16 stat1;
1400 } *t = (void *)0xfff000;
1401 u8 *z80 = (u8 *)0xa00000;
1402 u16 diff;
1403 int ok = 1;
1404 write16(0xa11100, 0x100);
1405 while (read16(0xa11100) & 0x100)
1406 ;
1407 test_ym_stopped_tick();
1408 mem_barrier();
1409 //start = ((u16)t->vcnt_start << 8) | hcnt2tm[t->hcnt_start >> 4];
1410 //end = ((u16)t->vcnt_end << 8) | hcnt2tm[t->hcnt_end >> 4];
1411 //diff = end - start;
1412 diff = t->vcnt_end - t->vcnt_start;
1413 //expect_range(ok, diff, 0x492, 0x5c2); // why so much variation?
1414 expect_range(ok, diff, 4, 5);
1415 expect(ok, t->stat0, 0);
1416 expect(ok, t->stat1, 2);
1417 expect(ok, z80[0x4000], 2);
1418 write8(&z80[0x4001], 0x30);
1419 return ok;
1420}
1421
1422static int t_tim_ym_timer_ab_sync(void)
1423{
3d80f940 1424 u16 v1, v2, v3, v4, v5, ln0, ln1, ln2;
e71680d5 1425 int ok = 1;
3d80f940 1426
1427 vdp_wait_for_line_0();
635f2450 1428 v1 = test_ym_ab_sync();
3d80f940 1429
1430 ln0 = get_line();
1431 burn10(3420*15/7/10); // ~15 scanlines
1432 write8(0xa04001, 0x3f); // clear, no reload
1433 burn10(12); // wait for busy to clear
635f2450 1434 v2 = read8(0xa04000);
1435 v3 = test_ym_ab_sync2();
3d80f940 1436
1437 ln1 = get_line();
1438 burn10(3420*15/7/10); // ~15 scanlines
1439 v4 = test_ym_ab_sync2();
1440
1441 ln2 = get_line();
1442 burn10(3420*30/7/10); // ~35 scanlines
1443 v5 = read8(0xa04000);
1444
635f2450 1445 expect(ok, v1, 3);
1446 expect(ok, v2, 0);
1447 expect(ok, v3, 3);
3d80f940 1448 expect(ok, v4, 2);
1449 expect(ok, v5, 0);
1450 expect_range(ok, ln1-ln0, 18, 19);
1451 expect_range(ok, ln2-ln1, 32, 34); // almost always 33
e71680d5 1452 return ok;
1453}
1454
4f936a9c 1455struct irq_test {
1456 u16 cnt;
1457 union {
1458 u16 hv;
1459 u8 v;
1460 } first, last;
8517a6df 1461 u16 pad;
4f936a9c 1462};
1463
e71680d5 1464// broken on fresh boot due to uknown reasons
6c839579 1465static int t_irq_hint(void)
1466{
4f936a9c 1467 struct irq_test *it = (void *)0xfff000;
e71680d5 1468 struct irq_test *itv = it + 1;
6c839579 1469 int ok = 1;
1470
e71680d5 1471 memset_(it, 0, sizeof(*it) * 2);
1472 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1473 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1474
1475 // without this, tests fail after cold boot
1476 while (!(read16(VDP_CTRL_PORT) & 8))
1477 /* not blanking */;
1478
6c839579 1479 // for more fun, disable the display
1480 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
1481
6c839579 1482 VDP_setReg(10, 0);
1483 while (read8(VDP_HV_COUNTER) != 100)
1484 ;
1485 while (read8(VDP_HV_COUNTER) != 229)
1486 ;
1487 // take the pending irq
1488 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1489 move_sr(0x2000);
1490 burn10(488 * 2 / 10);
1491 move_sr(0x2700);
4f936a9c 1492 expect(ok, it->first.v, 229); // pending irq trigger
1493 expect(ok, it->cnt, 1);
e71680d5 1494 expect(ok, itv->cnt, 0);
4f936a9c 1495
6c839579 1496 // count irqs
4f936a9c 1497 it->cnt = it->first.hv = it->last.hv = 0;
6c839579 1498 move_sr(0x2000);
cc7e5122 1499 while (read8(VDP_HV_COUNTER) != 4)
6c839579 1500 ;
1501 while (read8(VDP_HV_COUNTER) != 228)
1502 ;
1503 move_sr(0x2700);
4f936a9c 1504 expect(ok, it->cnt, 225);
1505 expect(ok, it->first.v, 0);
1506 expect(ok, it->last.v, 224);
1507
6c839579 1508 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1509
4f936a9c 1510 // detect reload line
1511 it->cnt = it->first.hv = it->last.hv = 0;
1512 VDP_setReg(10, 17);
1513 move_sr(0x2000);
1514 while (read16(VDP_CTRL_PORT) & 8)
1515 /* blanking */;
1516 VDP_setReg(10, 255);
1517 while (read8(VDP_HV_COUNTER) != 228)
1518 ;
1519 move_sr(0x2700);
1520 expect(ok, it->cnt, 1);
1521 expect(ok, it->first.v, 17);
1522 expect(ok, it->last.v, 17);
1523
1524 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1525
6c839579 1526 return ok;
1527}
1528
8517a6df 1529static int t_irq_both_cpu_unmask(void)
1530{
1531 struct irq_test *ith = (void *)0xfff000;
1532 struct irq_test *itv = ith + 1;
1533 u16 s0, s1;
1534 int ok = 1;
1535
1536 memset_(ith, 0, sizeof(*ith) * 2);
1537 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1538 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1539 VDP_setReg(10, 0);
1540 while (read8(VDP_HV_COUNTER) != 100)
1541 ;
1542 while (read8(VDP_HV_COUNTER) != 226)
1543 ;
1544 VDP_setReg(10, 99);
1545 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1546 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1547 /* go to active display line 100 */
1548 while (read8(VDP_HV_COUNTER) != 100)
1549 ;
1550 s0 = read16(VDP_CTRL_PORT);
1551 s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1552 move_sr(0x2700);
1553 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1554 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1555
1556 expect(ok, itv->cnt, 1); // vint count
1557 expect(ok, itv->first.v, 100); // vint line
1558 expect(ok, ith->cnt, 1); // hint count
1559 expect(ok, ith->first.v, 100); // hint line
1560 expect_bits(ok, s0, SR_F, SR_F);
1561 expect_bits(ok, s1, 0, SR_F);
1562 return ok;
1563}
1564
6c839579 1565static int t_irq_ack_v_h(void)
1566{
8517a6df 1567 struct irq_test *ith = (void *)0xfff000;
1568 struct irq_test *itv = ith + 1;
6c839579 1569 u16 s0, s1, s2;
1570 int ok = 1;
1571
8517a6df 1572 memset_(ith, 0, sizeof(*ith) * 2);
6c839579 1573 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1574 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1575 VDP_setReg(10, 0);
4f936a9c 1576 /* ensure hcnt reload */
1577 while (!(read16(VDP_CTRL_PORT) & 8))
1578 /* not blanking */;
1579 while (read16(VDP_CTRL_PORT) & 8)
1580 /* blanking */;
6c839579 1581 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1582 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
1583 while (read8(VDP_HV_COUNTER) != 100)
1584 ;
1585 while (read8(VDP_HV_COUNTER) != 226)
1586 ;
1587 s0 = read16(VDP_CTRL_PORT);
1588 s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT);
1589 burn10(666 / 10);
1590 s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1591 burn10(488 / 10);
1592 move_sr(0x2700);
1593 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1594 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1595
8517a6df 1596 expect(ok, itv->cnt, 1); // vint count
1597 expect(ok, itv->first.v, 226); // vint line
1598 expect(ok, ith->cnt, 1); // hint count
1599 expect(ok, ith->first.v, 228); // hint line
6c839579 1600 expect_bits(ok, s0, SR_F, SR_F);
1601 expect_bits(ok, s1, 0, SR_F);
1602 expect_bits(ok, s2, 0, SR_F);
1603 return ok;
1604}
1605
cc7e5122 1606static int t_irq_ack_v_h_2(void)
1607{
8517a6df 1608 struct irq_test *ith = (void *)0xfff000;
1609 struct irq_test *itv = ith + 1;
cc7e5122 1610 u16 s0, s1;
1611 int ok = 1;
1612
8517a6df 1613 memset_(ith, 0, sizeof(*ith) * 2);
cc7e5122 1614 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1615 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1616 VDP_setReg(10, 0);
1617 while (read8(VDP_HV_COUNTER) != 100)
1618 ;
1619 while (read8(VDP_HV_COUNTER) != 226)
1620 ;
1621 s0 = read16(VDP_CTRL_PORT);
1622 test_v_h_2();
1623 s1 = read16(VDP_CTRL_PORT);
1624 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1625 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1626
8517a6df 1627 expect(ok, itv->cnt, 2); // vint count
1628 expect(ok, itv->first.v, 226); // vint line
1629 expect(ok, ith->cnt, 1); // hint count
1630 expect(ok, ith->first.v, 227); // hint line
cc7e5122 1631 expect_bits(ok, s0, SR_F, SR_F);
1632 expect_bits(ok, s1, 0, SR_F);
1633 return ok;
1634}
1635
6c839579 1636static int t_irq_ack_h_v(void)
1637{
1638 u16 *ram = (u16 *)0xfff000;
1639 u8 *ram8 = (u8 *)0xfff000;
1640 u16 s0, s1, s[4];
1641 int ok = 1;
1642
1643 ram[0] = ram[1] = ram[2] =
1644 ram[4] = ram[5] = ram[6] = 0;
1645 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1646 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1647 VDP_setReg(10, 0);
1648 while (read8(VDP_HV_COUNTER) != 100)
1649 ;
1650 while (read8(VDP_HV_COUNTER) != 226)
1651 ;
1652 s0 = read16(VDP_CTRL_PORT);
1653 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1654 move_sr(0x2000);
1655 burn10(666 / 10);
1656 s1 = read16(VDP_CTRL_PORT);
1657 write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8)
1658 | VDP_MODE2_MD | VDP_MODE2_IE0, s);
6c839579 1659 move_sr(0x2700);
1660 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1661 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1662
1663 expect(ok, ram[0], 1); // hint count
1664 expect(ok, ram8[2], 226); // hint line
1665 expect(ok, ram[4], 1); // vint count
1666 expect(ok, ram8[10], 228); // vint line
1667 expect_bits(ok, s0, SR_F, SR_F);
1668 expect_bits(ok, s1, SR_F, SR_F);
1669 expect_bits(ok, s[0], SR_F, SR_F);
1670 expect_bits(ok, s[1], SR_F, SR_F);
1671 expect_bits(ok, s[2], 0, SR_F);
1672 expect_bits(ok, s[3], 0, SR_F);
1673 return ok;
1674}
1675
cc7e5122 1676static int t_irq_ack_h_v_2(void)
1677{
1678 u16 *ram = (u16 *)0xfff000;
1679 u8 *ram8 = (u8 *)0xfff000;
1680 u16 s0, s1;
1681 int ok = 1;
1682
1683 ram[0] = ram[1] = ram[2] =
1684 ram[4] = ram[5] = ram[6] = 0;
1685 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1686 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1687 VDP_setReg(10, 0);
1688 while (read8(VDP_HV_COUNTER) != 100)
1689 ;
1690 while (read8(VDP_HV_COUNTER) != 226)
1691 ;
1692 s0 = read16(VDP_CTRL_PORT);
1693 test_h_v_2();
1694 s1 = read16(VDP_CTRL_PORT);
1695 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1696 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1697
1698 expect(ok, ram[0], 2); // hint count
1699 expect(ok, ram8[2], 226); // hint first line
1700 expect(ok, ram8[4], 226); // hint last line
1701 expect(ok, ram[4], 0); // vint count
1702 expect(ok, ram8[10], 0); // vint line
1703 expect_bits(ok, s0, SR_F, SR_F);
1704 expect_bits(ok, s1, 0, SR_F);
1705 return ok;
1706}
1707
1708static void t_irq_f_flag(void)
1709{
1710 memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint);
1711 memset_((void *)0xff0000, 0, 10);
1712 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1713 test_f();
1714 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1715}
1716
1717static int t_irq_f_flag_h40(void)
1718{
1719 u8 f, *r = (u8 *)0xff0000;
1720 int ok = 1;
1721
1722 t_irq_f_flag();
1723
1724 expect_bits(ok, r[0], 0, SR_F);
1725 expect_bits(ok, r[1], 0, SR_F);
1726 expect_bits(ok, r[2], 0, SR_F);
1727 // hits 1-3 times in range 3-9, usually ~5
1728 f = r[3] | r[4] | r[5] | r[6] | r[7];
1729
1730 expect_bits(ok, r[10], 0, SR_F);
1731 expect_bits(ok, r[11], 0, SR_F);
1732 expect_bits(ok, f, SR_F, SR_F);
1733 return ok;
1734}
1735
1736static int t_irq_f_flag_h32(void)
1737{
1738 u8 f, *r = (u8 *)0xff0000;
1739 int ok = 1;
1740
1741 VDP_setReg(VDP_MODE4, 0x00);
1742 t_irq_f_flag();
1743 VDP_setReg(VDP_MODE4, 0x81);
1744
1745 expect_bits(ok, r[0], 0, SR_F);
1746 expect_bits(ok, r[1], 0, SR_F);
1747 // hits 1-3 times in range 2-7, usually 3
1748 f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7];
1749
1750 expect_bits(ok, r[8], 0, SR_F);
1751 expect_bits(ok, r[9], 0, SR_F);
1752 expect_bits(ok, r[10], 0, SR_F);
1753 expect_bits(ok, r[11], 0, SR_F);
1754 expect_bits(ok, f, SR_F, SR_F);
1755 return ok;
1756}
1757
9d39a80e 1758// 32X
1759
5073ab5a 1760#define IRQ_CNT_FB_BASE 0x1ff00
1761
6474d733 1762// see do_cmd()
5073ab5a 1763static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
1764{
1765 u16 v, *r = (u16 *)0xa15120;
6474d733 1766 u8 *r8 = (u8 *)r;
5073ab5a 1767 u16 cmd_s = cmd | (is_slave << 15);
1768 int i;
1769
1770 write32(&r[4/2], a0);
1771 write32(&r[8/2], a1);
1772 mem_barrier();
1773 write16(r, cmd_s);
1774 mem_barrier();
1775 for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
1776 burn10(1);
1777 if (v != 0) {
1778 printf("cmd clr: %x\n", v);
1779 mem_barrier();
6474d733 1780 printf("exc m s: %02x %02x\n", r8[0x0e], r8[0x0f]);
5073ab5a 1781 write16(r, 0);
1782 }
1783 v = read16(&r[1]);
1784 if (v != 0) {
1785 printf("cmd err: %x\n", v);
1786 write16(&r[1], 0);
1787 }
1788}
1789
1790static int t_32x_reset_btn(void)
1791{
1792 void (*do_32x_disable)(void) = (void *)0xff0040;
1793 u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
1794 u16 *m_icnt = (u16 *)fbl_icnt;
1795 u16 *s_icnt = m_icnt + 8;
1796 u32 *r32 = (u32 *)0xa15100;
1797 u16 *r16 = (u16 *)r32, i, s;
1798 u8 *r8 = (u8 *)r32;
1799 u32 *rl = (u32 *)0;
1800 int ok = 1;
1801
1802 if (!(read16(r16) & 1))
1803 return R_SKIP;
1804
1805 expect(ok, r16[0x00/2], 0x8083);
1806
1807 write8(r8, 0x00); // FM=0
1808 mem_barrier();
1809 expect(ok, r16[0x00/2], 0x83);
1810 expect(ok, r16[0x02/2], 0);
1811 expect(ok, r16[0x04/2], 3);
1812 expect(ok, r16[0x06/2], 1); // RV (set in sega_gcc.s reset handler)
1813 expect(ok, r32[0x08/4], 0x5a5a08);
1814 expect(ok, r32[0x0c/4], 0x5a5a0c);
1815 expect(ok, r16[0x10/2], 0x5a10);
1816 expect(ok, r32[0x14/4], 0);
1817 expect(ok, r32[0x18/4], 0);
1818 expect(ok, r32[0x1c/4], 0);
1819 expect(ok, r32[0x20/4], 0x00005a20);
1820 expect(ok, r32[0x24/4], 0x5a5a5a24);
1821 expect(ok, r32[0x28/4], 0x5a5a5a28);
6474d733 1822 expect(ok, r32[0x2c/4], 0x07075a2c); // 7 - last_irq_vec
5073ab5a 1823 if (!(r16[0x00/2] & 0x8000)) {
1824 expect(ok, r8 [0x81], 0);
1825 expect(ok, r16[0x82/2], 0);
1826 expect(ok, r16[0x84/2], 0);
1827 expect(ok, r16[0x86/2], 0);
1828 //expect(ok, r16[0x88/2], 0); // triggers fill?
1829 expect(ok, r8 [0x8b] & ~2, 0); // FEN toggles periodically?
1830 expect(ok, r16[0x8c/2], 0);
1831 expect(ok, r16[0x8e/2], 0);
1832 }
1833 r32[0x20/4] = r32[0x24/4] = r32[0x28/4] = r32[0x2c/4] = 0;
1834 for (s = 0; s < 2; s++)
1835 {
1836 x32_cmd(CMD_READ32, 0x20004000, 0, s); // not cleared by hw
1837 expect_sh2(ok, s, r32[0x24/4], 0x02020000); // ADEN | cmd
1838 // t_32x_sh_defaults will test the other bits
1839 }
1840 // setup for t_32x_sh_defaults
1841 x32_cmd(CMD_WRITE8, 0x20004001, 0, 0);
1842 x32_cmd(CMD_WRITE8, 0x20004001, 0, 1);
1843
1844 for (i = 0; i < 7; i++) {
1845 expect(ok, m_icnt[i], 0x100);
1846 expect(ok, s_icnt[i], 0x100);
1847 }
1848 expect(ok, m_icnt[7], 0x101); // VRES happened
1849 expect(ok, s_icnt[7], 0x101);
1850
1851 memcpy_(do_32x_disable, x32x_disable,
1852 x32x_disable_end - x32x_disable);
1853 do_32x_disable();
1854
1855 expect(ok, r16[0x00/2], 0x82);
1856 expect(ok, r16[0x02/2], 0);
1857 expect(ok, r16[0x04/2], 3);
1858 expect(ok, r16[0x06/2], 1); // RV
1859 expect(ok, r32[0x08/4], 0x5a5a08);
1860 expect(ok, r32[0x0c/4], 0x5a5a0c);
1861 expect(ok, r16[0x10/2], 0x5a10);
1862 expect(ok, rl[0x04/4], 0x000800);
1863
1864 // setup for t_32x_init, t_32x_sh_defaults
1865 r16[0x04/2] = 0;
1866 r16[0x06/2] = 0; // can just set without ADEN
1867 r16[0x10/2] = 0x1234; // warm reset indicator
1868 mem_barrier();
1869 expect(ok, r16[0x06/2], 0); // RV
1870 return ok;
1871}
1872
9d39a80e 1873static int t_32x_init(void)
1874{
1875 void (*do_32x_enable)(void) = (void *)0xff0040;
1876 u32 M_OK = MKLONG('M','_','O','K');
1877 u32 S_OK = MKLONG('S','_','O','K');
5073ab5a 1878 u32 *r32 = (u32 *)0xa15100;
1879 u16 *r16 = (u16 *)r32;
1880 u8 *r8 = (u8 *)r32;
71b41fdd 1881 int i, ok = 1;
9d39a80e 1882
71b41fdd 1883 //v1070 = read32(0x1070);
1884
1885 /* what does REN mean exactly?
1886 * Seems to be sometimes clear after reset */
1887 for (i = 0; i < 1000000; i++)
1888 if (read16(r16) & 0x80)
1889 break;
9d39a80e 1890 expect(ok, r16[0x00/2], 0x82);
1891 expect(ok, r16[0x02/2], 0);
1892 expect(ok, r16[0x04/2], 0);
1893 expect(ok, r16[0x06/2], 0);
5073ab5a 1894 expect(ok, r8 [0x08], 0);
1895 //expect(ok, r32[0x08/4], 0); // garbage 24bit
1896 expect(ok, r8 [0x0c], 0);
1897 //expect(ok, r32[0x0c/4], 0); // garbage 24bit
1898 if (r16[0x10/2] != 0x1234) // warm reset
1899 expect(ok, r16[0x10/2], 0xffff);
1900 expect(ok, r16[0x12/2], 0);
1901 expect(ok, r32[0x14/4], 0);
1902 expect(ok, r32[0x18/4], 0);
1903 expect(ok, r32[0x1c/4], 0);
1904 //expect(ok, r8 [0x81], 0); // VDP; hangs without ADEN
1905 r32[0x20/4] = 0; // master resp
1906 r32[0x24/4] = 0; // slave resp
1907 r32[0x28/4] = 0;
1908 r32[0x2c/4] = 0;
1909
1910 // these have garbage or old values (survive MD's power cycle)
1911 r32[0x08/4] = 0;
1912 r32[0x0c/4] = 0;
9d39a80e 1913
1914 // could just set RV, but BIOS reads ROM, so can't
1915 memcpy_(do_32x_enable, x32x_enable,
1916 x32x_enable_end - x32x_enable);
1917 do_32x_enable();
1918
1919 expect(ok, r16[0x00/2], 0x83);
1920 expect(ok, r16[0x02/2], 0);
1921 expect(ok, r16[0x04/2], 0);
1922 expect(ok, r16[0x06/2], 1); // RV
5073ab5a 1923 expect(ok, r32[0x14/4], 0);
1924 expect(ok, r32[0x18/4], 0);
1925 expect(ok, r32[0x1c/4], 0);
1926 expect(ok, r32[0x20/4], M_OK);
9d39a80e 1927 while (!read16(&r16[0x24/2]))
1928 ;
5073ab5a 1929 expect(ok, r32[0x24/4], S_OK);
1930 write32(&r32[0x20/4], 0);
1931 if (!(r16[0x00/2] & 0x8000)) {
1932 expect(ok, r8 [0x81], 0);
1933 expect(ok, r16[0x82/2], 0);
1934 expect(ok, r16[0x84/2], 0);
1935 expect(ok, r16[0x86/2], 0);
1936 //expect(ok, r16[0x88/2], 0); // triggers fill?
1937 expect(ok, r8 [0x8b] & ~2, 0);
1938 expect(ok, r16[0x8c/2], 0);
1939 expect(ok, r16[0x8e/2], 0);
06d7984c 1940 }
5073ab5a 1941 return ok;
9d39a80e 1942}
1943
1944static int t_32x_echo(void)
1945{
6474d733 1946 u16 *r16 = (u16 *)0xa15100;
9d39a80e 1947 int ok = 1;
1948
6474d733 1949 r16[0x2c/2] = r16[0x2e/2] = 0;
06d7984c 1950 x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
6474d733 1951 expect_sh2(ok, 0, r16[0x26/2], 0x1234);
06d7984c 1952 x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
6474d733 1953 expect_sh2(ok, 1, r16[0x26/2], 0xa345);
1954 expect(ok, r16[0x2c/2], 0); // no last_irq_vec
1955 expect(ok, r16[0x2e/2], 0); // no exception_index
5073ab5a 1956 return ok;
1957}
1958
1959static int t_32x_sh_defaults(void)
1960{
1961 u32 *r32 = (u32 *)0xa15120;
1962 int ok = 1, s;
1963
1964 for (s = 0; s < 2; s++)
1965 {
1966 x32_cmd(CMD_READ32, 0x20004000, 0, s);
1967 expect_sh2(ok, s, r32[0x04/4], 0x02000000); // ADEN
1968 x32_cmd(CMD_READ32, 0x20004004, 0, s);
1969 expect_sh2(ok, s, r32[0x04/4], 0x00004001); // Empty Rv
1970 x32_cmd(CMD_READ32, 0x20004008, 0, s);
1971 expect_sh2(ok, s, r32[0x04/4], 0);
1972 x32_cmd(CMD_READ32, 0x2000400c, 0, s);
1973 expect_sh2(ok, s, r32[0x04/4], 0);
1974 x32_cmd(CMD_GETGBR, 0, 0, s);
1975 expect_sh2(ok, s, r32[0x04/4], 0x20004000);
1976 }
06d7984c 1977 return ok;
1978}
1979
1980static int t_32x_md_bios(void)
1981{
1982 void (*do_call_c0)(int a, int d) = (void *)0xff0040;
1983 u8 *rmb = (u8 *)0xff0000;
1984 u32 *rl = (u32 *)0;
1985 int ok = 1;
1986
1987 memcpy_(do_call_c0, test_32x_b_c0,
1988 test_32x_b_c0_end - test_32x_b_c0);
1989 write8(rmb, 0);
1990 do_call_c0(0xff0000, 0x5a);
1991
1992 expect(ok, rmb[0], 0x5a);
1993 expect(ok, rl[0x04/4], 0x880200);
234c4556 1994 expect(ok, rl[0x10/4], 0x880212);
1995 expect(ok, rl[0x94/4], 0x8802d8);
9d39a80e 1996 return ok;
1997}
1998
1999static int t_32x_md_rom(void)
2000{
2001 u32 *rl = (u32 *)0;
2002 int ok = 1;
2003
2004 expect(ok, rl[0x004/4], 0x880200);
2005 expect(ok, rl[0x100/4], 0x53454741);
2006 expect(ok, rl[0x70/4], 0);
71b41fdd 2007 write32(&rl[0x70/4], 0xa5123456);
9d39a80e 2008 write32(&rl[0x78/4], ~0);
2009 mem_barrier();
9d39a80e 2010 expect(ok, rl[0x78/4], 0x8802ae);
71b41fdd 2011 expect(ok, rl[0x70/4], 0xa5123456);
2012 //expect(ok, rl[0x1070/4], v1070);
2013 write32(&rl[0x70/4], 0);
2014 // with RV 0x880000/0x900000 hangs, can't test
9d39a80e 2015 return ok;
2016}
2017
06d7984c 2018static int t_32x_md_fb(void)
2019{
2020 u8 *fbb = (u8 *)0x840000;
2021 u16 *fbw = (u16 *)fbb;
2022 u32 *fbl = (u32 *)fbb;
2023 u8 *fob = (u8 *)0x860000;
2024 u16 *fow = (u16 *)fob;
2025 u32 *fol = (u32 *)fob;
2026 int ok = 1;
2027
2028 fbl[0] = 0x12345678;
2029 fol[1] = 0x89abcdef;
2030 mem_barrier();
2031 expect(ok, fbw[1], 0x5678);
2032 expect(ok, fow[2], 0x89ab);
2033 fbb[0] = 0;
2034 fob[1] = 0;
2035 fbw[1] = 0;
2036 fow[2] = 0;
2037 fow[3] = 1;
2038 mem_barrier();
2039 fow[3] = 0x200;
2040 mem_barrier();
2041 expect(ok, fol[0], 0x12340000);
2042 expect(ok, fbl[1], 0x89ab0201);
2043 return ok;
2044}
2045
2046static int t_32x_sh_fb(void)
2047{
2048 u32 *fbl = (u32 *)0x840000;
5073ab5a 2049 u8 *r8 = (u8 *)0xa15100;
06d7984c 2050 int ok = 1;
2051
5073ab5a 2052 if (read8(r8) & 0x80)
2053 write8(r8, 0x00); // FM=0
06d7984c 2054 fbl[0] = 0x12345678;
2055 fbl[1] = 0x89abcdef;
2056 mem_barrier();
5073ab5a 2057 write8(r8, 0x80); // FM=1
2058 x32_cmd(CMD_WRITE8, 0x24000000, 0, 0); // should ignore
2059 x32_cmd(CMD_WRITE8, 0x24020001, 0, 0); // ignore
2060 x32_cmd(CMD_WRITE16, 0x24000002, 0, 0); // ok
2061 x32_cmd(CMD_WRITE16, 0x24020000, 0, 0); // ignore
06d7984c 2062 x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
5073ab5a 2063 write8(r8, 0x00); // FM=0
06d7984c 2064 mem_barrier();
2065 expect(ok, fbl[0], 0x12340000);
2066 expect(ok, fbl[1], 0x5aabcda5);
2067 return ok;
2068}
2069
5073ab5a 2070static int t_32x_irq(void)
234c4556 2071{
5073ab5a 2072 u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
2073 u16 *m_icnt = (u16 *)fbl_icnt;
2074 u16 *s_icnt = m_icnt + 8;
234c4556 2075 u32 *r = (u32 *)0xa15100;
2076 u16 *r16 = (u16 *)r;
6474d733 2077 u8 *r8 = (u8 *)r;
5073ab5a 2078 int ok = 1, i;
234c4556 2079
5073ab5a 2080 write8(r, 0x00); // FM=0
6474d733 2081 r[0x2c/4] = 0;
5073ab5a 2082 mem_barrier();
2083 for (i = 0; i < 8; i++)
2084 write32(&fbl_icnt[i], 0);
2085 mem_barrier();
2086 write16(&r16[0x02/2], 0xfffd); // INTM+unused_bits
2087 mem_barrier();
2088 expect(ok, r16[0x02/2], 1);
2089 x32_cmd(CMD_WRITE8, 0x20004001, 2, 0); // unmask cmd
2090 x32_cmd(CMD_WRITE8, 0x20004001, 2, 1); // unmask cmd slave
2091 burn10(10);
2092 write8(r, 0x00); // FM=0 (hangs without)
2093 mem_barrier();
2094 expect(ok, r16[0x02/2], 0);
6474d733 2095 expect(ok, r8 [0x2c], 4);
2096 expect(ok, r8 [0x2d], 0);
2097 expect(ok, r16[0x2e/2], 0); // no exception_index
5073ab5a 2098 expect(ok, m_icnt[4], 1);
2099 expect(ok, s_icnt[4], 0);
2100 write16(&r16[0x02/2], 0xaaaa); // INTS+unused_bits
2101 mem_barrier();
2102 expect(ok, r16[0x02/2], 2);
2103 burn10(10);
2104 mem_barrier();
2105 expect(ok, r16[0x02/2], 0);
6474d733 2106 expect(ok, r8 [0x2c], 4);
2107 expect(ok, r8 [0x2d], 4);
2108 expect(ok, r16[0x2e/2], 0); // no exception_index
5073ab5a 2109 write8(r, 0x00); // FM=0
2110 mem_barrier();
2111 expect(ok, m_icnt[4], 1);
2112 expect(ok, s_icnt[4], 1);
2113 for (i = 0; i < 8; i++) {
2114 if (i == 4)
2115 continue;
2116 expect(ok, m_icnt[i], 0);
2117 expect(ok, s_icnt[i], 0);
2118 }
2119 return ok;
2120}
234c4556 2121
5073ab5a 2122static int t_32x_reg_w(void)
2123{
2124 u32 *r32 = (u32 *)0xa15100;
2125 u16 *r16 = (u16 *)r32, old;
2126 int ok = 1;
234c4556 2127
5073ab5a 2128 r32[0x08/4] = ~0;
2129 r32[0x0c/4] = ~0;
2130 r16[0x10/2] = ~0;
2131 mem_barrier();
2132 expect(ok, r32[0x08/4], 0xfffffe);
2133 expect(ok, r32[0x0c/4], 0xffffff);
2134 expect(ok, r16[0x10/2], 0xfffc);
2135 mem_barrier();
2136 r32[0x08/4] = r32[0x0c/4] = 0;
2137 r16[0x10/2] = 0;
2138 old = r16[0x06/2];
2139 x32_cmd(CMD_WRITE16, 0x20004006, ~old, 0);
2140 expect(ok, r16[0x06/2], old);
2141 return ok;
2142}
234c4556 2143
5073ab5a 2144// prepare for reset btn press tests
2145static int t_32x_reset_prep(void)
2146{
2147 u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
2148 u32 *r32 = (u32 *)0xa15100;
2149 u16 *r16 = (u16 *)r32;
2150 u8 *r8 = (u8 *)r32;
2151 int ok = 1, i;
2152
2153 expect(ok, r16[0x00/2], 0x83);
2154 write8(r8, 0x00); // FM=0
6474d733 2155 r32[0x2c/4] = 0;
234c4556 2156 mem_barrier();
5073ab5a 2157 expect(ok, r8[0x8b] & ~2, 0);
2158 for (i = 0; i < 8; i++)
2159 write32(&fbl_icnt[i], 0x01000100);
2160 x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 0); // unmask cmd
2161 x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 1); // unmask slave
2162 burn10(10);
2163 write8(r8, 0x00); // FM=0
6474d733 2164 expect(ok, r32[0x2c/4], 0);
5073ab5a 2165 mem_barrier();
2166 for (i = 0; i < 8; i++)
2167 expect(ok, fbl_icnt[i], 0x01000100);
2168
2169 r16[0x04/2] = 0xffff;
2170 r32[0x08/4] = 0x5a5a5a08;
2171 r32[0x0c/4] = 0x5a5a5a0c;
2172 r16[0x10/2] = 0x5a10;
2173 r32[0x20/4] = 0x00005a20; // no x32_cmd
2174 r32[0x24/4] = 0x5a5a5a24;
2175 r32[0x28/4] = 0x5a5a5a28;
2176 r32[0x2c/4] = 0x5a5a5a2c;
234c4556 2177 return ok;
2178}
2179
9d39a80e 2180enum {
2181 T_MD = 0,
2182 T_32 = 1, // 32X
2183};
2184
ffd4b35c 2185static const struct {
9d39a80e 2186 u8 type;
ffd4b35c 2187 int (*test)(void);
2188 const char *name;
2189} g_tests[] = {
5073ab5a 2190 // this must be first to disable the 32x and restore the 68k vector table
2191 { T_32, t_32x_reset_btn, "32x resetbtn" },
2192
9d39a80e 2193 { T_MD, t_dma_zero_wrap, "dma zero len + wrap" },
2194 { T_MD, t_dma_zero_fill, "dma zero len + fill" },
2195 { T_MD, t_dma_ram_wrap, "dma ram wrap" },
2196 { T_MD, t_dma_multi, "dma multi" },
2197 { T_MD, t_dma_cram_wrap, "dma cram wrap" },
2198 { T_MD, t_dma_vsram_wrap, "dma vsram wrap" },
2199 { T_MD, t_dma_and_data, "dma and data" },
2200 { T_MD, t_dma_short_cmd, "dma short cmd" },
2201 { T_MD, t_dma_fill3_odd, "dma fill3 odd" },
2202 { T_MD, t_dma_fill3_even, "dma fill3 even" },
9d39a80e 2203 { T_MD, t_dma_fill3_vsram, "dma fill3 vsram" },
9d39a80e 2204 { T_MD, t_dma_fill_dis, "dma fill disabled" },
2205 { T_MD, t_dma_fill_src, "dma fill src incr" },
2206 { T_MD, t_dma_128k, "dma 128k mode" },
2207 { T_MD, t_vdp_128k_b16, "vdp 128k addr bit16" },
a385208c 2208 // { t_vdp_128k_b16_inc, "vdp 128k bit16 inc" }, // mystery
9d39a80e 2209 { T_MD, t_vdp_reg_cmd, "vdp reg w cmd reset" },
2210 { T_MD, t_vdp_sr_vb, "vdp status reg vb" },
2211 { T_MD, t_z80mem_long_mirror, "z80 ram long mirror" },
2212 { T_MD, t_z80mem_noreq_w, "z80 ram noreq write" },
2213 { T_MD, t_z80mem_vdp_r, "z80 vdp read" },
ffd4b35c 2214 // { t_z80mem_vdp_w, "z80 vdp write" }, // hang
9d39a80e 2215 { T_MD, t_tim_loop, "time loop" },
e71680d5 2216 { T_MD, t_tim_z80_loop, "time z80 loop" },
9d39a80e 2217 { T_MD, t_tim_z80_ram, "time z80 ram" },
2218 { T_MD, t_tim_z80_ym, "time z80 ym2612" },
2219 { T_MD, t_tim_z80_vdp, "time z80 vdp" },
2220 { T_MD, t_tim_z80_bank_rom, "time z80 bank rom" },
2221 { T_MD, t_tim_vcnt, "time V counter" },
e71680d5 2222 { T_MD, t_tim_vcnt_loops, "time vcnt loops" },
9d39a80e 2223 { T_MD, t_tim_hblank_h40, "time hblank h40" },
2224 { T_MD, t_tim_hblank_h32, "time hblank h32" },
2225 { T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" },
2226 { T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" },
e71680d5 2227 { T_MD, t_tim_ym_timera_z80, "time timer a z80" },
2228 { T_MD, t_tim_ym_timerb_z80, "time timer b z80" },
2229 { T_MD, t_tim_ym_timerb_stop, "timer b stop" },
2230 { T_MD, t_tim_ym_timer_ab_sync,"timer ab sync" },
9d39a80e 2231 { T_MD, t_irq_hint, "irq4 / line" },
8517a6df 2232 { T_MD, t_irq_both_cpu_unmask, "irq both umask" },
9d39a80e 2233 { T_MD, t_irq_ack_v_h, "irq ack v-h" },
2234 { T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" },
2235 { T_MD, t_irq_ack_h_v, "irq ack h-v" },
2236 { T_MD, t_irq_ack_h_v_2, "irq ack h-v 2" },
2237 { T_MD, t_irq_f_flag_h40, "irq f flag h40" },
9d39a80e 2238 { T_MD, t_irq_f_flag_h32, "irq f flag h32" },
2239
06d7984c 2240 // the first one enables 32X, so must be kept
2241 // all tests assume RV=1 FM=0
9d39a80e 2242 { T_32, t_32x_init, "32x init" },
2243 { T_32, t_32x_echo, "32x echo" },
5073ab5a 2244 { T_32, t_32x_sh_defaults, "32x sh def" },
06d7984c 2245 { T_32, t_32x_md_bios, "32x md bios" },
2246 { T_32, t_32x_md_rom, "32x md rom" },
2247 { T_32, t_32x_md_fb, "32x md fb" },
2248 { T_32, t_32x_sh_fb, "32x sh fb" },
5073ab5a 2249 { T_32, t_32x_irq, "32x irq" },
2250 { T_32, t_32x_reg_w, "32x reg w" },
2251 { T_32, t_32x_reset_prep, "32x rstprep" }, // must be last 32x
ffd4b35c 2252};
2253
2254static void setup_z80(void)
2255{
2256 u8 *zram = (u8 *)0xa00000;
2257 int i, len;
2258
2259 /* z80 */
2260 write16(0xa11100, 0x100);
2261 write16(0xa11200, 0x100);
2262
2263 while (read16(0xa11100) & 0x100)
2264 ;
2265
2266 // load the default test program, clear it's data
2267 len = z80_test_end - z80_test;
2268 for (i = 0; i < len; i++)
2269 write8(&zram[i], z80_test[i]);
2270 for (i = 0x1000; i < 0x1007; i++)
2271 write8(&zram[i], 0);
a385208c 2272
2273 // reset
2274 write16(0xa11200, 0x000);
2275 write16(0xa11100, 0x000);
2276 burn10(1);
2277 write16(0xa11200, 0x100);
e71680d5 2278
2279 burn10(50 * 15 / 7 / 10); // see z80_test.s80
a385208c 2280
2281 // take back the bus
2282 write16(0xa11100, 0x100);
2283 while (read16(0xa11100) & 0x100)
2284 ;
2285}
2286
2287static void wait_next_vsync(void)
2288{
e71680d5 2289 while (read16(VDP_CTRL_PORT) & SR_VB)
a385208c 2290 /* blanking */;
e71680d5 2291 while (!(read16(VDP_CTRL_PORT) & SR_VB))
a385208c 2292 /* not blanking */;
2293}
2294
cc7e5122 2295static unused int hexinc(char *c)
a385208c 2296{
2297 (*c)++;
2298 if (*c > 'f') {
2299 *c = '0';
2300 return 1;
2301 }
2302 if (*c == '9' + 1)
2303 *c = 'a';
2304 return 0;
ffd4b35c 2305}
2306
2307int main()
2308{
5073ab5a 2309 void (*px32x_switch_rv)(short rv);
2310 short (*pget_input)(void) = get_input;
ffd4b35c 2311 int passed = 0;
9d39a80e 2312 int skipped = 0;
2313 int have_32x;
234c4556 2314 int en_32x;
ffd4b35c 2315 int ret;
a385208c 2316 u8 v8;
ffd4b35c 2317 int i;
2318
2319 setup_z80();
2320
a385208c 2321 /* io */
2322 write8(0xa10009, 0x40);
2323
ffd4b35c 2324 /* setup VDP */
2325 while (read16(VDP_CTRL_PORT) & 2)
2326 ;
2327
2328 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
2329 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
2330 VDP_setReg(VDP_MODE3, 0x00);
2331 VDP_setReg(VDP_MODE4, 0x81);
2332 VDP_setReg(VDP_NT_SCROLLA, APLANE >> 10);
2333 VDP_setReg(VDP_NT_SCROLLB, BPLANE >> 13);
2334 VDP_setReg(VDP_SAT_BASE, SLIST >> 9);
2335 VDP_setReg(VDP_HSCROLL, HSCRL >> 10);
2336 VDP_setReg(VDP_AUTOINC, 2);
2337 VDP_setReg(VDP_SCROLLSZ, 0x01);
2338 VDP_setReg(VDP_BACKDROP, 0);
2339
2340 // early tests
2341 t_dma_zero_wrap_early();
2342 t_dma_zero_fill_early();
2343
2344 /* pattern 0 */
2345 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
2346 for (i = 0; i < 32 / 4; i++)
2347 write32(VDP_DATA_PORT, 0);
2348
2349 /* clear name tables */
2350 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
2351 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
2352 write32(VDP_DATA_PORT, 0);
2353
2354 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(BPLANE));
2355 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
2356 write32(VDP_DATA_PORT, 0);
2357
2358 /* SAT, h. scroll */
2359 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(SLIST));
2360 write32(VDP_DATA_PORT, 0);
2361
2362 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2363 write32(VDP_DATA_PORT, 0);
2364
2365 /* scroll plane vscroll */
2366 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2367 write32(VDP_DATA_PORT, 0);
2368 printf_ypos = 1;
2369
2370 /* load font */
2371 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(TILE_FONT_BASE));
2372 for (i = 0; i < FONT_LEN * 32 / 4; i++)
2373 write32(VDP_DATA_PORT, font_base[i]);
2374
2375 /* set colors */
2376 setup_default_palette();
2377
2378 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
2379
9d39a80e 2380 have_32x = read32(0xa130ec) == MKLONG('M','A','R','S');
5073ab5a 2381 en_32x = have_32x && (read16(0xa15100) & 1);
a385208c 2382 v8 = read8(0xa10001);
234c4556 2383 printf("MD version: %02x %s %s %s%s\n", v8,
a385208c 2384 (v8 & 0x80) ? "world" : "jap",
9d39a80e 2385 (v8 & 0x40) ? "pal" : "ntsc",
234c4556 2386 have_32x ? "32X" : "",
2387 en_32x ? "+" : "");
ffd4b35c 2388
2389 for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
2390 // print test number if we haven't scrolled away
2391 if (printf_ypos < CSCREEN_H) {
2392 int old_ypos = printf_ypos;
2393 printf_ypos = 0;
ffd4b35c 2394 printf("%02d/%02d", i, ARRAY_SIZE(g_tests));
2395 printf_ypos = old_ypos;
2396 printf_xpos = 0;
2397 }
9d39a80e 2398 if ((g_tests[i].type & T_32) && !have_32x) {
2399 skipped++;
2400 continue;
2401 }
ffd4b35c 2402 ret = g_tests[i].test();
5073ab5a 2403 if (ret == R_SKIP) {
2404 skipped++;
2405 continue;
2406 }
a385208c 2407 if (ret != 1) {
2408 text_pal = 2;
ffd4b35c 2409 printf("failed %d: %s\n", i, g_tests[i].name);
a385208c 2410 text_pal = 0;
2411 }
ffd4b35c 2412 else
2413 passed++;
2414 }
2415
2416 text_pal = 0;
9d39a80e 2417 printf("%d/%d passed, %d skipped.\n",
2418 passed, ARRAY_SIZE(g_tests), skipped);
ffd4b35c 2419
2420 printf_ypos = 0;
2421 printf(" ");
2422
5073ab5a 2423 if (have_32x) {
2424 u8 *p = (u8 *)0xff0040;
2425 u32 len = x32x_switch_rv_end - x32x_switch_rv;
2426 px32x_switch_rv = (void *)p; p += len;
2427 memcpy_(px32x_switch_rv, x32x_switch_rv, len);
2428
2429 len = get_input_end - get_input_s;
2430 pget_input = (void *)p; p += len;
2431 memcpy_(pget_input, get_input_s, len);
2432
2433 // prepare for reset - run from 880xxx as the reset vector points there
2434 // todo: broken printf
2435 px32x_switch_rv(0);
2436 }
2437 for (i = 0; i < 60*60 && !(pget_input() & BTNM_A); i++)
a385208c 2438 wait_next_vsync();
e71680d5 2439#ifndef PICO
2440 // blank due to my lame tv being burn-in prone
2441 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
2442#endif
5073ab5a 2443 while (!(pget_input() & BTNM_A))
e71680d5 2444 burn10(488*100/10);
2445 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
a385208c 2446
2447
2448 {
2449 char c[3] = { '0', '0', '0' };
2450 short hscroll = 0, vscroll = 0;
2451 short hsz = 1, vsz = 0;
2452 short cellmode = 0;
2453
2454 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
2455
cc7e5122 2456#if 0
2457 for (i = 0, c[0] = 'a'; i < 8 * 1024 / 2; i++) {
2458 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2459 c[0]++;
2460 if (c[0] == 'z' + 1)
2461 c[0] = 'a';
2462 }
2463#else
a385208c 2464 for (i = 0; i < 8 * 1024 / 2 / 4; i++) {
2465 write16(VDP_DATA_PORT, (u16)'.' - 32 + TILE_FONT_BASE / 32);
2466 write16(VDP_DATA_PORT, (u16)c[2] - 32 + TILE_FONT_BASE / 32);
2467 write16(VDP_DATA_PORT, (u16)c[1] - 32 + TILE_FONT_BASE / 32);
2468 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2469 if (hexinc(&c[0]))
2470 if (hexinc(&c[1]))
2471 hexinc(&c[2]);
2472 }
cc7e5122 2473#endif
5073ab5a 2474 while (pget_input() & BTNM_A)
a385208c 2475 wait_next_vsync();
2476
2477 wait_next_vsync();
2478 for (;;) {
5073ab5a 2479 int b = pget_input();
a385208c 2480
2481 if (b & BTNM_C) {
2482 hscroll = 1, vscroll = -1;
2483 do {
2484 wait_next_vsync();
5073ab5a 2485 } while (pget_input() & BTNM_C);
a385208c 2486 cellmode ^= 1;
2487 }
2488 if (b & (BTNM_L | BTNM_R | BTNM_C)) {
2489 hscroll += (b & BTNM_L) ? 1 : -1;
2490 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2491 write16(VDP_DATA_PORT, hscroll);
2492 }
2493 if (b & (BTNM_U | BTNM_D | BTNM_C)) {
2494 vscroll += (b & BTNM_U) ? -1 : 1;
2495 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2496 if (cellmode) {
2497 int end = (int)vscroll + 21;
2498 for (i = vscroll; i < end; i++)
2499 write32(VDP_DATA_PORT, i << 17);
2500 VDP_setReg(VDP_MODE3, 0x04);
2501 }
2502 else {
2503 write16(VDP_DATA_PORT, vscroll);
2504 VDP_setReg(VDP_MODE3, 0x00);
2505 }
2506 }
2507 if (b & BTNM_A) {
2508 hsz = (hsz + 1) & 3;
2509 do {
2510 wait_next_vsync();
5073ab5a 2511 } while (pget_input() & BTNM_A);
a385208c 2512 }
2513 if (b & BTNM_B) {
2514 vsz = (vsz + 1) & 3;
2515 do {
2516 wait_next_vsync();
5073ab5a 2517 } while (pget_input() & BTNM_B);
a385208c 2518 }
2519 VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz);
2520
2521 printf_xpos = 1;
2522 printf_ypos = 0;
2523 text_pal = 1;
2524 printf(" %d %d ", hsz, vsz);
2525
2526 wait_next_vsync();
2527 }
2528 }
2529
ffd4b35c 2530 for (;;)
2531 ;
2532
2533 return 0;
2534}
2535
2536// vim:ts=4:sw=4:expandtab