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1 | |
2 | .text |
3 | |
4 | ! Master Vector Base Table at 0x06000000 |
5 | |
6 | .long mstart /* Cold Start PC */ |
7 | .long 0x06040000 /* Cold Start SP */ |
8 | .long mstart /* Manual Reset PC */ |
9 | .long 0x06040000 /* Manual Reset SP */ |
71b41fdd |
10 | .long master_e4 /* Illegal instruction */ |
11 | .long master_e5 /* reserved */ |
12 | .long master_e6 /* Invalid slot instruction */ |
13 | .long master_e7 /* reserved */ |
14 | .long master_e8 /* reserved */ |
15 | .long master_e9 /* CPU address error */ |
16 | .long master_e10 /* DMA address error */ |
17 | .long master_e11 /* NMI vector */ |
18 | .long master_e12 /* User break vector */ |
19 | .rept 19 |
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20 | .long master_err /* reserved */ |
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21 | .endr |
22 | .rept 32 |
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23 | .long master_err /* TRAPA #32-63 */ |
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24 | .endr |
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25 | .long master_irq0 /* Level 1 IRQ */ |
26 | .long master_irq1 /* Level 2 & 3 IRQ's */ |
27 | .long master_irq2 /* Level 4 & 5 IRQ's */ |
28 | .long master_irq3 /* PWM interupt */ |
29 | .long master_irq4 /* Command interupt */ |
30 | .long master_irq5 /* H Blank interupt */ |
31 | .long master_irq6 /* V Blank interupt */ |
32 | .long master_irq7 /* Reset Button */ |
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33 | .rept 56 |
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34 | .long master_err /* peripherals */ |
71b41fdd |
35 | .endr |
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36 | |
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37 | ! Slave Vector Base Table at 0x06000200 |
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38 | |
39 | .long sstart /* Cold Start PC */ |
40 | .long 0x0603f800 /* Cold Start SP */ |
41 | .long sstart /* Manual Reset PC */ |
42 | .long 0x0603f800 /* Manual Reset SP */ |
71b41fdd |
43 | .long slave_e4 /* Illegal instruction */ |
44 | .long slave_e5 /* reserved */ |
45 | .long slave_e6 /* Invalid slot instruction */ |
46 | .long slave_e7 /* reserved */ |
47 | .long slave_e8 /* reserved */ |
48 | .long slave_e9 /* CPU address error */ |
49 | .long slave_e10 /* DMA address error */ |
50 | .long slave_e11 /* NMI vector */ |
51 | .long slave_e12 /* User break vector */ |
52 | .rept 19 |
53 | .long slave_err /* reserved */ |
54 | .endr |
55 | .rept 32 |
56 | .long slave_err /* TRAPA #32-63 */ |
57 | .endr |
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58 | .long slave_irq0 /* Level 1 IRQ */ |
59 | .long slave_irq1 /* Level 2 & 3 IRQ's */ |
60 | .long slave_irq2 /* Level 4 & 5 IRQ's */ |
61 | .long slave_irq3 /* PWM interupt */ |
62 | .long slave_irq4 /* Command interupt */ |
63 | .long slave_irq5 /* H Blank interupt */ |
64 | .long slave_irq6 /* V Blank interupt */ |
65 | .long slave_irq7 /* Reset Button */ |
71b41fdd |
66 | .rept 56 |
67 | .long slave_err /* peripherals */ |
68 | .endr |
69 | |
70 | ! trashes r0 |
71 | .macro mov_bc const ofs reg |
72 | mov #\const, r0 |
73 | .if \ofs == 0 |
74 | mov.b r0, @\reg |
75 | .else |
76 | mov.b r0, @(\ofs, \reg) |
77 | .endif |
78 | .endm |
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79 | |
80 | ! Stacks set up by BIOS |
81 | |
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82 | ! The main SH2 starts here at 0x06000400 |
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83 | |
84 | mstart: |
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85 | bra xstart |
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86 | mov #0, r4 |
87 | |
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88 | ! The slave SH2 starts here at 0x06000404 |
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89 | |
90 | sstart: |
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91 | mov #1, r4 |
92 | |
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93 | xstart: |
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94 | .if 0 |
95 | ! cache init - done by BIOS with single 0x11 write |
96 | mov.l l_cctl, r1 /* cache */ |
97 | mov_bc 0x00, 0, r1 /* disable */ |
98 | mov.b @r1, r0 /* dummy read */ |
99 | mov_bc 0x10, 0, r1 /* purge */ |
100 | mov.b @r1, r0 |
101 | mov_bc 0x01, 0, r1 /* enable */ |
102 | .endif |
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103 | mov #0x10, r0 /* enable irqs, 0 causes endless irq */ |
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104 | ldc r0, sr |
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105 | mov.l l_main_c, r0 |
106 | jmp @r0 |
107 | nop |
108 | |
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109 | ! r0=vector_number |
110 | do_irq_master: |
111 | mov.b r0, @(0x2c, gbr) |
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112 | mov.l r1, @-r15 |
113 | mov.l l_irq_cnt, r1 /* counters in fb (0x2401ff00) */ |
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114 | |
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115 | do_irq_cmn: |
116 | mov.l r2, @-r15 |
117 | mov #0x80, r0 |
118 | mov.b r0, @(0, gbr) /* FM=1 */ |
119 | mov.b r0, @(0, gbr) /* flush write buf */ |
120 | stc sr, r0 /* SR holds IRQ level in I3-I0 */ |
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121 | shlr2 r0 |
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122 | shlr2 r0 |
123 | and #0x0e, r0 |
124 | mov r0, r2 |
125 | add r1, r0 |
126 | mov.w @r0, r1 |
127 | add #1, r1 |
128 | mov.w r1, @r0 |
129 | mova l_irq_ao, r0 |
130 | mov.w @(r0, r2), r0 |
131 | stc gbr, r1 |
132 | mov.w r0, @(r0, r1) /* ack */ |
133 | mov #0x80, r0 |
134 | mov.b r0, @(0, gbr) /* FM=1 and flush writebuf (alt: ~20 nops) */ |
135 | mov.l @r15+, r2 |
136 | mov.l @r15+, r1 |
137 | mov.l @r15+, r0 |
138 | rte |
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139 | nop |
140 | |
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141 | ! not used |
142 | .if 0 |
143 | main_irq_vres_: |
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144 | mov.w r0, @(0x14, gbr) /* ack */ |
145 | mov.b @(7, gbr), r0 /* RV */ |
146 | tst #1, r0 |
147 | bt main_irq_ret |
148 | |
149 | ! Try to set FTOB pin that's wired to 32X hard reset. |
150 | ! Doesn't seem to be working right though, it somehow disturbs |
151 | ! 68k reset PC fetch which mysteriously ends up at range |
152 | ! 2c8 - 304 in multiples of 4, proportionally to reset delay |
153 | ! (0 - ~300 (?) sh2 cycles). Longer delay just hangs, presumably |
154 | ! at 880200? |
155 | mov.l l_frt, r1 |
156 | mov_bc 0xf1, 7, r1 /* TOCR sel OCRB, pin on B match */ |
157 | mov #0, r0 |
158 | mov.b r0, @(4, r1) /* OCRB H - output compare B */ |
159 | mov.b r0, @(5, r1) /* OCRB L */ |
160 | mov.b r0, @(2, r1) /* FRC H */ |
161 | mov.b r0, @(3, r1) /* FRC L */ |
162 | mov.b @(7, r1), r0 |
163 | ! sleep - docs say not to use |
164 | ! sleep |
165 | 0: |
166 | bra 0b |
167 | nop |
168 | |
169 | main_irq_ret: |
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170 | mov.l @r15+, r0 |
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171 | rte |
172 | nop |
173 | .endif |
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174 | |
175 | .global _read_frt |
176 | _read_frt: |
177 | mov.l l_frt, r2 |
178 | mov.b @(2, r2), r0 |
179 | extu.b r0, r1 |
180 | mov.b @(3, r2), r0 |
181 | extu.b r0, r0 |
182 | shll8 r1 |
183 | rts |
184 | or r1, r0 |
185 | |
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186 | ! dummy |
187 | .global _start |
188 | _start: |
189 | |
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190 | master_err: |
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191 | bra do_exc_master |
192 | mov #0xff, r0 |
193 | slave_err: |
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194 | bra do_exc_slave |
195 | mov #0xff, r0 |
196 | |
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197 | ! r0=vector_number |
198 | do_irq_slave: |
199 | mov.b r0, @(0x2d, gbr) |
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200 | mov.l r1, @-r15 |
201 | mov.l l_irq_cnt, r1 /* counters in fb (0x2401ff00) */ |
202 | bra do_irq_cmn |
203 | add #0x10, r1 |
204 | |
205 | .align 2 |
206 | l_cctl: |
207 | .long 0xFFFFFE92 |
208 | l_frt: |
209 | .long 0xFFFFFE10 |
210 | l_main_c: |
211 | .long _main_c |
212 | l_irq_cnt: |
213 | .long 0x2401ff00 |
214 | l_irq_ao: |
215 | /* ?, ?, ?, pwm, cmd, h, v, rst */ |
216 | .word 0x0e, 0x0e, 0x0e, 0x1c, 0x1a, 0x18, 0x16, 0x14 |
217 | |
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218 | .macro exc_master num |
219 | master_e\num: |
220 | bra do_exc_master |
221 | mov #\num, r0 |
222 | .endm |
223 | |
224 | .macro exc_slave num |
225 | slave_e\num: |
226 | bra do_exc_slave |
227 | mov #\num, r0 |
228 | .endm |
229 | |
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230 | .macro irq_master num |
231 | master_irq\num: |
232 | mov.l r0, @-r15 |
233 | bra do_irq_master |
234 | mov #\num, r0 |
235 | .endm |
236 | |
237 | .macro irq_slave num |
238 | slave_irq\num: |
239 | mov.l r0, @-r15 |
240 | bra do_irq_slave |
241 | mov #\num, r0 |
242 | .endm |
243 | |
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244 | exc_master 4 |
245 | exc_master 5 |
246 | exc_master 6 |
247 | exc_master 7 |
248 | exc_master 8 |
249 | exc_master 9 |
250 | exc_master 10 |
251 | exc_master 11 |
252 | exc_master 12 |
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253 | irq_master 0 |
254 | irq_master 1 |
255 | irq_master 2 |
256 | irq_master 3 |
257 | irq_master 4 |
258 | irq_master 5 |
259 | irq_master 6 |
260 | irq_master 7 |
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261 | |
262 | exc_slave 4 |
263 | exc_slave 5 |
264 | exc_slave 6 |
265 | exc_slave 7 |
266 | exc_slave 8 |
267 | exc_slave 9 |
268 | exc_slave 10 |
269 | exc_slave 11 |
270 | exc_slave 12 |
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271 | irq_slave 0 |
272 | irq_slave 1 |
273 | irq_slave 2 |
274 | irq_slave 3 |
275 | irq_slave 4 |
276 | irq_slave 5 |
277 | irq_slave 6 |
278 | irq_slave 7 |
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279 | |
280 | do_exc_master: |
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281 | mov.b r0, @(0x2e, gbr) |
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282 | 0: |
283 | bra 0b |
284 | nop |
285 | |
286 | do_exc_slave: |
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287 | mov.b r0, @(0x2f, gbr) |
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288 | 0: |
289 | bra 0b |
290 | nop |
291 | |
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292 | .global _spin |
293 | _spin: |
294 | dt r4 |
295 | bf _spin |
296 | rts |
297 | nop |
298 | |
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299 | ! vim:ts=8:sw=8:expandtab |