| 9d39a80e |
1 | |
| 2 | .text |
| 3 | |
| 4 | ! Master Vector Base Table at 0x06000000 |
| 5 | |
| 6 | .long mstart /* Cold Start PC */ |
| 7 | .long 0x06040000 /* Cold Start SP */ |
| 8 | .long mstart /* Manual Reset PC */ |
| 9 | .long 0x06040000 /* Manual Reset SP */ |
| 10 | .long main_err /* Illegal instruction */ |
| 11 | .long 0x00000000 /* reserved */ |
| 12 | .long main_err /* Invalid slot instruction */ |
| 13 | .long 0x20100400 /* reserved */ |
| 14 | .long 0x20100420 /* reserved */ |
| 15 | .long main_err /* CPU address error */ |
| 16 | .long main_err /* DMA address error */ |
| 17 | .long main_err /* NMI vector */ |
| 18 | .long main_err /* User break vector */ |
| 19 | .space 76 /* reserved */ |
| 20 | .long main_err /* TRAPA #32 */ |
| 21 | .long main_err /* TRAPA #33 */ |
| 22 | .long main_err /* TRAPA #34 */ |
| 23 | .long main_err /* TRAPA #35 */ |
| 24 | .long main_err /* TRAPA #36 */ |
| 25 | .long main_err /* TRAPA #37 */ |
| 26 | .long main_err /* TRAPA #38 */ |
| 27 | .long main_err /* TRAPA #39 */ |
| 28 | .long main_err /* TRAPA #40 */ |
| 29 | .long main_err /* TRAPA #41 */ |
| 30 | .long main_err /* TRAPA #42 */ |
| 31 | .long main_err /* TRAPA #43 */ |
| 32 | .long main_err /* TRAPA #44 */ |
| 33 | .long main_err /* TRAPA #45 */ |
| 34 | .long main_err /* TRAPA #46 */ |
| 35 | .long main_err /* TRAPA #47 */ |
| 36 | .long main_err /* TRAPA #48 */ |
| 37 | .long main_err /* TRAPA #49 */ |
| 38 | .long main_err /* TRAPA #50 */ |
| 39 | .long main_err /* TRAPA #51 */ |
| 40 | .long main_err /* TRAPA #52 */ |
| 41 | .long main_err /* TRAPA #53 */ |
| 42 | .long main_err /* TRAPA #54 */ |
| 43 | .long main_err /* TRAPA #55 */ |
| 44 | .long main_err /* TRAPA #56 */ |
| 45 | .long main_err /* TRAPA #57 */ |
| 46 | .long main_err /* TRAPA #58 */ |
| 47 | .long main_err /* TRAPA #59 */ |
| 48 | .long main_err /* TRAPA #60 */ |
| 49 | .long main_err /* TRAPA #61 */ |
| 50 | .long main_err /* TRAPA #62 */ |
| 51 | .long main_err /* TRAPA #63 */ |
| 52 | .long main_irq /* Level 1 IRQ */ |
| 53 | .long main_irq /* Level 2 & 3 IRQ's */ |
| 54 | .long main_irq /* Level 4 & 5 IRQ's */ |
| 55 | .long main_irq /* PWM interupt */ |
| 56 | .long main_irq /* Command interupt */ |
| 57 | .long main_irq /* H Blank interupt */ |
| 58 | .long main_irq /* V Blank interupt */ |
| 59 | .long main_irq /* Reset Button */ |
| 60 | .long main_irq /* DMA1 TE INT */ |
| 61 | |
| 62 | ! Slave Vector Base Table at 0x06000124 |
| 63 | |
| 64 | .long sstart /* Cold Start PC */ |
| 65 | .long 0x0603f800 /* Cold Start SP */ |
| 66 | .long sstart /* Manual Reset PC */ |
| 67 | .long 0x0603f800 /* Manual Reset SP */ |
| 68 | .long slav_err /* Illegal instruction */ |
| 69 | .long 0x00000000 /* reserved */ |
| 70 | .long slav_err /* Invalid slot instruction */ |
| 71 | .long 0x20100400 /* reserved */ |
| 72 | .long 0x20100420 /* reserved */ |
| 73 | .long slav_err /* CPU address error */ |
| 74 | .long slav_err /* DMA address error */ |
| 75 | .long slav_err /* NMI vector */ |
| 76 | .long slav_err /* User break vector */ |
| 77 | .space 76 /* reserved */ |
| 78 | .long slav_err /* TRAPA #32 */ |
| 79 | .long slav_err /* TRAPA #33 */ |
| 80 | .long slav_err /* TRAPA #34 */ |
| 81 | .long slav_err /* TRAPA #35 */ |
| 82 | .long slav_err /* TRAPA #36 */ |
| 83 | .long slav_err /* TRAPA #37 */ |
| 84 | .long slav_err /* TRAPA #38 */ |
| 85 | .long slav_err /* TRAPA #39 */ |
| 86 | .long slav_err /* TRAPA #40 */ |
| 87 | .long slav_err /* TRAPA #41 */ |
| 88 | .long slav_err /* TRAPA #42 */ |
| 89 | .long slav_err /* TRAPA #43 */ |
| 90 | .long slav_err /* TRAPA #44 */ |
| 91 | .long slav_err /* TRAPA #45 */ |
| 92 | .long slav_err /* TRAPA #46 */ |
| 93 | .long slav_err /* TRAPA #47 */ |
| 94 | .long slav_err /* TRAPA #48 */ |
| 95 | .long slav_err /* TRAPA #49 */ |
| 96 | .long slav_err /* TRAPA #50 */ |
| 97 | .long slav_err /* TRAPA #51 */ |
| 98 | .long slav_err /* TRAPA #52 */ |
| 99 | .long slav_err /* TRAPA #53 */ |
| 100 | .long slav_err /* TRAPA #54 */ |
| 101 | .long slav_err /* TRAPA #55 */ |
| 102 | .long slav_err /* TRAPA #56 */ |
| 103 | .long slav_err /* TRAPA #57 */ |
| 104 | .long slav_err /* TRAPA #58 */ |
| 105 | .long slav_err /* TRAPA #59 */ |
| 106 | .long slav_err /* TRAPA #60 */ |
| 107 | .long slav_err /* TRAPA #61 */ |
| 108 | .long slav_err /* TRAPA #62 */ |
| 109 | .long slav_err /* TRAPA #63 */ |
| 110 | .long slav_irq /* Level 1 IRQ */ |
| 111 | .long slav_irq /* Level 2 & 3 IRQ's */ |
| 112 | .long slav_irq /* Level 4 & 5 IRQ's */ |
| 113 | .long slav_irq /* PWM interupt */ |
| 114 | .long slav_irq /* Command interupt */ |
| 115 | .long slav_irq /* H Blank interupt */ |
| 116 | .long slav_irq /* V Blank interupt */ |
| 117 | .long slav_irq /* Reset Button */ |
| 118 | |
| 119 | ! Stacks set up by BIOS |
| 120 | |
| 121 | ! The main SH2 starts here at 0x06000244 |
| 122 | |
| 123 | mstart: |
| 124 | bra mcont |
| 125 | mov #0, r4 |
| 126 | |
| 127 | ! The slave SH2 starts here at 0x06000248 |
| 128 | |
| 129 | sstart: |
| 130 | sleep |
| 131 | ! broken |
| 132 | bra xstart |
| 133 | mov #1, r4 |
| 134 | |
| 135 | mcont: |
| 136 | |
| 137 | xstart: |
| 138 | mov.l l_cctl, r0 |
| 139 | mov #0x11, r1 |
| 140 | mov.b r1, @r0 |
| 141 | mov.l l_main_c, r0 |
| 142 | jmp @r0 |
| 143 | nop |
| 144 | |
| 145 | .align 2 |
| 146 | l_cctl: |
| 147 | .long 0xFFFFFE92 |
| 148 | l_main_c: |
| 149 | .long _main_c |
| 150 | |
| 151 | ! dummy |
| 152 | .global _start |
| 153 | _start: |
| 154 | |
| 155 | .global _spin |
| 156 | _spin: |
| 157 | dt r4 |
| 158 | bf _spin |
| 159 | rts |
| 160 | nop |
| 161 | |
| 162 | main_err: |
| 163 | main_irq: |
| 164 | slav_err: |
| 165 | slav_irq: |
| 166 | 0: |
| 167 | bra 0b |
| 168 | nop |
| 169 | |
| 170 | ! vim:ts=8:sw=8:expandtab |
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