psp snd output improved
[picodrive.git] / Pico / Memory.c
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1// This is part of Pico Library\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4// (c) Copyright 2006 notaz, All rights reserved.\r
5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9\r
10#define __debug_io\r
11\r
12#include "PicoInt.h"\r
13\r
14#include "sound/ym2612.h"\r
15#include "sound/sn76496.h"\r
16\r
17#ifndef UTYPES_DEFINED\r
18typedef unsigned char u8;\r
19typedef unsigned short u16;\r
20typedef unsigned int u32;\r
21#define UTYPES_DEFINED\r
22#endif\r
23\r
24extern unsigned int lastSSRamWrite; // used by serial SRAM code\r
25\r
26#ifdef _ASM_MEMORY_C\r
27u32 PicoRead8(u32 a);\r
28u32 PicoRead16(u32 a);\r
29void PicoWrite8(u32 a,u8 d);\r
30void PicoWriteRomHW_SSF2(u32 a,u32 d);\r
31void PicoWriteRomHW_in1 (u32 a,u32 d);\r
32#endif\r
33\r
34\r
35#ifdef EMU_CORE_DEBUG\r
36u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
37int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;\r
38extern unsigned int ppop;\r
39#endif\r
40\r
41#ifdef IO_STATS\r
42void log_io(unsigned int addr, int bits, int rw);\r
43#else\r
44#define log_io(...)\r
45#endif\r
46\r
47#if defined(EMU_C68K)\r
48static __inline int PicoMemBase(u32 pc)\r
49{\r
50 int membase=0;\r
51\r
52 if (pc<Pico.romsize+4)\r
53 {\r
54 membase=(int)Pico.rom; // Program Counter in Rom\r
55 }\r
56 else if ((pc&0xe00000)==0xe00000)\r
57 {\r
58 membase=(int)Pico.ram-(pc&0xff0000); // Program Counter in Ram\r
59 }\r
60 else\r
61 {\r
62 // Error - Program Counter is invalid\r
63 membase=(int)Pico.rom;\r
64 }\r
65\r
66 return membase;\r
67}\r
68#endif\r
69\r
70\r
71static u32 PicoCheckPc(u32 pc)\r
72{\r
73 u32 ret=0;\r
74#if defined(EMU_C68K)\r
75 pc-=PicoCpuCM68k.membase; // Get real pc\r
76// pc&=0xfffffe;\r
77 pc&=~1;\r
78 if ((pc<<8) == 0)\r
79 {\r
80 printf("%i:%03i: game crash detected @ %06x\n", Pico.m.frame_count, Pico.m.scanline, SekPc);\r
81 return (int)Pico.rom + Pico.romsize; // common crash condition, can happen if acc timing is off\r
82 }\r
83\r
84 PicoCpuCM68k.membase=PicoMemBase(pc&0x00ffffff);\r
85 PicoCpuCM68k.membase-=pc&0xff000000;\r
86\r
87 ret = PicoCpuCM68k.membase+pc;\r
88#endif\r
89 return ret;\r
90}\r
91\r
92\r
93PICO_INTERNAL int PicoInitPc(u32 pc)\r
94{\r
95 PicoCheckPc(pc);\r
96 return 0;\r
97}\r
98\r
99#ifndef _ASM_MEMORY_C\r
100PICO_INTERNAL_ASM void PicoMemReset(void)\r
101{\r
102}\r
103#endif\r
104\r
105// -----------------------------------------------------------------\r
106\r
107int PadRead(int i)\r
108{\r
109 int pad,value,data_reg;\r
110 pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU\r
111 data_reg=Pico.ioports[i+1];\r
112\r
113 // orr the bits, which are set as output\r
114 value = data_reg&(Pico.ioports[i+4]|0x80);\r
115\r
116 if(PicoOpt & 0x20) { // 6 button gamepad enabled\r
117 int phase = Pico.m.padTHPhase[i];\r
118\r
119 if(phase == 2 && !(data_reg&0x40)) { // TH\r
120 value|=(pad&0xc0)>>2; // ?0SA 0000\r
121 return value;\r
122 } else if(phase == 3) {\r
123 if(data_reg&0x40)\r
124 value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r
125 else\r
126 value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r
127 return value;\r
128 }\r
129 }\r
130\r
131 if(data_reg&0x40) // TH\r
132 value|=(pad&0x3f); // ?1CB RLDU\r
133 else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
134\r
135 return value; // will mirror later\r
136}\r
137\r
138\r
139#ifndef _ASM_MEMORY_C\r
140static\r
141#endif\r
142u32 SRAMRead(u32 a)\r
143{\r
144 unsigned int sreg = Pico.m.sram_reg;\r
145 if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
146 elprintf(EL_SRAMIO, "normal sram detected.");\r
147 Pico.m.sram_reg|=0x10; // should be normal SRAM\r
148 }\r
149 if(sreg & 4) // EEPROM read\r
150 return SRAMReadEEPROM();\r
151 else // if(sreg & 1) // (sreg&5) is one of prerequisites\r
152 return *(u8 *)(SRam.data-SRam.start+a);\r
153}\r
154\r
155static void SRAMWrite(u32 a, u32 d)\r
156{\r
157 unsigned int sreg = Pico.m.sram_reg;\r
158 if(!(sreg & 0x10)) {\r
159 // not detected SRAM\r
160 if((a&~1)==0x200000) {\r
161 elprintf(EL_SRAMIO, "eeprom detected.");\r
162 sreg|=4; // this should be a game with EEPROM (like NBA Jam)\r
163 SRam.start=0x200000; SRam.end=SRam.start+1;\r
164 } else\r
165 elprintf(EL_SRAMIO, "normal sram detected.");\r
166 sreg|=0x10;\r
167 Pico.m.sram_reg=sreg;\r
168 }\r
169 if(sreg & 4) { // EEPROM write\r
170 // this diff must be at most 16 for NBA Jam to work\r
171 if(SekCyclesDoneT()-lastSSRamWrite < 16) {\r
172 // just update pending state\r
173 elprintf(EL_EEPROM, "eeprom: skip because cycles=%i", SekCyclesDoneT()-lastSSRamWrite);\r
174 SRAMUpdPending(a, d);\r
175 } else {\r
176 int old=sreg;\r
177 SRAMWriteEEPROM(sreg>>6); // execute pending\r
178 SRAMUpdPending(a, d);\r
179 if ((old^Pico.m.sram_reg)&0xc0) // update time only if SDA/SCL changed\r
180 lastSSRamWrite = SekCyclesDoneT();\r
181 }\r
182 } else if(!(sreg & 2)) {\r
183 u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
184 if(*pm != (u8)d) {\r
185 SRam.changed = 1;\r
186 *pm=(u8)d;\r
187 }\r
188 }\r
189}\r
190\r
191// for nonstandard reads\r
192#ifndef _ASM_MEMORY_C\r
193static\r
194#endif\r
195u32 OtherRead16End(u32 a, int realsize)\r
196{\r
197 u32 d=0;\r
198\r
199 // for games with simple protection devices, discovered by Haze\r
200 // some dumb detection is used, but that should be enough to make things work\r
201 if ((a>>22) == 1 && Pico.romsize >= 512*1024) {\r
202 if (*(int *)(Pico.rom+0x123e4) == 0x00550c39 && *(int *)(Pico.rom+0x123e8) == 0x00000040) { // Super Bubble Bobble (Unl) [!]\r
203 if (a == 0x400000) { d=0x55<<8; goto end; }\r
204 else if (a == 0x400002) { d=0x0f<<8; goto end; }\r
205 }\r
206 else if (*(int *)(Pico.rom+0x008c4) == 0x66240055 && *(int *)(Pico.rom+0x008c8) == 0x00404df9) { // Smart Mouse (Unl)\r
207 if (a == 0x400000) { d=0x55<<8; goto end; }\r
208 else if (a == 0x400002) { d=0x0f<<8; goto end; }\r
209 else if (a == 0x400004) { d=0xaa<<8; goto end; }\r
210 else if (a == 0x400006) { d=0xf0<<8; goto end; }\r
211 }\r
212 else if (*(int *)(Pico.rom+0x00404) == 0x00a90600 && *(int *)(Pico.rom+0x00408) == 0x6708b013) { // King of Fighters '98, The (Unl) [!]\r
213 if (a == 0x480000 || a == 0x4800e0 || a == 0x4824a0 || a == 0x488880) { d=0xaa<<8; goto end; }\r
214 else if (a == 0x4a8820) { d=0x0a<<8; goto end; }\r
215 // there is also a read @ 0x4F8820 which needs 0, but that is returned in default case\r
216 }\r
217 else if (*(int *)(Pico.rom+0x01b24) == 0x004013f9 && *(int *)(Pico.rom+0x01b28) == 0x00ff0000) { // Mahjong Lover (Unl) [!]\r
218 if (a == 0x400000) { d=0x90<<8; goto end; }\r
219 else if (a == 0x401000) { d=0xd3<<8; goto end; } // this one doesn't seem to be needed, the code does 2 comparisons and only then\r
220 // checks the result, which is of the above one. Left it just in case.\r
221 }\r
222 else if (*(int *)(Pico.rom+0x05254) == 0x0c3962d0 && *(int *)(Pico.rom+0x05258) == 0x00400055) { // Elf Wor (Unl)\r
223 if (a == 0x400000) { d=0x55<<8; goto end; }\r
224 else if (a == 0x400004) { d=0xc9<<8; goto end; } // this check is done if the above one fails\r
225 else if (a == 0x400002) { d=0x0f<<8; goto end; }\r
226 else if (a == 0x400006) { d=0x18<<8; goto end; } // similar to above\r
227 }\r
228 // our default behaviour is to return whatever was last written a 0x400000-0x7fffff range (used by Squirrel King (R) [!])\r
229 // Lion King II, The (Unl) [!] writes @ 400000 and wants to get that val @ 400002 and wites another val\r
230 // @ 400004 which is expected @ 400006, so we really remember 2 values here\r
231 d = Pico.m.prot_bytes[(a>>2)&1]<<8;\r
232 }\r
233 else if (a == 0xa13000 && Pico.romsize >= 1024*1024) {\r
234 if (*(int *)(Pico.rom+0xc8af0) == 0x30133013 && *(int *)(Pico.rom+0xc8af4) == 0x000f0240) { // Rockman X3 (Unl) [!]\r
235 d=0x0c; goto end;\r
236 }\r
237 else if (*(int *)(Pico.rom+0x28888) == 0x07fc0000 && *(int *)(Pico.rom+0x2888c) == 0x4eb94e75) { // Bug's Life, A (Unl) [!]\r
238 d=0x28; goto end; // does the check from RAM\r
239 }\r
240 else if (*(int *)(Pico.rom+0xc8778) == 0x30133013 && *(int *)(Pico.rom+0xc877c) == 0x000f0240) { // Super Mario Bros. (Unl) [!]\r
241 d=0x0c; goto end; // seems to be the same code as in Rockman X3 (Unl) [!]\r
242 }\r
243 else if (*(int *)(Pico.rom+0xf20ec) == 0x30143013 && *(int *)(Pico.rom+0xf20f0) == 0x000f0200) { // Super Mario 2 1998 (Unl) [!]\r
244 d=0x0a; goto end;\r
245 }\r
246 }\r
247 else if (a == 0xa13002) { // Pocket Monsters (Unl)\r
248 d=0x01; goto end;\r
249 }\r
250 else if (a == 0xa1303E) { // Pocket Monsters (Unl)\r
251 d=0x1f; goto end;\r
252 }\r
253 else if (a == 0x30fe02) {\r
254 // Virtua Racing - just for fun\r
255 // this seems to be some flag that SVP is ready or something similar\r
256 d=1; goto end;\r
257 }\r
258\r
259end:\r
260 elprintf(EL_UIO, "strange r%i: [%06x] %04x @%06x", realsize, a&0xffffff, d, SekPc);\r
261 return d;\r
262}\r
263\r
264\r
265//extern UINT32 mz80GetRegisterValue(void *, UINT32);\r
266\r
267static void OtherWrite8End(u32 a,u32 d,int realsize)\r
268{\r
269 // sram\r
270 if(a >= SRam.start && a <= SRam.end) {\r
271 elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d, SekPc);\r
272 SRAMWrite(a, d);\r
273 return;\r
274 }\r
275\r
276#ifdef _ASM_MEMORY_C\r
277 // special ROM hardware (currently only banking and sram reg supported)\r
278 if((a&0xfffff1) == 0xA130F1) {\r
279 PicoWriteRomHW_SSF2(a, d); // SSF2 or SRAM\r
280 return;\r
281 }\r
282#else\r
283 // sram access register\r
284 if(a == 0xA130F1) {\r
285 elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
286 Pico.m.sram_reg &= ~3;\r
287 Pico.m.sram_reg |= (u8)(d&3);\r
288 return;\r
289 }\r
290#endif\r
291 elprintf(EL_UIO, "strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
292\r
293 if(a >= 0xA13004 && a < 0xA13040) {\r
294 // dumb 12-in-1 or 4-in-1 banking support\r
295 int len;\r
296 a &= 0x3f; a <<= 16;\r
297 len = Pico.romsize - a;\r
298 if (len <= 0) return; // invalid/missing bank\r
299 if (len > 0x200000) len = 0x200000; // 2 megs\r
300 memcpy(Pico.rom, Pico.rom+a, len); // code which does this is in RAM so this is safe.\r
301 return;\r
302 }\r
303\r
304 // for games with simple protection devices, discovered by Haze\r
305 else if ((a>>22) == 1)\r
306 Pico.m.prot_bytes[(a>>2)&1] = (u8)d;\r
307}\r
308\r
309\r
310#include "MemoryCmn.c"\r
311\r
312\r
313// -----------------------------------------------------------------\r
314// Read Rom and read Ram\r
315\r
316#ifndef _ASM_MEMORY_C\r
317PICO_INTERNAL_ASM u32 PicoRead8(u32 a)\r
318{\r
319 u32 d=0;\r
320\r
321 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram\r
322\r
323 a&=0xffffff;\r
324\r
325#ifndef EMU_CORE_DEBUG\r
326 // sram\r
327 if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
328 d = SRAMRead(a);\r
329 elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
330 goto end;\r
331 }\r
332#endif\r
333\r
334 if (a<Pico.romsize) { d = *(u8 *)(Pico.rom+(a^1)); goto end; } // Rom\r
335 log_io(a, 8, 0);\r
336 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r
337\r
338 d=OtherRead16(a&~1, 8); if ((a&1)==0) d>>=8;\r
339\r
340end:\r
341#ifdef __debug_io\r
342 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
343#endif\r
344#ifdef EMU_CORE_DEBUG\r
345 if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
346 lastread_a = a;\r
347 lastread_d[lrp_cyc++&15] = (u8)d;\r
348 }\r
349#endif\r
350 return d;\r
351}\r
352\r
353PICO_INTERNAL_ASM u32 PicoRead16(u32 a)\r
354{\r
355 u32 d=0;\r
356\r
357 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram\r
358\r
359 a&=0xfffffe;\r
360\r
361#ifndef EMU_CORE_DEBUG\r
362 // sram\r
363 if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
364 d = SRAMRead(a);\r
365 d |= d<<8;\r
366 elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
367 goto end;\r
368 }\r
369#endif\r
370\r
371 if (a<Pico.romsize) { d = *(u16 *)(Pico.rom+a); goto end; } // Rom\r
372 log_io(a, 16, 0);\r
373\r
374 d = OtherRead16(a, 16);\r
375\r
376end:\r
377#ifdef __debug_io\r
378 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
379#endif\r
380#ifdef EMU_CORE_DEBUG\r
381 if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
382 lastread_a = a;\r
383 lastread_d[lrp_cyc++&15] = d;\r
384 }\r
385#endif\r
386 return d;\r
387}\r
388\r
389PICO_INTERNAL_ASM u32 PicoRead32(u32 a)\r
390{\r
391 u32 d=0;\r
392\r
393 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram\r
394\r
395 a&=0xfffffe;\r
396\r
397 // sram\r
398 if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
399 d = (SRAMRead(a)<<16)|SRAMRead(a+2);\r
400 d |= d<<8;\r
401 elprintf(EL_SRAMIO, "sram r32 [%06x] %08x @ %06x", a, d, SekPc);\r
402 goto end;\r
403 }\r
404\r
405 if (a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+a); d = (pm[0]<<16)|pm[1]; goto end; } // Rom\r
406 log_io(a, 32, 0);\r
407\r
408 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
409\r
410end:\r
411#ifdef __debug_io\r
412 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
413#endif\r
414#ifdef EMU_CORE_DEBUG\r
415 if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
416 lastread_a = a;\r
417 lastread_d[lrp_cyc++&15] = d;\r
418 }\r
419#endif\r
420 return d;\r
421}\r
422#endif\r
423\r
424// -----------------------------------------------------------------\r
425// Write Ram\r
426\r
427#ifndef _ASM_MEMORY_C\r
428PICO_INTERNAL_ASM void PicoWrite8(u32 a,u8 d)\r
429{\r
430#ifdef __debug_io\r
431 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
432#endif\r
433#ifdef EMU_CORE_DEBUG\r
434 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
435#endif\r
436\r
437 if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram\r
438 log_io(a, 8, 1);\r
439\r
440 a&=0xffffff;\r
441 OtherWrite8(a,d);\r
442}\r
443#endif\r
444\r
445void PicoWrite16(u32 a,u16 d)\r
446{\r
447#ifdef __debug_io\r
448 dprintf("w16: %06x, %04x", a&0xffffff, d);\r
449#endif\r
450#ifdef EMU_CORE_DEBUG\r
451 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
452#endif\r
453\r
454 if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram\r
455 log_io(a, 16, 1);\r
456\r
457 a&=0xfffffe;\r
458 OtherWrite16(a,d);\r
459}\r
460\r
461static void PicoWrite32(u32 a,u32 d)\r
462{\r
463#ifdef __debug_io\r
464 dprintf("w32: %06x, %08x", a&0xffffff, d);\r
465#endif\r
466#ifdef EMU_CORE_DEBUG\r
467 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
468#endif\r
469\r
470 if ((a&0xe00000)==0xe00000)\r
471 {\r
472 // Ram:\r
473 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r
474 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
475 return;\r
476 }\r
477 log_io(a, 32, 1);\r
478\r
479 a&=0xfffffe;\r
480 OtherWrite16(a, (u16)(d>>16));\r
481 OtherWrite16(a+2,(u16)d);\r
482}\r
483\r
484\r
485// -----------------------------------------------------------------\r
486PICO_INTERNAL void PicoMemSetup(void)\r
487{\r
488 // Setup memory callbacks:\r
489#ifdef EMU_C68K\r
490 PicoCpuCM68k.checkpc=PicoCheckPc;\r
491 PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoRead8;\r
492 PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoRead16;\r
493 PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoRead32;\r
494 PicoCpuCM68k.write8 =PicoWrite8;\r
495 PicoCpuCM68k.write16=PicoWrite16;\r
496 PicoCpuCM68k.write32=PicoWrite32;\r
497#endif\r
498#ifdef EMU_F68K\r
499 PicoCpuFM68k.read_byte =PicoRead8;\r
500 PicoCpuFM68k.read_word =PicoRead16;\r
501 PicoCpuFM68k.read_long =PicoRead32;\r
502 PicoCpuFM68k.write_byte=PicoWrite8;\r
503 PicoCpuFM68k.write_word=PicoWrite16;\r
504 PicoCpuFM68k.write_long=PicoWrite32;\r
505\r
506 // setup FAME fetchmap\r
507 {\r
508 int i;\r
509 // by default, point everything to fitst 64k of ROM\r
510 for (i = 0; i < M68K_FETCHBANK1; i++)\r
511 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
512 // now real ROM\r
513 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
514 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;\r
515 // .. and RAM\r
516 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
517 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
518 }\r
519#endif\r
520}\r
521\r
522\r
523#ifdef EMU_M68K\r
524unsigned int m68k_read_pcrelative_CD8 (unsigned int a);\r
525unsigned int m68k_read_pcrelative_CD16(unsigned int a);\r
526unsigned int m68k_read_pcrelative_CD32(unsigned int a);\r
527\r
528// these are allowed to access RAM\r
529static unsigned int m68k_read_8 (unsigned int a, int do_fake) {\r
530 a&=0xffffff;\r
531 if(PicoMCD&1) return m68k_read_pcrelative_CD8(a);\r
532 if(a<Pico.romsize) return *(u8 *)(Pico.rom+(a^1)); // Rom\r
533#ifdef EMU_CORE_DEBUG\r
534 if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
535#endif\r
536 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
537 return 0;\r
538}\r
539static unsigned int m68k_read_16(unsigned int a, int do_fake) {\r
540 a&=0xffffff;\r
541 if(PicoMCD&1) return m68k_read_pcrelative_CD16(a);\r
542 if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
543#ifdef EMU_CORE_DEBUG\r
544 if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
545#endif\r
546 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
547 return 0;\r
548}\r
549static unsigned int m68k_read_32(unsigned int a, int do_fake) {\r
550 a&=0xffffff;\r
551 if(PicoMCD&1) return m68k_read_pcrelative_CD32(a);\r
552 if(a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
553#ifdef EMU_CORE_DEBUG\r
554 if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
555#endif\r
556 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
557 return 0;\r
558}\r
559\r
560unsigned int m68k_read_pcrelative_8 (unsigned int a) { return m68k_read_8 (a, 1); }\r
561unsigned int m68k_read_pcrelative_16(unsigned int a) { return m68k_read_16(a, 1); }\r
562unsigned int m68k_read_pcrelative_32(unsigned int a) { return m68k_read_32(a, 1); }\r
563unsigned int m68k_read_immediate_16(unsigned int a) { return m68k_read_16(a, 0); }\r
564unsigned int m68k_read_immediate_32(unsigned int a) { return m68k_read_32(a, 0); }\r
565unsigned int m68k_read_disassembler_8 (unsigned int a) { return m68k_read_8 (a, 0); }\r
566unsigned int m68k_read_disassembler_16(unsigned int a) { return m68k_read_16(a, 0); }\r
567unsigned int m68k_read_disassembler_32(unsigned int a) { return m68k_read_32(a, 0); }\r
568\r
569#ifdef EMU_CORE_DEBUG\r
570// ROM only\r
571unsigned int m68k_read_memory_8(unsigned int a)\r
572{\r
573 u8 d;\r
574 if(a<Pico.romsize) d = *(u8 *) (Pico.rom+(a^1));\r
575 else d = (u8) lastread_d[lrp_mus++&15];\r
576#ifdef __debug_io\r
577 dprintf("r8_mu : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
578#endif\r
579 return d;\r
580}\r
581unsigned int m68k_read_memory_16(unsigned int a)\r
582{\r
583 u16 d;\r
584 if(a<Pico.romsize) d = *(u16 *)(Pico.rom+(a&~1));\r
585 else d = (u16) lastread_d[lrp_mus++&15];\r
586#ifdef __debug_io\r
587 dprintf("r16_mu: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
588#endif\r
589 return d;\r
590}\r
591unsigned int m68k_read_memory_32(unsigned int a)\r
592{\r
593 u32 d;\r
594 if(a<Pico.romsize) {u16 *pm=(u16 *)(Pico.rom+(a&~1));d=(pm[0]<<16)|pm[1];}\r
595 else d = lastread_d[lrp_mus++&15];\r
596#ifdef __debug_io\r
597 dprintf("r32_mu: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
598#endif\r
599 return d;\r
600}\r
601\r
602// ignore writes, Cyclone already done that\r
603void m68k_write_memory_8(unsigned int address, unsigned int value) { lastwrite_mus_d[lwp_mus++&15] = value; }\r
604void m68k_write_memory_16(unsigned int address, unsigned int value) { lastwrite_mus_d[lwp_mus++&15] = value; }\r
605void m68k_write_memory_32(unsigned int address, unsigned int value) { lastwrite_mus_d[lwp_mus++&15] = value; }\r
606#else\r
607unsigned char PicoReadCD8w (unsigned int a);\r
608unsigned short PicoReadCD16w(unsigned int a);\r
609unsigned int PicoReadCD32w(unsigned int a);\r
610void PicoWriteCD8w (unsigned int a, unsigned char d);\r
611void PicoWriteCD16w(unsigned int a, unsigned short d);\r
612void PicoWriteCD32w(unsigned int a, unsigned int d);\r
613\r
614/* it appears that Musashi doesn't always mask the unused bits */\r
615unsigned int m68k_read_memory_8(unsigned int address)\r
616{\r
617 unsigned int d = (PicoMCD&1) ? PicoReadCD8w(address) : PicoRead8(address);\r
618 return d&0xff;\r
619}\r
620\r
621unsigned int m68k_read_memory_16(unsigned int address)\r
622{\r
623 unsigned int d = (PicoMCD&1) ? PicoReadCD16w(address) : PicoRead16(address);\r
624 return d&0xffff;\r
625}\r
626\r
627unsigned int m68k_read_memory_32(unsigned int address)\r
628{\r
629 return (PicoMCD&1) ? PicoReadCD32w(address) : PicoRead32(address);\r
630}\r
631\r
632void m68k_write_memory_8(unsigned int address, unsigned int value)\r
633{\r
634 if (PicoMCD&1) PicoWriteCD8w(address, (u8)value); else PicoWrite8(address, (u8)value);\r
635}\r
636\r
637void m68k_write_memory_16(unsigned int address, unsigned int value)\r
638{\r
639 if (PicoMCD&1) PicoWriteCD16w(address,(u16)value); else PicoWrite16(address,(u16)value);\r
640}\r
641\r
642void m68k_write_memory_32(unsigned int address, unsigned int value)\r
643{\r
644 if (PicoMCD&1) PicoWriteCD32w(address, value); else PicoWrite32(address, value);\r
645}\r
646#endif\r
647#endif // EMU_M68K\r
648\r
649\r
650// -----------------------------------------------------------------\r
651// z80 memhandlers\r
652\r
653PICO_INTERNAL unsigned char z80_read(unsigned short a)\r
654{\r
655 u8 ret = 0;\r
656\r
657#ifndef _USE_DRZ80\r
658 if (a<0x4000) return Pico.zram[a&0x1fff];\r
659#endif\r
660\r
661 if ((a>>13)==2) // 0x4000-0x5fff (Charles MacDonald)\r
662 {\r
663 if (PicoOpt&1) ret = (u8) YM2612Read();\r
664 return ret;\r
665 }\r
666\r
667 if (a>=0x8000)\r
668 {\r
669 u32 addr68k;\r
670 addr68k=Pico.m.z80_bank68k<<15;\r
671 addr68k+=a&0x7fff;\r
672\r
673 ret = (u8) PicoRead8(addr68k);\r
674 elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
675 return ret;\r
676 }\r
677\r
678#ifdef _USE_DRZ80\r
679 // should not be needed || dprintf("z80_read RAM");\r
680 if (a<0x4000) return Pico.zram[a&0x1fff];\r
681#endif\r
682\r
683 elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, ret);\r
684 return ret;\r
685}\r
686\r
687#ifndef _USE_CZ80\r
688PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a)\r
689#else\r
690PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data)\r
691#endif\r
692{\r
693#ifndef _USE_DRZ80\r
694 if (a<0x4000) { Pico.zram[a&0x1fff]=data; return; }\r
695#endif\r
696\r
697 if ((a>>13)==2) // 0x4000-0x5fff (Charles MacDonald)\r
698 {\r
699 if(PicoOpt&1) emustatus|=YM2612Write(a, data) & 1;\r
700 return;\r
701 }\r
702\r
703 if ((a&0xfff9)==0x7f11) // 7f11 7f13 7f15 7f17\r
704 {\r
705 if(PicoOpt&2) SN76496Write(data);\r
706 return;\r
707 }\r
708\r
709 if ((a>>8)==0x60)\r
710 {\r
711 Pico.m.z80_bank68k>>=1;\r
712 Pico.m.z80_bank68k|=(data&1)<<8;\r
713 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one\r
714 return;\r
715 }\r
716\r
717 if (a>=0x8000)\r
718 {\r
719 u32 addr68k;\r
720 addr68k=Pico.m.z80_bank68k<<15;\r
721 addr68k+=a&0x7fff;\r
722 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
723 PicoWrite8(addr68k, data);\r
724 return;\r
725 }\r
726\r
727#ifdef _USE_DRZ80\r
728 // should not be needed, drZ80 knows how to access RAM itself || dprintf("z80_write RAM @ %08x", lr);\r
729 if (a<0x4000) { Pico.zram[a&0x1fff]=data; return; }\r
730#endif\r
731\r
732 elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
733}\r
734\r
735#ifndef _USE_CZ80\r
736PICO_INTERNAL unsigned short z80_read16(unsigned short a)\r
737{\r
738 return (u16) ( (u16)z80_read(a) | ((u16)z80_read((u16)(a+1))<<8) );\r
739}\r
740\r
741PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a)\r
742{\r
743 z80_write((unsigned char) data,a);\r
744 z80_write((unsigned char)(data>>8),(u16)(a+1));\r
745}\r
746#endif\r
747\r