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frontend: update libpicofe, fix missed callbacks
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c
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1/*
2 * (C) GraÅžvydas "notaz" Ignotas, 2010-2011
3 *
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
6 */
7
8#include <stdio.h>
9#include "../psxhw.h"
10#include "../cdrom.h"
11#include "../mdec.h"
12#include "../gpu.h"
13#include "../psxmem_map.h"
14#include "emu_if.h"
15#include "pcsxmem.h"
16
17#ifdef __thumb__
18#error the dynarec is incompatible with Thumb functions,
19#error please add -marm to compile flags
20#endif
21
22//#define memprintf printf
23#define memprintf(...)
24
25static uintptr_t *mem_readtab;
26static uintptr_t *mem_writetab;
27static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
28static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
29static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4];
30static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
31//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
32static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
33
34static
35#ifdef __clang__
36// When this is called in a loop, and 'h' is a function pointer, clang will crash.
37__attribute__ ((noinline))
38#endif
39void map_item(uintptr_t *out, const void *h, uintptr_t flag)
40{
41 uintptr_t hv = (uintptr_t)h;
42 if (hv & 1) {
43 SysPrintf("FATAL: %p has LSB set\n", h);
44 abort();
45 }
46 *out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1));
47}
48
49// size must be power of 2, at least 4k
50#define map_l1_mem(tab, i, addr, size, base) \
51 map_item(&tab[((u32)(addr) >> 12) + i], \
52 (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)
53
54#define IOMEM32(a) (((a) & 0xfff) / 4)
55#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
56#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
57
58u32 zero_mem[0x1000/4];
59static u32 ffff_mem[0x1000/4];
60
61static u32 read_mem_dummy(u32 addr)
62{
63 // use 'addr' and not 'address', yes the api is weird...
64 memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle);
65 return 0xffffffff;
66}
67
68static void write_mem_dummy(u32 data)
69{
70 if (!(psxRegs.CP0.n.SR & (1 << 16)))
71 memprintf("unmapped w %08x, %08x @%08x %u\n",
72 address, data, psxRegs.pc, psxRegs.cycle);
73}
74
75/* IO handlers */
76static u32 io_read_sio16()
77{
78 return sioRead8();
79}
80
81static u32 io_read_sio32()
82{
83 return sioRead8();
84}
85
86static void io_write_sio16(u32 value)
87{
88 sioWrite8(value);
89}
90
91static void io_write_sio32(u32 value)
92{
93 sioWrite8(value);
94}
95
96#if !defined(DRC_DBG) && defined(__arm__)
97
98static void map_rcnt_rcount0(u32 mode)
99{
100 if (mode & 0x001) { // sync mode
101 map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
102 map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
103 }
104 else if (mode & 0x100) { // pixel clock
105 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
106 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
107 }
108 else {
109 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
110 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
111 }
112}
113
114static void map_rcnt_rcount1(u32 mode)
115{
116 if (mode & 0x001) { // sync mode
117 map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
118 map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
119 }
120 else if (mode & 0x100) { // hcnt
121 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
122 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
123 }
124 else {
125 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
126 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
127 }
128}
129
130static void map_rcnt_rcount2(u32 mode)
131{
132 if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode
133 map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
134 map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
135 }
136 else if (mode & 0x200) { // clk/8
137 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
138 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
139 }
140 else {
141 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
142 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
143 }
144}
145
146#else
147#define map_rcnt_rcount0(mode)
148#define map_rcnt_rcount1(mode)
149#define map_rcnt_rcount2(mode)
150#endif
151
152#define make_rcnt_funcs(i) \
153static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
154static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
155static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
156static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
157static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
158
159make_rcnt_funcs(0)
160make_rcnt_funcs(1)
161make_rcnt_funcs(2)
162
163static u32 io_spu_read8_even(u32 addr)
164{
165 return SPU_readRegister(addr, psxRegs.cycle) & 0xff;
166}
167
168static u32 io_spu_read8_odd(u32 addr)
169{
170 return SPU_readRegister(addr, psxRegs.cycle) >> 8;
171}
172
173static u32 io_spu_read16(u32 addr)
174{
175 return SPU_readRegister(addr, psxRegs.cycle);
176}
177
178static u32 io_spu_read32(u32 addr)
179{
180 u32 ret;
181 ret = SPU_readRegister(addr, psxRegs.cycle);
182 ret |= SPU_readRegister(addr + 2, psxRegs.cycle) << 16;
183 return ret;
184}
185
186static void io_spu_write16(u32 value)
187{
188 // meh
189 SPU_writeRegister(address, value, psxRegs.cycle);
190}
191
192static void io_spu_write32(u32 value)
193{
194 SPUwriteRegister wfunc = SPU_writeRegister;
195 u32 a = address;
196
197 wfunc(a, value & 0xffff, psxRegs.cycle);
198 wfunc(a + 2, value >> 16, psxRegs.cycle);
199}
200
201void new_dyna_pcsx_mem_isolate(int enable)
202{
203 int i;
204
205 // note: apparently 0xa0000000 uncached access still works,
206 // at least read does for sure, so assume write does too
207 memprintf("mem isolate %d\n", enable);
208 if (enable) {
209 for (i = 0; i < (0x800000 >> 12); i++) {
210 map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
211 map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
212 //map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
213 }
214 }
215 else {
216 for (i = 0; i < (0x800000 >> 12); i++) {
217 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
218 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
219 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
220 }
221 }
222}
223
224static u32 read_biu(u32 addr)
225{
226 if (addr != 0xfffe0130)
227 return read_mem_dummy(addr);
228
229 memprintf("read_biu %08x @%08x %u\n",
230 psxRegs.biuReg, psxRegs.pc, psxRegs.cycle);
231 return psxRegs.biuReg;
232}
233
234static void write_biu(u32 value)
235{
236 if (address != 0xfffe0130) {
237 write_mem_dummy(value);
238 return;
239 }
240
241 memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
242 psxRegs.biuReg = value;
243}
244
245/* scph7001 (pc = 8003de60, v1 = 1f8010f0):
246 lhu $t9, 0($v1)
247 li $at, 0xFFF0FFFF
248 and $t0, $t9, $at
249 lui $at, 8
250 or $t1, $t0, $at
251 sh $t1, 0($v1)
252*/
253#define make_forcew32_func(addr) \
254static void io_write_force32_##addr(u32 value) \
255{ \
256 psxHu32ref(0x##addr) = SWAPu32(value); \
257}
258make_forcew32_func(1014)
259make_forcew32_func(1060)
260make_forcew32_func(1080)
261make_forcew32_func(1090)
262make_forcew32_func(10a0)
263make_forcew32_func(10b0)
264make_forcew32_func(10c0)
265make_forcew32_func(10e0)
266
267void new_dyna_pcsx_mem_load_state(void)
268{
269 map_rcnt_rcount0(rcnts[0].mode);
270 map_rcnt_rcount1(rcnts[1].mode);
271 map_rcnt_rcount2(rcnts[2].mode);
272}
273
274int pcsxmem_is_handler_dynamic(unsigned int addr)
275{
276 if ((addr & 0xfffff000) != 0x1f801000)
277 return 0;
278
279 addr &= 0xffff;
280 return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
281}
282
283void new_dyna_pcsx_mem_init(void)
284{
285 int i;
286
287 memset(ffff_mem, 0xff, sizeof(ffff_mem));
288
289 // have to map these further to keep tcache close to .text
290 mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
291 if (mem_readtab == NULL) {
292 SysPrintf("failed to map mem tables\n");
293 exit(1);
294 }
295 mem_writetab = mem_readtab + 0x100000;
296
297 // 1st level lookup:
298 // 0: direct mem
299 // 1: use 2nd lookup
300 // 2nd level lookup:
301 // 0: direct mem variable
302 // 1: memhandler
303
304 // default/unmapped memhandlers
305 for (i = 0; i < 0x100000; i++) {
306 //map_item(&mem_readtab[i], mem_unmrtab, 1);
307 map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem);
308 map_item(&mem_writetab[i], mem_unmwtab, 1);
309 }
310
311 // RAM and it's mirrors
312 for (i = 0; i < (0x800000 >> 12); i++) {
313 map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
314 map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
315 map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
316 }
317 new_dyna_pcsx_mem_isolate(0);
318
319 // BIOS and it's mirrors
320 for (i = 0; i < (0x80000 >> 12); i++) {
321 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
322 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
323 }
324
325 // scratchpad
326 map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
327 map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
328 map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
329 map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
330
331 // I/O
332 map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1);
333 map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1);
334 map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1);
335 map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1);
336 map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1);
337 map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1);
338
339 // L2
340 // unmapped tables
341 for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
342 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
343
344 // fill IO tables
345 for (i = 0; i < 0x1000/4; i++) {
346 map_item(&mem_iortab[i], &psxH[0x1000], 0);
347 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
348 }
349 for (; i < 0x1000/4 + 0x1000/2; i++) {
350 map_item(&mem_iortab[i], &psxH[0x1000], 0);
351 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
352 }
353 for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
354 map_item(&mem_iortab[i], &psxH[0x1000], 0);
355 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
356 }
357
358 map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
359 map_item(&mem_iortab[IOMEM32(0x1044)], sioReadStat16, 1);
360 map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
361 map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
362 map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
363 map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
364 map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
365 map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
366 map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1);
367 map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
368 map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
369// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
370 map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSR, 1);
371 map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
372 map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
373
374 map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
375 map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
376 map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
377 map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
378 map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
379 map_item(&mem_iortab[IOMEM16(0x1054)], sio1ReadStat16, 1);
380 map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
381 map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
382 map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
383 map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
384 map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
385 map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
386 map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1);
387 map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
388 map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
389
390 map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
391 map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
392 map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
393 map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
394 map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
395
396 for (i = 0x1c00; i < 0x2000; i += 2) {
397 map_item(&mem_iortab[IOMEM8(i)], io_spu_read8_even, 1);
398 map_item(&mem_iortab[IOMEM8(i+1)], io_spu_read8_odd, 1);
399 map_item(&mem_iortab[IOMEM16(i)], io_spu_read16, 1);
400 map_item(&mem_iortab[IOMEM32(i)], io_spu_read32, 1);
401 }
402
403 // write(u32 data)
404 map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
405 map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1);
406 map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1);
407 map_item(&mem_iowtab[IOMEM32(0x1088)], psxHwWriteChcr0, 1);
408 map_item(&mem_iowtab[IOMEM32(0x108c)], psxHwWriteChcr0, 1);
409 map_item(&mem_iowtab[IOMEM32(0x1098)], psxHwWriteChcr1, 1);
410 map_item(&mem_iowtab[IOMEM32(0x109c)], psxHwWriteChcr1, 1);
411 map_item(&mem_iowtab[IOMEM32(0x10a8)], psxHwWriteChcr2, 1);
412 map_item(&mem_iowtab[IOMEM32(0x10ac)], psxHwWriteChcr2, 1);
413 map_item(&mem_iowtab[IOMEM32(0x10b8)], psxHwWriteChcr3, 1);
414 map_item(&mem_iowtab[IOMEM32(0x10bc)], psxHwWriteChcr3, 1);
415 map_item(&mem_iowtab[IOMEM32(0x10c8)], psxHwWriteChcr4, 1);
416 map_item(&mem_iowtab[IOMEM32(0x10cc)], psxHwWriteChcr4, 1);
417 map_item(&mem_iowtab[IOMEM32(0x10e8)], psxHwWriteChcr6, 1);
418 map_item(&mem_iowtab[IOMEM32(0x10ec)], psxHwWriteChcr6, 1);
419 map_item(&mem_iowtab[IOMEM32(0x10f0)], psxHwWriteDmaPcr32, 1);
420 map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1);
421 map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
422 map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
423 map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
424 map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
425 map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
426 map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
427 map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
428 map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
429 map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
430// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
431 map_item(&mem_iowtab[IOMEM32(0x1814)], psxHwWriteGpuSR, 1);
432 map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
433 map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
434
435 map_item(&mem_iowtab[IOMEM16(0x1014)], io_write_force32_1014, 1);
436 map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
437 map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
438 map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
439 map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
440 map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
441 map_item(&mem_iowtab[IOMEM16(0x1060)], io_write_force32_1060, 1);
442 map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1);
443 map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1);
444 map_item(&mem_iowtab[IOMEM16(0x1080)], io_write_force32_1080, 1);
445 map_item(&mem_iowtab[IOMEM16(0x1088)], psxHwWriteChcr0, 1);
446 map_item(&mem_iowtab[IOMEM16(0x108c)], psxHwWriteChcr0, 1);
447 map_item(&mem_iowtab[IOMEM16(0x1090)], io_write_force32_1090, 1);
448 map_item(&mem_iowtab[IOMEM16(0x1098)], psxHwWriteChcr1, 1);
449 map_item(&mem_iowtab[IOMEM16(0x109c)], psxHwWriteChcr1, 1);
450 map_item(&mem_iowtab[IOMEM16(0x10a0)], io_write_force32_10a0, 1);
451 map_item(&mem_iowtab[IOMEM16(0x10a8)], psxHwWriteChcr2, 1);
452 map_item(&mem_iowtab[IOMEM16(0x10ac)], psxHwWriteChcr2, 1);
453 map_item(&mem_iowtab[IOMEM16(0x10b0)], io_write_force32_10b0, 1);
454 map_item(&mem_iowtab[IOMEM16(0x10b8)], psxHwWriteChcr3, 1);
455 map_item(&mem_iowtab[IOMEM16(0x10bc)], psxHwWriteChcr3, 1);
456 map_item(&mem_iowtab[IOMEM16(0x10c0)], io_write_force32_10c0, 1);
457 map_item(&mem_iowtab[IOMEM16(0x10c8)], psxHwWriteChcr4, 1);
458 map_item(&mem_iowtab[IOMEM16(0x10cc)], psxHwWriteChcr4, 1);
459 map_item(&mem_iowtab[IOMEM16(0x10e0)], io_write_force32_10e0, 1);
460 map_item(&mem_iowtab[IOMEM16(0x10e8)], psxHwWriteChcr6, 1);
461 map_item(&mem_iowtab[IOMEM16(0x10ec)], psxHwWriteChcr6, 1);
462 map_item(&mem_iowtab[IOMEM16(0x10f0)], psxHwWriteDmaPcr32, 1);
463 map_item(&mem_iowtab[IOMEM16(0x10f4)], psxHwWriteDmaIcr32, 1);
464 map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
465 map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
466 map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
467 map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
468 map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
469 map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
470 map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
471 map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
472 map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
473
474 map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
475 map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
476 map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
477 map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
478 map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
479
480 for (i = 0x1c00; i < 0x2000; i += 2) {
481 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
482 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
483 }
484
485 // misc
486 map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1);
487 map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1);
488 for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
489 map_item(&mem_ffrtab[i], read_biu, 1);
490 map_item(&mem_ffwtab[i], write_biu, 1);
491 }
492
493 mem_rtab = mem_readtab;
494 mem_wtab = mem_writetab;
495
496 new_dyna_pcsx_mem_load_state();
497}
498
499void new_dyna_pcsx_mem_reset(void)
500{
501 // plugins might change so update the pointers
502 map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
503 map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
504}
505
506void new_dyna_pcsx_mem_shutdown(void)
507{
508 psxUnmap(mem_readtab, 0x200000 * sizeof(mem_readtab[0]), MAP_TAG_LUTS);
509 mem_writetab = mem_readtab = NULL;
510}
ARM optimized PCSX fork