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cdrom: change pause timing again
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c
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CommitLineData
1/*
2 * (C) GraÅžvydas "notaz" Ignotas, 2010-2011
3 *
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
6 */
7
8#include <stdio.h>
9#include "../psxhw.h"
10#include "../cdrom.h"
11#include "../mdec.h"
12#include "../gpu.h"
13#include "../psxmem_map.h"
14#include "emu_if.h"
15#include "pcsxmem.h"
16
17#ifdef __thumb__
18#error the dynarec is incompatible with Thumb functions,
19#error please add -marm to compile flags
20#endif
21
22//#define memprintf printf
23#define memprintf(...)
24
25static uintptr_t *mem_readtab;
26static uintptr_t *mem_writetab;
27static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
28static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
29static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4];
30static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
31//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
32static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
33
34static
35#ifdef __clang__
36// When this is called in a loop, and 'h' is a function pointer, clang will crash.
37__attribute__ ((noinline))
38#endif
39void map_item(uintptr_t *out, const void *h, uintptr_t flag)
40{
41 uintptr_t hv = (uintptr_t)h;
42 if (hv & 1) {
43 SysPrintf("FATAL: %p has LSB set\n", h);
44 abort();
45 }
46 *out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1));
47}
48
49// size must be power of 2, at least 4k
50#define map_l1_mem(tab, i, addr, size, base) \
51 map_item(&tab[((u32)(addr) >> 12) + i], \
52 (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)
53
54#define IOMEM32(a) (((a) & 0xfff) / 4)
55#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
56#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
57
58u32 zero_mem[0x1000/4];
59static u32 ffff_mem[0x1000/4];
60
61static u32 read_mem_dummy(u32 addr)
62{
63 // use 'addr' and not 'address', yes the api is weird...
64 memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle);
65 return 0xffffffff;
66}
67
68static void write_mem_dummy(u32 data)
69{
70 if (!(psxRegs.CP0.n.SR & (1 << 16)))
71 memprintf("unmapped w %08x, %08x @%08x %u\n",
72 address, data, psxRegs.pc, psxRegs.cycle);
73}
74
75/* IO handlers */
76static u32 io_read_sio16()
77{
78 return sioRead8();
79}
80
81static u32 io_read_sio32()
82{
83 return sioRead8();
84}
85
86static void io_write_sio16(u32 value)
87{
88 sioWrite8((unsigned char)value);
89 sioWrite8((unsigned char)(value>>8));
90}
91
92static void io_write_sio32(u32 value)
93{
94 sioWrite8((unsigned char)value);
95 sioWrite8((unsigned char)(value >> 8));
96 sioWrite8((unsigned char)(value >> 16));
97 sioWrite8((unsigned char)(value >> 24));
98}
99
100#if !defined(DRC_DBG) && defined(__arm__)
101
102static void map_rcnt_rcount0(u32 mode)
103{
104 if (mode & 0x001) { // sync mode
105 map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
106 map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
107 }
108 else if (mode & 0x100) { // pixel clock
109 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
110 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
111 }
112 else {
113 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
114 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
115 }
116}
117
118static void map_rcnt_rcount1(u32 mode)
119{
120 if (mode & 0x001) { // sync mode
121 map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
122 map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
123 }
124 else if (mode & 0x100) { // hcnt
125 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
126 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
127 }
128 else {
129 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
130 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
131 }
132}
133
134static void map_rcnt_rcount2(u32 mode)
135{
136 if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode
137 map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
138 map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
139 }
140 else if (mode & 0x200) { // clk/8
141 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
142 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
143 }
144 else {
145 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
146 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
147 }
148}
149
150#else
151#define map_rcnt_rcount0(mode)
152#define map_rcnt_rcount1(mode)
153#define map_rcnt_rcount2(mode)
154#endif
155
156#define make_rcnt_funcs(i) \
157static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
158static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
159static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
160static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
161static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
162
163make_rcnt_funcs(0)
164make_rcnt_funcs(1)
165make_rcnt_funcs(2)
166
167static u32 io_spu_read8_even(u32 addr)
168{
169 return SPU_readRegister(addr, psxRegs.cycle) & 0xff;
170}
171
172static u32 io_spu_read8_odd(u32 addr)
173{
174 return SPU_readRegister(addr, psxRegs.cycle) >> 8;
175}
176
177static u32 io_spu_read16(u32 addr)
178{
179 return SPU_readRegister(addr, psxRegs.cycle);
180}
181
182static u32 io_spu_read32(u32 addr)
183{
184 u32 ret;
185 ret = SPU_readRegister(addr, psxRegs.cycle);
186 ret |= SPU_readRegister(addr + 2, psxRegs.cycle) << 16;
187 return ret;
188}
189
190static void io_spu_write16(u32 value)
191{
192 // meh
193 SPU_writeRegister(address, value, psxRegs.cycle);
194}
195
196static void io_spu_write32(u32 value)
197{
198 SPUwriteRegister wfunc = SPU_writeRegister;
199 u32 a = address;
200
201 wfunc(a, value & 0xffff, psxRegs.cycle);
202 wfunc(a + 2, value >> 16, psxRegs.cycle);
203}
204
205void new_dyna_pcsx_mem_isolate(int enable)
206{
207 int i;
208
209 // note: apparently 0xa0000000 uncached access still works,
210 // at least read does for sure, so assume write does too
211 memprintf("mem isolate %d\n", enable);
212 if (enable) {
213 for (i = 0; i < (0x800000 >> 12); i++) {
214 map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
215 map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
216 //map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
217 }
218 }
219 else {
220 for (i = 0; i < (0x800000 >> 12); i++) {
221 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
222 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
223 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
224 }
225 }
226}
227
228static u32 read_biu(u32 addr)
229{
230 if (addr != 0xfffe0130)
231 return read_mem_dummy(addr);
232
233 memprintf("read_biu %08x @%08x %u\n",
234 psxRegs.biuReg, psxRegs.pc, psxRegs.cycle);
235 return psxRegs.biuReg;
236}
237
238static void write_biu(u32 value)
239{
240 if (address != 0xfffe0130) {
241 write_mem_dummy(value);
242 return;
243 }
244
245 memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
246 psxRegs.biuReg = value;
247}
248
249/* scph7001 (pc = 8003de60, v1 = 1f8010f0):
250 lhu $t9, 0($v1)
251 li $at, 0xFFF0FFFF
252 and $t0, $t9, $at
253 lui $at, 8
254 or $t1, $t0, $at
255 sh $t1, 0($v1)
256*/
257#define make_forcew32_func(addr) \
258static void io_write_force32_##addr(u32 value) \
259{ \
260 psxHu32ref(0x##addr) = SWAPu32(value); \
261}
262make_forcew32_func(1014)
263make_forcew32_func(1060)
264make_forcew32_func(1080)
265make_forcew32_func(1090)
266make_forcew32_func(10a0)
267make_forcew32_func(10b0)
268make_forcew32_func(10c0)
269make_forcew32_func(10e0)
270make_forcew32_func(10f0)
271
272void new_dyna_pcsx_mem_load_state(void)
273{
274 map_rcnt_rcount0(rcnts[0].mode);
275 map_rcnt_rcount1(rcnts[1].mode);
276 map_rcnt_rcount2(rcnts[2].mode);
277}
278
279int pcsxmem_is_handler_dynamic(unsigned int addr)
280{
281 if ((addr & 0xfffff000) != 0x1f801000)
282 return 0;
283
284 addr &= 0xffff;
285 return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
286}
287
288void new_dyna_pcsx_mem_init(void)
289{
290 int i;
291
292 memset(ffff_mem, 0xff, sizeof(ffff_mem));
293
294 // have to map these further to keep tcache close to .text
295 mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
296 if (mem_readtab == NULL) {
297 SysPrintf("failed to map mem tables\n");
298 exit(1);
299 }
300 mem_writetab = mem_readtab + 0x100000;
301
302 // 1st level lookup:
303 // 0: direct mem
304 // 1: use 2nd lookup
305 // 2nd level lookup:
306 // 0: direct mem variable
307 // 1: memhandler
308
309 // default/unmapped memhandlers
310 for (i = 0; i < 0x100000; i++) {
311 //map_item(&mem_readtab[i], mem_unmrtab, 1);
312 map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem);
313 map_item(&mem_writetab[i], mem_unmwtab, 1);
314 }
315
316 // RAM and it's mirrors
317 for (i = 0; i < (0x800000 >> 12); i++) {
318 map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
319 map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
320 map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
321 }
322 new_dyna_pcsx_mem_isolate(0);
323
324 // BIOS and it's mirrors
325 for (i = 0; i < (0x80000 >> 12); i++) {
326 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
327 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
328 }
329
330 // scratchpad
331 map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
332 map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
333 map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
334 map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
335
336 // I/O
337 map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1);
338 map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1);
339 map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1);
340 map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1);
341 map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1);
342 map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1);
343
344 // L2
345 // unmapped tables
346 for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
347 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
348
349 // fill IO tables
350 for (i = 0; i < 0x1000/4; i++) {
351 map_item(&mem_iortab[i], &psxH[0x1000], 0);
352 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
353 }
354 for (; i < 0x1000/4 + 0x1000/2; i++) {
355 map_item(&mem_iortab[i], &psxH[0x1000], 0);
356 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
357 }
358 for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
359 map_item(&mem_iortab[i], &psxH[0x1000], 0);
360 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
361 }
362
363 map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
364 map_item(&mem_iortab[IOMEM32(0x1044)], sioReadStat16, 1);
365 map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
366 map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
367 map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
368 map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
369 map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
370 map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
371 map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1);
372 map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
373 map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
374// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
375 map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSR, 1);
376 map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
377 map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
378
379 map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
380 map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
381 map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
382 map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
383 map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
384 map_item(&mem_iortab[IOMEM16(0x1054)], sio1ReadStat16, 1);
385 map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
386 map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
387 map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
388 map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
389 map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
390 map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
391 map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1);
392 map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
393 map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
394
395 map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
396 map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
397 map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
398 map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
399 map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
400
401 for (i = 0x1c00; i < 0x2000; i += 2) {
402 map_item(&mem_iortab[IOMEM8(i)], io_spu_read8_even, 1);
403 map_item(&mem_iortab[IOMEM8(i+1)], io_spu_read8_odd, 1);
404 map_item(&mem_iortab[IOMEM16(i)], io_spu_read16, 1);
405 map_item(&mem_iortab[IOMEM32(i)], io_spu_read32, 1);
406 }
407
408 // write(u32 data)
409 map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
410 map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1);
411 map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1);
412 map_item(&mem_iowtab[IOMEM32(0x1088)], psxHwWriteChcr0, 1);
413 map_item(&mem_iowtab[IOMEM32(0x108c)], psxHwWriteChcr0, 1);
414 map_item(&mem_iowtab[IOMEM32(0x1098)], psxHwWriteChcr1, 1);
415 map_item(&mem_iowtab[IOMEM32(0x109c)], psxHwWriteChcr1, 1);
416 map_item(&mem_iowtab[IOMEM32(0x10a8)], psxHwWriteChcr2, 1);
417 map_item(&mem_iowtab[IOMEM32(0x10ac)], psxHwWriteChcr2, 1);
418 map_item(&mem_iowtab[IOMEM32(0x10b8)], psxHwWriteChcr3, 1);
419 map_item(&mem_iowtab[IOMEM32(0x10bc)], psxHwWriteChcr3, 1);
420 map_item(&mem_iowtab[IOMEM32(0x10c8)], psxHwWriteChcr4, 1);
421 map_item(&mem_iowtab[IOMEM32(0x10cc)], psxHwWriteChcr4, 1);
422 map_item(&mem_iowtab[IOMEM32(0x10e8)], psxHwWriteChcr6, 1);
423 map_item(&mem_iowtab[IOMEM32(0x10ec)], psxHwWriteChcr6, 1);
424 map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1);
425 map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
426 map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
427 map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
428 map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
429 map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
430 map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
431 map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
432 map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
433 map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
434// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
435 map_item(&mem_iowtab[IOMEM32(0x1814)], psxHwWriteGpuSR, 1);
436 map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
437 map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
438
439 map_item(&mem_iowtab[IOMEM16(0x1014)], io_write_force32_1014, 1);
440 map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
441 map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
442 map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
443 map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
444 map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
445 map_item(&mem_iowtab[IOMEM16(0x1060)], io_write_force32_1060, 1);
446 map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1);
447 map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1);
448 map_item(&mem_iowtab[IOMEM16(0x1080)], io_write_force32_1080, 1);
449 map_item(&mem_iowtab[IOMEM16(0x1088)], psxHwWriteChcr0, 1);
450 map_item(&mem_iowtab[IOMEM16(0x108c)], psxHwWriteChcr0, 1);
451 map_item(&mem_iowtab[IOMEM16(0x1090)], io_write_force32_1090, 1);
452 map_item(&mem_iowtab[IOMEM16(0x1098)], psxHwWriteChcr1, 1);
453 map_item(&mem_iowtab[IOMEM16(0x109c)], psxHwWriteChcr1, 1);
454 map_item(&mem_iowtab[IOMEM16(0x10a0)], io_write_force32_10a0, 1);
455 map_item(&mem_iowtab[IOMEM16(0x10a8)], psxHwWriteChcr2, 1);
456 map_item(&mem_iowtab[IOMEM16(0x10ac)], psxHwWriteChcr2, 1);
457 map_item(&mem_iowtab[IOMEM16(0x10b0)], io_write_force32_10b0, 1);
458 map_item(&mem_iowtab[IOMEM16(0x10b8)], psxHwWriteChcr3, 1);
459 map_item(&mem_iowtab[IOMEM16(0x10bc)], psxHwWriteChcr3, 1);
460 map_item(&mem_iowtab[IOMEM16(0x10c0)], io_write_force32_10c0, 1);
461 map_item(&mem_iowtab[IOMEM16(0x10c8)], psxHwWriteChcr4, 1);
462 map_item(&mem_iowtab[IOMEM16(0x10cc)], psxHwWriteChcr4, 1);
463 map_item(&mem_iowtab[IOMEM16(0x10e0)], io_write_force32_10e0, 1);
464 map_item(&mem_iowtab[IOMEM16(0x10e8)], psxHwWriteChcr6, 1);
465 map_item(&mem_iowtab[IOMEM16(0x10ec)], psxHwWriteChcr6, 1);
466 map_item(&mem_iowtab[IOMEM16(0x10f0)], io_write_force32_10f0, 1);
467 map_item(&mem_iowtab[IOMEM16(0x10f4)], psxHwWriteDmaIcr32, 1);
468 map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
469 map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
470 map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
471 map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
472 map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
473 map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
474 map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
475 map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
476 map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
477
478 map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
479 map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
480 map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
481 map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
482 map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
483
484 for (i = 0x1c00; i < 0x2000; i += 2) {
485 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
486 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
487 }
488
489 // misc
490 map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1);
491 map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1);
492 for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
493 map_item(&mem_ffrtab[i], read_biu, 1);
494 map_item(&mem_ffwtab[i], write_biu, 1);
495 }
496
497 mem_rtab = mem_readtab;
498 mem_wtab = mem_writetab;
499
500 new_dyna_pcsx_mem_load_state();
501}
502
503void new_dyna_pcsx_mem_reset(void)
504{
505 // plugins might change so update the pointers
506 map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
507 map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
508}
509
510void new_dyna_pcsx_mem_shutdown(void)
511{
512 psxUnmap(mem_readtab, 0x200000 * sizeof(mem_readtab[0]), MAP_TAG_LUTS);
513 mem_writetab = mem_readtab = NULL;
514}
ARM optimized PCSX fork